-
Notifications
You must be signed in to change notification settings - Fork 177
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
platform.add_clock_constraint does not work for instances with vivado #373
Comments
This comment has been minimized.
This comment has been minimized.
These are actually two separate bugs, could you please file the 2nd one as another issue? I believe that's a Tcl escaping issue. |
Alright, sorry for not keeping them seperate. |
Don't blame you--this is immediately obvious to me but it's unlikely to be so to anyone who doesn't maintain the Tcl scripts... |
Ah, #374 is yet another bug you found here :) Nice triple catch. |
There are two issues here. First, the clock net requires an attribute. This can be added with: --- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -177,6 +177,10 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
m.submodules.reset_sync = ResetSynchronizer(rst_i, domain="sync")
return m
+ def add_clock_constraint(self, clock, frequency):
+ super().add_clock_constraint(clock, frequency)
+ clock.attrs["keep"] = 1
+
def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
def get_dff(clk, d, q):
# SDR I/O is performed by packing a flip-flop into the pad IOB. Unfortunately that's not enough because Vivado doesn't consider |
Let me know if the fix works for you. It's somewhat gross but that's just what we can do with Yosys today. |
In commit 892cff0, `-decimal` was used when writing Verilog for Vivado targets because it treats (* keep=32'd1 *) and (* keep=1 *) differently in violation of Verilog LRM. However, it is possible to avoid that workaround by using (* keep="TRUE" *). Do that, and remove `-decimal` to avoid special-casing 32-bit constants. Refs #373.
For clocks coming from an instance,
platform.add_clock_constraint
doesn't seem to work, as vivado is unable to find the net that the constraint is assigned to.Running this example:
causes vivado to issue the following warning:
And the subsequent timing report is empty.
Full build directory: build.zip
This is using nmigen commit ba79b0c.
The text was updated successfully, but these errors were encountered: