We currently nudge people towards writing testbenches where the testbench modifies signals (inputs, registers) on the same edge as the edge-triggered synchronous logic (i.e. posedge for default posedge domains), but this is wrong:
testbenches written like this are susceptible to races, especially if yield Settle() is used;
VCD files produced by testbenches written like this are hard to read because changes to inputs (and, rarely, registers) made by the bench, as well as any combinatorial logic triggered by those changes, appear at the same instant of time in the waveform viewer as the changes caused by the posedge.
Migen did not suffer from the problem (1) because it had a far simpler simulator that always ordered synchronous logic after the testbench logic and had no way to advance the simulation by zero time. (However, this caused severe issues for testbench logic by making it impossible to observe combinatorial feedback; e.g. it is not possible to implement a 1-cycle FIFOInterface.read() in Migen).
Migen did suffer from the problem (2).
The text was updated successfully, but these errors were encountered:
What I think we should do is to recommend using the inactive edge of a clock domain for testbench logic. This is actually already the recommended way to use CXXRTL, for the same reason. This implies eliminating or reworking Tick as it currently exists.
There is a partial solution to issue (1) in a branch. We discussed issue (2) on IRC and it is possible that nothing needs to be done there because if the DUT was embedded in a normal module, the waveform dump would have the same problem as with the recommended way of writing testbenches.