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Inverted DiffPairs in connectors #386
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No idea. I never considered this case and the existing DSL isn't built to support it. |
@anuejn Use the vendor macro, so for Xilinx Series7 this would be [1] https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf |
The question is about the platform DSL. Of course you can always bypass the DSL, but it would be nice if we didn't have to. |
I suspect the best way to handle this (hopefully very rare!) corner case is to allow passing a tuple to |
Yup that would be quite nice :) |
Should I formulate a separate Issue as an RFC or is this enough space for discussion on that specific topic? |
Ideally an RFC would be a separate issue, though it's not that important here. (It mostly matters when there's a lot of discussion to follow, since a separate issue allows summarizing all that without forcing people to skip unnecessary context.) |
I have a board that has some inverted differential pairs broken out to a connector. The connector is used on several boards and there are daughterboards that can be plugged into those connectors.
Right now I am modeling this using the nmigen platform dsl in the following way: My board defines connectors. The add-on boards are functions which take the platform as an argument and then add the resources they hold to the connectors. For example:
In my platform i do:
Now one of the Lanes on the mainboard (not the daughterboard) is inverted (lvds3_p is connected to the negative side of the FPGAs differential buffer and vice versa to ease routing on the PCB). This raises the requirement, that I somehow need to mark pins as inverted diff pairs right in the platform and to mark single pairs of a DiffPairs Object as inverted.
How would you model this using the existing platform dsl or what would be the preferred way to extend the dsl?
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