Integer parameters over 32 bits

[dlharmon]

6e29fbc breaks integer parameters greater than 2**32 -1

With Yosys HEAD, a large integer parameter results in the error nmigen.back.verilog.YosysError: ERROR: Parser error in line 247: syntax error, with older Yosys, the parameter is silently clipped to 2**32-1.

I'm not sure what the best way to handle this is. It could be as simple as converting large integer parameters to ast.Const parameters. Even an assert to catch this early may be an option.

[whitequark]

I'm not sure what the best way to handle this is.

Plain integers used as parameters in RTLIL are equivalent to 32-bit constants, so we can convert them on nMigen's side without loss of generality.

[whitequark]

breaks integer parameters greater than 2**32 -1

with older Yosys, the parameter is silently clipped to 2**32-1.

I think it's even worse than this. Consider this RTLIL:

module \foo
	attribute \init 2147483647
	wire width 64 \2**31-1
	#attribute \init 2147483648
	#wire width 64 \2**31
	attribute \init -2147483647
	wire width 64 \-2**31+1
	attribute \init -2147483648
	wire width 64 \-2**31
end

If you convert it to Verilog, Yosys outputs:

module foo();
  (* init = 32'd2147483648 *)
  wire [63:0] \-2**31 ;
  (* init = 32'd2147483649 *)
  wire [63:0] \-2**31+1 ;
  (* init = 32'd2147483647 *)
  wire [63:0] \2**31-1 ;
endmodule

So it's discarding the sign bit! And not only that but you can't even specify any values between 2**31 and 2**32-1 inclusive, even though you ought to be able to.

[whitequark]

Looking closer, it seems that negative numbers in RTLIL don't roundtrip:

module \foo
  attribute \init 32'10000000000000000000000000000000
  wire width 64 \-2**31
  attribute \init 32'10000000000000000000000000000001
  wire width 64 \-2**31+1
  attribute \init 2147483647
  wire width 64 \2**31-1
end

[whitequark]

Proposed upstream fix: YosysHQ/yosys#2066