Better diagnostics for undefined domain usage

[matthuszagh]

When an undefined domain is used, nmigen issues an appropriate error, but does not specify the source line that triggered the error. Take the following example:

#!/usr/bin/env python

from nmigen.vendor.xilinx_7series import Xilinx7SeriesPlatform
from nmigen import Elaboratable, Signal, Module
from nmigen.build import Resource, Pins, Clock, Attrs


class Plat(Xilinx7SeriesPlatform):
    device = "XC7A15T"
    package = "FTG256"
    speed = "1"
    resources = [
        Resource(
            "clk40",
            0,
            Pins("N11", dir="i"),
            Clock(40e6),
            Attrs(IOSTANDARD="LVCMOS33"),
        ),
    ]
    connectors = []
    default_clk = "clk40"


class Demo(Elaboratable):
    def elaborate(self, platform):
        m = Module()
        a = Signal()
        m.d.clk += a.eq(1)
        return m


if __name__ == "__main__":
    platform = Plat()
    platform.build(Demo())

On my system, this gives the error:

Traceback (most recent call last):
  File "./file.py", line 35, in <module>
    platform.build(Demo())
  File "/nix/store/f29xvgxh94qcv0v1sd438928yix5hfwm-python3-3.7.7-env/lib/python3.7/site-packages/nmigen/build/plat.py", line 78, in build
    plan = self.prepare(elaboratable, name, **kwargs)
  File "/nix/store/f29xvgxh94qcv0v1sd438928yix5hfwm-python3-3.7.7-env/lib/python3.7/site-packages/nmigen/build/plat.py", line 120, in prepare
    fragment._propagate_domains(self.create_missing_domain, platform=self)
  File "/nix/store/f29xvgxh94qcv0v1sd438928yix5hfwm-python3-3.7.7-env/lib/python3.7/site-packages/nmigen/hdl/ir.py", line 380, in _propagate_domains
    new_domains = self._create_missing_domains(missing_domain, platform=platform)
  File "/nix/store/f29xvgxh94qcv0v1sd438928yix5hfwm-python3-3.7.7-env/lib/python3.7/site-packages/nmigen/hdl/ir.py", line 358, in _create_missing_domains
    raise DomainError("Domain '{}' is used but not defined".format(domain_name))
nmigen.hdl.cd.DomainError: Domain 'clk' is used but not defined

It might be nice if the error included a message stating that line 29 (m.d.clk += a.eq(1)) was the offender.

[whitequark]

This isn't currently very easy to implement, but a good thing to keep in mind for the future.