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If a module uses a ResetSignal(allow_reset_less=True) on a clock domain which is later renamed into a reset-less domain, the ResetSignal still refers to the now non-existent reset:
from nmigen import (Elaboratable, Module, Signal, ResetSignal, ClockDomain, DomainRenamer) from nmigen.back import verilog class Mod(Elaboratable): def __init__(self): self.x = Signal() def elaborate(self, platform): m = Module() s = ResetSignal(domain="x", allow_reset_less=True) m.d.comb += self.x.eq(s) return m class Top(Elaboratable): def elaborate(self, platform): m = Module() # Change reset_less=False to fix cd_y = ClockDomain("y", reset_less=True) m.domains += cd_y m.submodules += DomainRenamer({"x": "y"})(Mod()) return m if __name__ == "__main__": verilog.convert(Top())
<very long traceback snip> nmigen.hdl.cd.DomainError: Signal (rst y) refers to reset of reset-less domain 'y'
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If a module uses a ResetSignal(allow_reset_less=True) on a clock domain which is later renamed into a reset-less domain, the ResetSignal still refers to the now non-existent reset:
The text was updated successfully, but these errors were encountered: