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Records don't work in Assert #403

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BracketMaster opened this issue Jun 13, 2020 · 5 comments
Closed

Records don't work in Assert #403

BracketMaster opened this issue Jun 13, 2020 · 5 comments
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@BracketMaster
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@BracketMaster BracketMaster commented Jun 13, 2020

You can't don Assert on records.
The following will fail in elaboration.

from nmigen import *
from nmigen.asserts import Assert

rec = Record([("sig1", 3), ("sig2", 3)])
Assert(rec == 3)
@whitequark whitequark added the bug label Jun 13, 2020
@whitequark
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@whitequark whitequark commented Nov 7, 2020

Works for me on latest nMigen:

from nmigen import *
from nmigen.asserts import Assert
from nmigen.back import verilog

rec = Record([("sig1", 3), ("sig2", 3)])
m = Module()
m.d.sync += Assert(rec == 3)
print(verilog.convert(m))

Can you please confirm?

@BracketMaster
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@BracketMaster BracketMaster commented Nov 7, 2020

Seems fine. I'm honestly not sure what I was trying to
do in the original issue. Its been four months haha.

@rroohhh
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@rroohhh rroohhh commented Nov 7, 2020

Due to #533, while it works it probably does not produce what one expects:

>>> from nmigen import *
>>> from nmigen.asserts import Assert
>>>
>>> rec = Record([("sig1", 3), ("sig2", 3)])
>>> Assert(rec == 3)
(assert (const 1'd0))

@whitequark whitequark reopened this Nov 7, 2020
@whitequark
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@whitequark whitequark commented Nov 7, 2020

@rroohhh Thanks for noticing!

@rroohhh
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@rroohhh rroohhh commented Nov 9, 2020

Should be fixed by #541 now:

>>> from nmigen import *
>>> from nmigen.asserts import Assert
>>> rec = Record([("sig1", 3), ("sig2", 3)])
>>> Assert(rec == 3)
(assert (== (cat (sig rec__sig1) (sig rec__sig2)) (const 2'd3)))
>>>

and

from nmigen import *
from nmigen.asserts import Assert
from nmigen.back import verilog

rec = Record([("sig1", 3), ("sig2", 3)])
m = Module()
m.d.sync += Assert(rec == 3)
print(verilog.convert(m))
/* Generated by Yosys 0.9+3477 (git sha1 UNKNOWN, g++ 7.5.0 -fPIC -Os) */

(* \nmigen.hierarchy  = "top" *)
(* top =  1  *)
(* generator = "nMigen" *)
module top(rec__sig2, rst, clk, rec__sig1);
  reg \initial  = 0;
  (* src = "/data/projects/nmigen/nmigen/hdl/rec.py:255" *)
  wire \$1 ;
  (* src = "<stdin>:1" *)
  reg \$assert$check  = 1'h0;
  (* src = "<stdin>:1" *)
  reg \$assert$check$next ;
  (* src = "<stdin>:1" *)
  reg \$assert$en  = 1'h0;
  (* src = "<stdin>:1" *)
  reg \$assert$en$next ;
  (* src = "/data/projects/nmigen/nmigen/hdl/ir.py:526" *)
  input clk;
  (* src = "<stdin>:1" *)
  input [2:0] rec__sig1;
  (* src = "<stdin>:1" *)
  input [2:0] rec__sig2;
  (* src = "/data/projects/nmigen/nmigen/hdl/ir.py:526" *)
  input rst;
  assign \$1  = { rec__sig2, rec__sig1 } == (* src = "/data/projects/nmigen/nmigen/hdl/rec.py:255" *) 2'h3;
  always @* if (\$assert$en ) assert(\$assert$check );
  always @(posedge clk)
    \$assert$en  <= \$assert$en$next ;
  always @(posedge clk)
    \$assert$check  <= \$assert$check$next ;
  always @* begin
    if (\initial ) begin end
    \$assert$en$next  = \$assert$en ;
    \$assert$check$next  = \$assert$check ;
    \$assert$check$next  = \$1 ;
    \$assert$en$next  = 1'h1;
  end
endmodule

@whitequark whitequark closed this Nov 9, 2020
@whitequark whitequark added this to the 0.3 milestone Nov 24, 2020
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