Error accessing ResetSignal() #415
Comments
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Btw, here's the full output when I run And when I run it with |
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Are there any workarounds for this, or can simulations just never toggle reset currently? |
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@bhansconnect you can do something like this: from nmigen import *
from nmigen.back import pysim
class Issue(Elaboratable):
def __init__(self):
self.rst = Signal()
self.a = Signal()
def elaborate(self, platform):
m = Module()
m.d.comb += ResetSignal().eq(self.rst)
with m.If(self.rst):
m.d.sync += self.a.eq(1)
return m
if __name__ == "__main__":
dut = Issue()
sim = pysim.Simulator(Issue())
sim.add_clock(1.0 / 12e6)
def test():
yield dut.rst.eq(1)
yield
yield dut.rst.eq(0)
yield
sim.add_sync_process(test)
with sim.write_vcd("issue.vcd", "issue.gtkw", traces=[dut.rst]):
sim.run() |
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That does work, thanks. |
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@bhansconnect, @GuzTech from nmigen import Elaboratable, Module, ResetSignal, Signal
from nmigen.sim import Simulator
from nmigen.cli import main
class Issue(Elaboratable):
def __init__(self):
self.rst = Signal()
self.a = Signal(reset=1)
def elaborate(self, platform):
m = Module()
m.d.comb += ResetSignal().eq(self.rst)
m.d.sync += self.a.eq(0)
return m
if __name__ == "__main__":
dut = Issue()
simulate = True
if simulate:
sim = Simulator(dut)
sim.add_clock(1.0 / 12e6)
def test():
yield
yield dut.rst.eq(1)
yield
yield dut.rst.eq(0)
yield
sim.add_sync_process(test)
with sim.write_vcd("issue.vcd", "issue.gtkw", traces=[dut.a, dut.rst]):
sim.run()
else:
main(dut, ports=[dut.a])Which will get you: module top(clk, rst, a);
reg \initial = 0;
output a;
reg a = 1'h1;
reg \a$next ;
input clk;
output rst; // rst became an output!
wire \rst$1 ;
always @(posedge clk)
a <= \a$next ;
always @* begin
if (\initial ) begin end
\a$next = 1'h0;
casez (rst)
1'h1:
\a$next = 1'h1;
endcase
end
assign \rst$1 = 1'h0;
assign rst = 1'h0; // rst is hardwired to 0
endmoduleThe most noteable here is that rst became an output, generating a driver-driver conflict with the connected module which is actually supposed to drive rst. |
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@bhansconnect, @GuzTech from nmigen import Elaboratable, Module, ResetSignal, Signal
from nmigen.sim import Simulator
from nmigen.cli import main
class Issue(Elaboratable):
def __init__(self):
self.reset = Signal()
self.a = Signal(reset=1, reset_less=True)
def elaborate(self, platform):
m = Module()
with m.If(self.reset):
m.d.sync += self.a.eq(1)
with m.Else():
m.d.sync += self.a.eq(0)
return mbut while this works in the simulator as above, the verilog file shows: module top(reset, clk, rst, a);
reg \initial = 0;
output a;
reg a = 1'h1;
reg \a$next ;
input clk;
input reset;
input rst;
always @(posedge clk)
a <= \a$next ;
always @* begin
if (\initial ) begin end
casez (reset)
/* src = "issue-fix.py:13" */
1'h1:
\a$next = 1'h1;
/* src = "issue-fix.py:15" */
default:
\a$next = 1'h0;
endcase
end
endmodulewhich looks useable, with the wart that |
I want to toggle the reset signal of a module in simulation, but I get an error that do not quite understand. Here is a simple example:
This gives me the error
AttributeError: 'ResetSignal' object has no attribute 'name'.If I change it to
traces=[dut.a], then I get the errorAttributeError: 'ResetSignal' object has no attribute 'reset'.The text was updated successfully, but these errors were encountered: