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Wrong timestep with mixed clock edge ticks within pysim #440

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kruemelkeks opened this issue Jul 19, 2020 · 2 comments
Closed

Wrong timestep with mixed clock edge ticks within pysim #440

kruemelkeks opened this issue Jul 19, 2020 · 2 comments

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@kruemelkeks
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kruemelkeks commented Jul 19, 2020

Take a module with a positive and a negative sensitive clock edge and excite it with pysim. When changing from Tick('sync_neg') to Tick('sync') the expected half cycle is added, but after a consecutive Tick('sync') the simulator also only runs another half cycle instead of a full one.

This behaviour can be observed since 2efeb05.
An example reproducing the mentioned issue:

from nmigen import *
from nmigen.back.pysim import *

m = Module()
m.domains += ClockDomain('sync_neg', clk_edge='neg')
m.d.comb += ClockSignal('sync_neg').eq(ClockSignal('sync'))

a = Signal()
b = Signal()
m.d.sync += a.eq(1)
m.d.sync_neg += b.eq(1)

sim = Simulator(m)
sim.add_clock(1e-6, domain='sync')

def process():
    yield Tick('sync_neg') # <- ok
    yield Tick('sync') # <- ok
    yield Tick('sync') # <- wrong

sim.add_sync_process(process)
with sim.write_vcd("test.vcd", "test.gtkw", traces=[]):
    sim.run()
@whitequark
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whitequark commented Jul 22, 2020

I believe this has been fixed in commit 58f1d4b. Please check with the latest master.

@whitequark
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whitequark commented Jul 22, 2020

I've also discovered another simulator bug based on your testcase. It is fixed in commit 1321c45.

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