Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

PS7 block not initialized on series-7 Zynq targets #441

Closed
DaKnig opened this issue Jul 19, 2020 · 10 comments
Closed

PS7 block not initialized on series-7 Zynq targets #441

DaKnig opened this issue Jul 19, 2020 · 10 comments

Comments

@DaKnig
Copy link

@DaKnig DaKnig commented Jul 19, 2020

I'm using Vivado 2019.2, with the artix z7 board. Vivado spits this warning:

WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.

this should be simple enough to fix in verilog, but I don't know how to fix that in nMigen.

@whitequark
Copy link
Member

@whitequark whitequark commented Jul 20, 2020

Try something like:

m.submodules += Instance("PS7")

@whitequark
Copy link
Member

@whitequark whitequark commented Jul 22, 2020

Did this work for you?

@DaKnig
Copy link
Author

@DaKnig DaKnig commented Jul 23, 2020

it did not.

@whitequark
Copy link
Member

@whitequark whitequark commented Jul 23, 2020

Right, there's likely a bug in the RTLIL backend that prevents this from working. I'll take a look.

@rroohhh
Copy link
Contributor

@rroohhh rroohhh commented Jul 23, 2020

From IRC:

[11:45:03] <vup> this seems to be the problematic line: https://github.com/nmigen/nmigen/blob/7aedb3e77045e865ea8e676b4a6616d03599a3ad/nmigen/back/rtlil.py#L858-L859 Considering Instances could be nested arbitrarily deep inside submodules without any ports this doesn't seem correct

@whitequark
Copy link
Member

@whitequark whitequark commented Jul 23, 2020

@rroohhh Ah right, so the problem that 9faa1d3 was fixing is that Yosys treats empty modules as black boxes by default. Maybe they should contain a dummy wire instead or something.

@whitequark
Copy link
Member

@whitequark whitequark commented Jul 23, 2020

Now that I think again about it, this might be a Yosys bug.

@DaKnig
Copy link
Author

@DaKnig DaKnig commented Jul 23, 2020

from a question on the xilinx forums, it seems like putting a dummy with all the wires connected to some values (or disconnected- open in vhdl) should solve the issue. I am not sure this is optimal- this means many many lines of code for this one small problem.

@andresdemski
Copy link

@andresdemski andresdemski commented Aug 22, 2020

Try something like:

m.d.submodules += Instance("PS7")

I think the PS7 is removed during the synthesis.

Try adding the attribute DONT_TOUCH:

m.d.submodules += Instance("PS7", a_DONT_TOUCH="true")

I use it with PS8 for ZynqMP and it works. https://github.com/satellogic/nmigen-zynq/blob/89c0c87801f3a6d5f2059b9af88c39231e24d41d/nmigen_zynq/ps.py#L119

@rroohhh
Copy link
Contributor

@rroohhh rroohhh commented Aug 22, 2020

@andresdemski it is actually omitted by nmigen if it doesn't have any ports, so simply adding a attribute is not enough. See my comment here and the source code snippet linked to in there.

@whitequark whitequark added this to the 0.3 milestone Aug 26, 2020
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Linked pull requests

Successfully merging a pull request may close this issue.

None yet
4 participants