I'm not sure what division synthesizes to in Yosys in general, or if it supports the general case at all, but it seems that on the nMigen side we can now emit $divfloor and fully support division with correct semantics. I'd be happy to put together a PR for this at some point.
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Reasonable. I think we might want to wait until there's a Yosys release, because we can't shim over the lack of $divfloor in older Yosys in back.verilog, like we do for other Yosys-related variability.
The verilog backend in that commit (which I do not claim to fully understand) does seem to "shim" over the lack of flooring division in Verilog, so I think it might technically be possible to work around it, but I agree waiting for a Yosys release is easier. Bit unfortunate that Yosys releases are not exactly frequent.
I think it might technically be possible to work around it
I guess you could, when targeting older Yosys, always provide a $divfloor cell as a part of nmigen.back.verilog, and then immediately flattening it, so that it never actually appears in output Verilog. But it's not clear that the effort is justified.