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assignment not respecting RHS signedness #502

programmerjake opened this issue Oct 6, 2020 · 1 comment

assignment not respecting RHS signedness #502

programmerjake opened this issue Oct 6, 2020 · 1 comment


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I'm using nmigen commit 69ed491

I expect nmigen to behave more like most other programming languages in that when converting from a smaller RHS type to a larger LHS type, the sign/zero extension is decided based on the RHS. The expected behavior matches what was decided for #464


from nmigen import Signal, Module, signed, unsigned, Const
from nmigen.sim import Simulator, Delay

m = Module()
inp = Signal(unsigned(8))
out = Signal(unsigned(16))

m.d.sync += out.eq(inp.as_signed())

sim = Simulator(m)


def process():
    yield inp.eq(0xFF)
    inp_v = yield inp
    expected = Const.normalize(inp_v, signed(8))
    expected = Const.normalize(expected, unsigned(16))
    out_v = yield out
    print(hex(inp_v), hex(expected), hex(out_v))
    assert expected == out_v



0xff 0xffff 0xff
Traceback (most recent call last):
  File "", line 26, in <module>
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/", line 165, in run
    while self.advance():
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/", line 156, in advance
    return self._engine.advance()
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/", line 315, in advance
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/", line 304, in _step
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/", line 123, in run
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/", line 64, in run
    command = self.coroutine.send(response)
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/", line 90, in wrapper
    yield from process()
  File "", line 23, in process
    assert expected == out_v

Expected output:

0xff 0xffff 0xffff
@whitequark whitequark added the bug label Oct 6, 2020
@whitequark whitequark added this to the 0.3 milestone Oct 6, 2020
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@programmerjake I believe this is actually a sim/synth mismatch, since it translates to the following Verilog:

module top(inp);
  wire [15:0] \$1 ;
  input [7:0] inp;
  wire [15:0] out;
  assign \$1  = + $signed(inp);
  assign out = \$1 ;

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