assignment not respecting RHS signedness

[programmerjake]

I'm using nmigen commit 69ed491

I expect nmigen to behave more like most other programming languages in that when converting from a smaller RHS type to a larger LHS type, the sign/zero extension is decided based on the RHS. The expected behavior matches what was decided for #464

Code:

from nmigen import Signal, Module, signed, unsigned, Const
from nmigen.sim import Simulator, Delay

m = Module()
inp = Signal(unsigned(8))
out = Signal(unsigned(16))

m.d.sync += out.eq(inp.as_signed())

sim = Simulator(m)

sim.add_clock(1e-6)

def process():
    yield inp.eq(0xFF)
    yield
    yield
    inp_v = yield inp
    expected = Const.normalize(inp_v, signed(8))
    expected = Const.normalize(expected, unsigned(16))
    out_v = yield out
    print(hex(inp_v), hex(expected), hex(out_v))
    assert expected == out_v

sim.add_sync_process(process)
sim.run()

Output:

0xff 0xffff 0xff
Traceback (most recent call last):
  File "nmigen-bug.py", line 26, in <module>
    sim.run()
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/core.py", line 165, in run
    while self.advance():
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/core.py", line 156, in advance
    return self._engine.advance()
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/pysim.py", line 315, in advance
    self._step()
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/pysim.py", line 304, in _step
    process.run()
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/_pycoro.py", line 123, in run
    self.coroutine.throw(exn)
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/_pycoro.py", line 64, in run
    command = self.coroutine.send(response)
  File "/home/jacob/projects/libreriscv/nmigen/nmigen/sim/core.py", line 90, in wrapper
    yield from process()
  File "nmigen-bug.py", line 23, in process
    assert expected == out_v
AssertionError

Expected output:

0xff 0xffff 0xffff

[whitequark]

@programmerjake I believe this is actually a sim/synth mismatch, since it translates to the following Verilog:

module top(inp);
  wire [15:0] \$1 ;
  input [7:0] inp;
  wire [15:0] out;
  assign \$1  = + $signed(inp);
  assign out = \$1 ;
endmodule