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For the Stratix IV PLL (I assume it also applies to altpll in general), the input clock can't be driven by a combinational block. When instantiating a PLL, I can't find any way of driving it directly from the input pin. Using platform.request() explicitly creates a module with an altiobuf, which confuses quartus by placing buffers that get synthesised as combinational blocks (LUTs) in the clock path.
Ah my bad: I sort of changed what I was asking halfway through, I should edit the original question to make it a bit more clear. Basically I'm asking how you would do this on a platform with one clock: if the sync domain has already requested the default clock ("clk50", 0), how would one go about using that clock input directly (ie without an iobuf)?