You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
So, Verilog doesn't support arrays on ports, only vectors. The best way to get around this limitation in Verilog, in my opinion, is to encode the array into a vector. This works even for Arrays of Records.
I suggest perhaps making a PackedArray class (like in SV), derived from Value, that takes a shape and a size. I believe this would also solve the issue of not being able to place an Array inside of a Record.
I'll work on developing an example of it.
The text was updated successfully, but these errors were encountered:
I don't think that any changes related to Records should be done before the Record redesign (#342). In general, I would prefer to enable you to use ValueCastable to do this change localized in your codebase than to add it to the core language.