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For designs that want to be as platform-independent as possible, it would be nice to have access to the total latency from the design to the physical IO in IO buffer clocks. This way IOs of different XDR ratios can be synchronized.
Update: the undocumented nature of the latency is now clearly stated in the docs, but at least the relevant intervals are now clearly defined. In practice:
t1 is either 3 (on Lattice platforms; excluding SiliconBlue iCE40) or 1 (other platforms).
For designs that want to be as platform-independent as possible, it would be nice to have access to the total latency from the design to the physical IO in IO buffer clocks. This way IOs of different XDR ratios can be synchronized.
Followup from #532.
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