Closed as not planned
Closed as not planned
Description
I have the following simulator configuration:
receiver = ADATReceiver()
clk_freq = 120e6
# 24 bit plus the 6 nibble separator bits for eight channel
# then 1 separator, 10 sync bits (zero), 1 separator and 4 user bits
adat_freq = 48000 * ((24 + 6) * 8 + 1 + 10 + 1 + 4)
clockratio = clk_freq / adat_freq
sim = Simulator(receiver)
sim.add_clock(1.0/clk_freq, domain="sync")
sim.add_clock(1.0/adat_freq, domain="adat")
print(f"clock ratio: {clockratio}")
cycles = 10
def sync_process():
for _ in range(int(clockratio) * cycles):
yield Tick("sync")
def adat_process():
testdata = one_empty_adat_frame() + generate_sixteen_frames_with_channel_numbers_in_most_significant_nibble_and_sample_numbers_in_sample()
for bit in testdata[224:512 * 2]:
yield receiver.adat_in.eq(bit)
yield Tick("adat") # if I don't put this here, the adat signal is constant zero
sim.add_sync_process(sync_process, domain="sync")
sim.add_sync_process(adat_process, domain="adat")
with sim.write_vcd('receiver-smoke-test.vcd', traces=[receiver.adat_in, receiver.clk_in, receiver.adat_clk_in]):
sim.run()
When I simulate this, I have strange parts, where the clock of domain sync seems to pause,
but at the same time a counter in that domain seems to speed up:
What is going on here? Am I using the simulator in a wrong way, or is this a bug in the simulator?