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write_cfgmem is writing to arty board when not specified to in the code #558
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I think the issue is that Two possible fixes that come to mind:
The first option seems conceptually a bit nicer to me, but would mean writing and running a second .tcl file, so might be more work. |
afaik, |
It is needed to change the endianness of every 4 byte group with respect to what |
@nfbraun Do you have any insight on fixing this bug? I'm not familiar with Xilinx's deployment tools. |
I guess FPGA Manager is not normally involved in programming non-Zynq 7 Series FPGAs, so maybe restore the old behavior for non-Zynqs? |
Hm. I guess we could make the |
Either that, or just put the whole |
That would break all existing board definitions, no? Since |
As far as I can see, the board definitions for various Artix-7 boards (e.g. https://github.com/nmigen/nmigen-boards/blob/master/nmigen_boards/arty_a7.py) already have a So I guess I added the |
I would suggest to revert #523. I have opened a PR in nmigen-boards for a ZedBoard config that fixes #519 (for the ZedBoard) without affecting other devices: amaranth-lang/amaranth-boards#135. The board configs for other Zynq boards would have to add something similar. @rachsug: Can you confirm that reverting commit |
I strongly suspect there will come a case where our default |
Yep, @rachsug and I both locally reverted that commit and it did indeed fix the problem. Thanks |
@whitequark: not sure if I understand correctly... AFAIK, there was no |
I believe this is no longer an issue after reverting #523. Please comment if there is anything that still needs to be done here. |
Trying to generate a bitstream from nmigen for the arty board. The output finishes with this error:
Seems to try to write to arty board when it has not been coded to.
Here is the code that produces this error:
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