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cxxsim: error when reading unused combinatorial signal #568

cestrauss opened this issue Dec 27, 2020 · 1 comment

cxxsim: error when reading unused combinatorial signal #568

cestrauss opened this issue Dec 27, 2020 · 1 comment


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As of this latest Yosys commit (master branch):

commit d30063ea652eba11a0319a1e29e16ac72f814224 (HEAD -> master, origin/master, origin/HEAD)
Merge: af457ce8 cb228338
Author: Claire Xen <>
Date:   Sun Dec 27 16:33:58 2020 +0100

    Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS-verilog-ast

... and this latest nMigen commit (cxxsim branch):

commit ce8ccdc487a9356d7bb0e3903037bb9232c47a5c (HEAD -> cxxsim, origin/cxxsim)
Author: whitequark <>
Date:   Sun Dec 20 11:00:59 2020 +0000

    sim.cxxsim: add function tracing facility.

...this code:

from nmigen import Signal, Module
from nmigen.sim import Simulator

m = Module()
o = Signal()
m.d.comb += o.eq(1)

def process():
    print((yield o))

sim = Simulator(m, engine="cxxsim")

... produces this error:

$ python 
/home/cstrauss/src/nmigen/nmigen/sim/ YosysWarning: The `-Og` option has been removed. Use `-g3` instead for complete design coverage regardless of optimization level.
  cxx_source, name_map = cxxrtl.convert_fragment(fragment)
Traceback (most recent call last):
  File "/home/cstrauss/src/nmigen/nmigen/sim/", line 138, in get_signal
    index = self.rtl_signals[signal]
  File "/home/cstrauss/src/nmigen/nmigen/hdl/", line 1561, in __getitem__
    return self._storage[key]
KeyError: <nmigen.hdl.ast.SignalKey (sig o)>

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "", line 15, in <module>
  File "/home/cstrauss/src/nmigen/nmigen/sim/", line 168, in run
    while self.advance():
  File "/home/cstrauss/src/nmigen/nmigen/sim/", line 159, in advance
    return self._engine.advance()
  File "/home/cstrauss/src/nmigen/nmigen/sim/", line 260, in advance
  File "/home/cstrauss/src/nmigen/nmigen/sim/", line 250, in _step
  File "/home/cstrauss/src/nmigen/nmigen/sim/", line 123, in run
  File "/home/cstrauss/src/nmigen/nmigen/sim/", line 84, in wrapper
    yield from process()
  File "", line 10, in process
    print((yield o))
  File "/home/cstrauss/src/nmigen/nmigen/sim/", line 70, in run
    exec(_RHSValueCompiler.compile(self.state, command, mode="curr"),
  File "/home/cstrauss/src/nmigen/nmigen/sim/", line 239, in compile
    emitter.append(f"result = {compiler(value)}")
  File "/home/cstrauss/src/nmigen/nmigen/hdl/", line 127, in __call__
    return self.on_value(value)
  File "/home/cstrauss/src/nmigen/nmigen/hdl/", line 96, in on_value
    new_value = self.on_Signal(value)
  File "/home/cstrauss/src/nmigen/nmigen/sim/", line 108, in on_Signal
    return f"slots[{self.state.get_signal(value)}].{self.mode}"
  File "/home/cstrauss/src/nmigen/nmigen/sim/", line 140, in get_signal
    index = self._add_rtl_signal(signal)
  File "/home/cstrauss/src/nmigen/nmigen/sim/", line 110, in _add_rtl_signal
    assert all(part.type == signal_parts[0].type for part in signal_parts)
TypeError: 'NoneType' object is not iterable

I didn't bisect, so this regression can possibly have been introduced in earlier commits.

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Seems to be fixed now.
Amaranth cxxsim branch (1c0cf92)
Yosys 0.12+45 (git sha1 cfe940a98, clang 7.0.1-8+deb10u2 -fPIC -Os)

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