Closed
Description
As of this latest Yosys commit (master branch):
commit d30063ea652eba11a0319a1e29e16ac72f814224 (HEAD -> master, origin/master, origin/HEAD)
Merge: af457ce8 cb228338
Author: Claire Xen <claire@symbioticeda.com>
Date: Sun Dec 27 16:33:58 2020 +0100
Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS-verilog-ast
... and this latest nMigen commit (cxxsim branch):
commit ce8ccdc487a9356d7bb0e3903037bb9232c47a5c (HEAD -> cxxsim, origin/cxxsim)
Author: whitequark <whitequark@whitequark.org>
Date: Sun Dec 20 11:00:59 2020 +0000
sim.cxxsim: add function tracing facility.
...this code:
from nmigen import Signal, Module
from nmigen.sim import Simulator
m = Module()
o = Signal()
m.d.comb += o.eq(1)
def process():
print((yield o))
sim = Simulator(m, engine="cxxsim")
sim.add_process(process)
sim.run()... produces this error:
$ python bug24.py
/home/cstrauss/src/nmigen/nmigen/sim/cxxsim.py:198: YosysWarning: The `-Og` option has been removed. Use `-g3` instead for complete design coverage regardless of optimization level.
cxx_source, name_map = cxxrtl.convert_fragment(fragment)
Traceback (most recent call last):
File "/home/cstrauss/src/nmigen/nmigen/sim/cxxsim.py", line 138, in get_signal
index = self.rtl_signals[signal]
File "/home/cstrauss/src/nmigen/nmigen/hdl/ast.py", line 1561, in __getitem__
return self._storage[key]
KeyError: <nmigen.hdl.ast.SignalKey (sig o)>
During handling of the above exception, another exception occurred:
Traceback (most recent call last):
File "bug24.py", line 15, in <module>
sim.run()
File "/home/cstrauss/src/nmigen/nmigen/sim/core.py", line 168, in run
while self.advance():
File "/home/cstrauss/src/nmigen/nmigen/sim/core.py", line 159, in advance
return self._engine.advance()
File "/home/cstrauss/src/nmigen/nmigen/sim/cxxsim.py", line 260, in advance
self._step()
File "/home/cstrauss/src/nmigen/nmigen/sim/cxxsim.py", line 250, in _step
process.run()
File "/home/cstrauss/src/nmigen/nmigen/sim/_pycoro.py", line 123, in run
self.coroutine.throw(exn)
File "/home/cstrauss/src/nmigen/nmigen/sim/core.py", line 84, in wrapper
yield from process()
File "bug24.py", line 10, in process
print((yield o))
File "/home/cstrauss/src/nmigen/nmigen/sim/_pycoro.py", line 70, in run
exec(_RHSValueCompiler.compile(self.state, command, mode="curr"),
File "/home/cstrauss/src/nmigen/nmigen/sim/_pyrtl.py", line 239, in compile
emitter.append(f"result = {compiler(value)}")
File "/home/cstrauss/src/nmigen/nmigen/hdl/xfrm.py", line 127, in __call__
return self.on_value(value)
File "/home/cstrauss/src/nmigen/nmigen/hdl/xfrm.py", line 96, in on_value
new_value = self.on_Signal(value)
File "/home/cstrauss/src/nmigen/nmigen/sim/_pyrtl.py", line 108, in on_Signal
return f"slots[{self.state.get_signal(value)}].{self.mode}"
File "/home/cstrauss/src/nmigen/nmigen/sim/cxxsim.py", line 140, in get_signal
index = self._add_rtl_signal(signal)
File "/home/cstrauss/src/nmigen/nmigen/sim/cxxsim.py", line 110, in _add_rtl_signal
assert all(part.type == signal_parts[0].type for part in signal_parts)
TypeError: 'NoneType' object is not iterable
I didn't bisect, so this regression can possibly have been introduced in earlier commits.