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I'm using nmigen 6ce2b21 and Yosys 0.9+3521 (git sha1 4f2b78e1, clang 6.0.0-1ubuntu2 -fPIC -Os).
When a signal is assigned to by a single comb statement, I end up with 1'hx = 1'hx; in the output Verilog, which breaks some other tools (specifically, it works for me with yosys+nextpnr-ecp5, but fails in Diamond). I'm using LatticeECP5Platform in the actual code (but the issue is still present in the reproduction below); the generated yosys script does include delete w:$verilog_initial_trigger.
I'm using nmigen 6ce2b21 and Yosys 0.9+3521 (git sha1 4f2b78e1, clang 6.0.0-1ubuntu2 -fPIC -Os).
When a signal is assigned to by a single comb statement, I end up with
1'hx = 1'hx;
in the output Verilog, which breaks some other tools (specifically, it works for me with yosys+nextpnr-ecp5, but fails in Diamond). I'm usingLatticeECP5Platform
in the actual code (but the issue is still present in the reproduction below); the generated yosys script does includedelete w:$verilog_initial_trigger
.Repro:
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