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I struggle to find an documentation or tutorial on how to integrate a design with the bus (such as AXI or Wishbone), and whether there is an option to automatically generate status and control registers.
I have found in https://github.com/m-labs/misoc README that there used to be some kind of "automatic CSR maps" but it also misses to point to the source.
Is it possible to automatically generate control/status registers with nmigen?
If yes, is there any tutorial on how to do that?
The text was updated successfully, but these errors were encountered:
I struggle to find an documentation or tutorial on how to integrate a design with the bus (such as AXI or Wishbone), and whether there is an option to automatically generate status and control registers.
I have found in https://github.com/m-labs/misoc README that there used to be some kind of "automatic CSR maps" but it also misses to point to the source.
Is it possible to automatically generate control/status registers with nmigen?
If yes, is there any tutorial on how to do that?
The text was updated successfully, but these errors were encountered: