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Yosys assertion when converting SyncFIFO #617
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Please report this against Yosys, |
from the yosys issue:
It seems like we should reflect this in the nMigen Memory / FIFO? |
Fixed on the yosys side, sorry for the mess (this issue will only affect yosys master compiled within the last 9 days). |
We should also set |
Verilog frontend uses 0, hence my expectation in the check. However, I don't see a point of changing this — I explicitely don't want to break compatibility with old RTLIL inputs and |
Alright. |
closing this as it is fixed upstream :) |
SyncFIFO
cant be used with recent yosys anymore.Probably related to YosysHQ/yosys@c707649 ?
repro:
results in:
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