Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Clock signal jumps two states with one edge #625

Closed
AlanVek opened this issue Aug 11, 2021 · 3 comments
Closed

Clock signal jumps two states with one edge #625

AlanVek opened this issue Aug 11, 2021 · 3 comments
Labels

Comments

@AlanVek
Copy link

AlanVek commented Aug 11, 2021

I'm trying to create a module that receives two wires and retrieves a clock signal from them as clk2 = w1^w2 to drive said module's FSM. w1 is driven from sync, w2 is driven from comb. The issue I'm having is that I can see clk2 and it's exactly the same as the original clock, but when w2 maintains the same value for more than one clock period, the clock edge in that period acts as two fast edges, making the FSM jump two states instead of one.

I have a test case in this repository. https://github.com/AlanVek/nMigen-Cocotb-bug

Please, let me know if I wasn't clear enough with the explanation. Thank you.

Here are some images with the outputs of the test case. The signal "counter", which should be incremented by one in each state, is sometimes incremented by two. And those glitches coincide with the edge in which w1 is changing and w2 is stable.

Bug_counter
Bug_waveform

@whitequark
Copy link
Member

whitequark commented Aug 11, 2021

Neither the nMigen language nor the FPGA synthesis toolchains guarantee that clocks generated with logic in this way are glitchless. In other words, the behavior you're seeing is not a bug, but an allowed interpretation of the language semantics.

If you give a bit more detail about the problem you're solving, I could suggest a different way of approaching it.

@AlanVek
Copy link
Author

AlanVek commented Aug 11, 2021

Thank you for the quick response! I'm implementing a SpaceWire IP core, and the standard defines this method of sending the clock in those two wires in that specific way. I thought the problem was with the generation of the signals, so I tried changing w2 from comb to a DDR flip-flop, but this kept happening, so clearly the problem is with the receiver and its retrieval of the clock. Currently I'm using a workaround that solves the problem in the simulations, but won't work in the actual FPGA.

@AlanVek
Copy link
Author

AlanVek commented Aug 11, 2021

Thanks for the help. I ended up solving it with this change:

image

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Development

No branches or pull requests

2 participants