When run the attributes appear in the generated ucf, and an IBUFDS primitive is instantiated in the generated verilog. However when ISE actually runs synthesis, the instance properties do not show these attributes applied:
In order for ISE to apply the attributes, they need to be parameters to the IBUFDS which is Instanced in xilinx.py.
If the generated verilog is edited where the IBUFDS is Instanced, then the attributes are properly applied:
ISE doesn't support using the constraints file to specify attributes on
IO buffers, this works around that by specifying them also as module
parameters which ISE does support properly.
The IBUF_LOW_PWR attribute, when applied as a parameter to the IBUFDS cell in your design, does not change the bitstream whether its value is "TRUE" or "FALSE", so looking at it is not informative. However, other attributes, like DIFF_TERM or IOSTANDARD, are indeed applied when specified in the UCF file, which you can see by looking at the top_par_pad.txt report.