Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

remove non-verilog code at start of output #365

Merged
merged 3 commits into from Apr 23, 2020
Merged

remove non-verilog code at start of output #365

Changes from 1 commit
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
d58c96d
remove non-verilog code at start of output
hofstee Apr 23, 2020
63b68e2
Clarify verilog_text header removal
hofstee Apr 23, 2020
be61e99
clarify comment further
whitequark Apr 23, 2020
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Jump to
Jump to file
Failed to load files.
Diff view
Diff view
7 changes: 7 additions & 0 deletions nmigen/back/verilog.py
View file
Open in desktop
@@ -1,6 +1,7 @@
import os
import re
import subprocess
import itertools

from .._toolchain import *
from . import rtlil
Expand Down Expand Up @@ -65,6 +66,12 @@ def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog
if popen.returncode:
raise YosysError(error.strip())
else:
# Remove empty lines and things that are not legal Verilog
# syntax at start of file
hofstee marked this conversation as resolved.
Show resolved Hide resolved
verilog_text = "\n".join(itertools.dropwhile(
lambda x: not x or x.strip().startswith("--"),
hofstee marked this conversation as resolved.
Show resolved Hide resolved
verilog_text.splitlines()
))
return verilog_text


Expand Down