[WIP] Initial implementation of ECP5 PLL instantiation

[GuzTech]

This is the initial implementation where I took the liberty to be inspired by the Litex implementation.

Signed-off-by: Oguz Meteer info@guztech.nl

[codecov]

Codecov Report

Merging #426 into master will not change coverage.
The diff coverage is n/a.

@@           Coverage Diff           @@
##           master     #426   +/-   ##
=======================================
  Coverage   81.72%   81.72%           
=======================================
  Files          40       40           
  Lines        6100     6100           
  Branches     1243     1243           
=======================================
  Hits         4985     4985           
+ Misses        935      934    -1     
- Partials      180      181    +1     

Impacted Files	Coverage Δ
nmigen/build/run.py	31.25% <0.00%> (ø)

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[GuzTech]

I have no doubt that the implementation can be improved, but I'm not entirely sure how. My Python skills aren't the best, and there are parts that I'm a bit iffy about.

Some examples:

• In register_clkin, I don't know exactly how to check that the clkin parameter is a ClockSignal.
• Also in register_clkin, I had an intermediate signal self.clkin that I commented out. That actually caused me to not define a new Module in elaborate, but in __init__, since I needed to assign the clkin parameter to self.clkin combinatorially. I found that an intermediate signal is unnecessary, so I now instantiate a new Module and return in it in elaborate.
• In the Litex implementation, they always feed the last clock output back into the feedback input. Maybe we should make this optional?

[whitequark]

It's way too early to consider merging anything upstream. Let's discuss what API we want first in #425.

[GuzTech]

Of course. I just posted this just to have some code that we could look at.