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nmigen.build.res: Ensure all pins are available in a DiffPairs #457

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@jeanthom jeanthom commented Jul 31, 2020

Fixes #456

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@jeanthom jeanthom commented Jul 31, 2020

Breaks here:

Traceback (most recent call last):
  File "soc.py", line 108, in <module>
    platform.build(soc, do_program=True)
  File "/home/jeanthomas/Documents/nmigen/nmigen/build/plat.py", line 90, in build
    plan = self.prepare(elaboratable, name, **kwargs)
  File "/home/jeanthomas/Documents/nmigen/nmigen/build/plat.py", line 151, in prepare
    for pin, p_port, n_port, attrs, invert in self.iter_differential_pins():
  File "/home/jeanthomas/Documents/nmigen/nmigen/build/res.py", line 182, in iter_differential_pins
    yield pin, port.p, port.n, attrs, res.ios[0].invert
  File "/home/jeanthomas/Documents/nmigen/nmigen/hdl/rec.py", line 149, in __getattr__
    return self[name]
  File "/home/jeanthomas/Documents/nmigen/nmigen/hdl/rec.py", line 160, in __getitem__
    raise AttributeError("{} does not have a field '{}'. Did you mean one of: {}?"
AttributeError: Record 'ddr3_0__clk' does not have a field 'n'. Did you mean one of: p?

whitequark added a commit that referenced this issue Jul 31, 2020
When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
whitequark added a commit that referenced this issue Jul 31, 2020
When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
@jeanthom jeanthom closed this Jul 31, 2020
whitequark added a commit that referenced this issue Jul 31, 2020
When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
whitequark added a commit that referenced this issue Jul 31, 2020
When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
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