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vendor.quicklogic: enable SoC clock configuration #543

merged 1 commit into from Nov 13, 2020


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Related PR: amaranth-lang/amaranth-boards#117
Signed-off-by: Jan Kowalewski

Signed-off-by: Jan Kowalewski <>
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codecov bot commented Nov 13, 2020

Codecov Report

Merging #543 (39438cd) into master (36bc1d2) will not change coverage.
The diff coverage is n/a.

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@@           Coverage Diff           @@
##           master     #543   +/-   ##
  Coverage   81.43%   81.43%           
  Files          49       49           
  Lines        6464     6464           
  Branches     1290     1290           
  Hits         5264     5264           
  Misses       1010     1010           
  Partials      190      190           

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The code looks basically reasonable. However, I don't understand the meaning of --osc-freq and --fpga-clk-divider being provided at the same time. Normally, I would expect an on-chip oscillator, such as a ring oscillator, to have a fixed frequency, and the system clock frequency could be configured by specifying a divisor explicitly, or providing a frequency and letting the tools come up with the closest matching divisor.

Could you explain the relevant part of the clock tree to me, or refer me to a section of the EOS S3 TRM that does?

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Here is the TRM link related to clocks:
Table on page 90 (link) provides information about maximum frequencies for FPGA domain.

Currently I can see that the bitstream_to_openocd tool assumes that the divider is always on, so it is not possible for now to achieve frequencies beyond 40MHz (which is max 80MHz divided by minimum divisor: 2). I think it would be nice to have an option to configure higher frequency in future like maximum 72MHz for FPGA domain, to do so we'll need --osc-freq . We can set default osc_freq and osc_div in platform definition thus setting them would be optional in board definition.

or providing a frequency and letting the tools come up with the closest matching divisor.

I agree this is something that is missing in bitstream_to_openocd tool. For now it is a very manual approach if user wants to configure other frequency for FPGA domain than the default one.

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Thanks. I've reviewed the EOS S3 clocking and the approach you picked is perfectly fine.

@whitequark whitequark merged commit adef3b2 into amaranth-lang:master Nov 13, 2020
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2 participants