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back.rtlil: avoid sync process emission in RTLIL. #667

merged 1 commit into from Jan 1, 2022


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Avoiding emission of sync processes in RTLIL allows us to avoid a dependency on matching the behavior expected by Yosys, which generally expects sync processes in RTLIL to match those emitted by the output from it's own Verilog parser. This also simplifies the logic used in emitting RTLIL overall.

Combinatorial processes are still emitted however. Without these the RTLIL does not have a high-level understanding of Switch statements, which significantly diminishes the quality of emitted Verilog, as these are converted to $mux cells in Yosys, which become ? constructs when converted back to Verilog.

Fixes #603.

We continue to emit combinatorial processes in RTLIL. This allows switch
statements in the HDL itself to be mapped to switch statements in RTLIL,
getting translated to Verilog case statements. This output has much
higher clarity than using `$mux` cells directly.

Fixes amaranth-lang#603.
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codecov-commenter commented Dec 18, 2021

Codecov Report

Merging #667 (abc2d06) into main (39a83f4) will decrease coverage by 0.15%.
The diff coverage is 100.00%.

Impacted file tree graph

@@            Coverage Diff             @@
##             main     #667      +/-   ##
- Coverage   81.48%   81.32%   -0.16%     
  Files          49       49              
  Lines        6475     6464      -11     
  Branches     1533     1526       -7     
- Hits         5276     5257      -19     
- Misses       1007     1014       +7     
- Partials      192      193       +1     
Impacted Files Coverage Δ
amaranth/back/ 78.19% <100.00%> (-1.62%) ⬇️
amaranth/build/ 22.05% <0.00%> (ø)

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@whitequark whitequark linked an issue Jan 1, 2022 that may be closed by this pull request
@whitequark whitequark merged commit 5a4d45b into amaranth-lang:main Jan 1, 2022
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Thank you!

@Lunaphied Lunaphied deleted the fix-603 branch January 2, 2022 22:22
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