back.rtlil: avoid sync process emission in RTLIL. #667
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Avoiding emission of sync processes in RTLIL allows us to avoid a dependency on matching the behavior expected by Yosys, which generally expects sync processes in RTLIL to match those emitted by the output from it's own Verilog parser. This also simplifies the logic used in emitting RTLIL overall.
Combinatorial processes are still emitted however. Without these the RTLIL does not have a high-level understanding of
Switch
statements, which significantly diminishes the quality of emitted Verilog, as these are converted to$mux
cells in Yosys, which become?
constructs when converted back to Verilog.Fixes #603.