{"payload":{"header_redesign_enabled":false,"results":[{"id":"42888543","archived":false,"color":"#b2b7f8","followers":1,"has_funding_file":false,"hl_name":"ameyjain/VERILOG-Five-stage-32-bit-MIPS-processor","hl_trunc_description":"Design & Implementation of a balanced five stage pipelined MIPS Processor ensuring improved performance using pipelining & hazard control…","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":42888543,"name":"VERILOG-Five-stage-32-bit-MIPS-processor","owner_id":12677412,"owner_login":"ameyjain","updated_at":"2015-09-21T19:26:44.219Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":50,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aameyjain%252FVERILOG-Five-stage-32-bit-MIPS-processor%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/ameyjain/VERILOG-Five-stage-32-bit-MIPS-processor/star":{"post":"Oh17PiL7ghoMp7m3WXdY1lviUbeppKoyRdaQ7KBijSg1DC37do0om27ba7VkavXhLCe2wo_21YCO0OogRMwEXg"},"/ameyjain/VERILOG-Five-stage-32-bit-MIPS-processor/unstar":{"post":"m2txKlSfkYBtOqK5clogY4vh7E0gJ7lrcvSo3TrJqeSOPiZ7P3zU5qPT3CetK4dIoEe6vnn-t9PfQQP_CngVng"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"PHBWFxhr10HPrun-P1Gfjp9hV5ULsP1DDb3Ao6hzj5v5xgajvaJQJtcgNBURmCJZTuzYiN4iAOY1gDl6ZOMzEA"}}},"title":"Repository search results"}