diff --git a/+adi/+AD9361/Base.m b/+adi/+AD9361/Base.m index 5876a74..450f417 100644 --- a/+adi/+AD9361/Base.m +++ b/+adi/+AD9361/Base.m @@ -1,5 +1,7 @@ -classdef (Abstract, Hidden = true) Base < adi.common.Attribute & matlabshared.libiio.base & ... - matlab.system.mixin.CustomIcon +classdef (Abstract, Hidden = true) Base < adi.common.Attribute & ... + adi.common.DebugAttribute & ... + matlabshared.libiio.base & matlab.system.mixin.CustomIcon + %adi.AD9361.Base Class % This class contains shared parameters and methods between TX and RX % classes diff --git a/+adi/+AD9361/Rx.m b/+adi/+AD9361/Rx.m index a101310..f2b126c 100644 --- a/+adi/+AD9361/Rx.m +++ b/+adi/+AD9361/Rx.m @@ -1,4 +1,5 @@ -classdef Rx < adi.AD9361.Base & adi.common.Rx & matlab.system.mixin.SampleTime +classdef Rx < adi.AD9361.Base & adi.AD9361.TuneAGC & ... + adi.common.Rx & matlab.system.mixin.SampleTime % adi.AD9361.Rx Receive data from the AD9361 transceiver % The adi.AD9361.Rx System object is a signal source that can receive % complex data from the AD9361. @@ -215,7 +216,7 @@ obj.setAttributeLongLong(id,'sampling_frequency',value,true,4); end end - end + end end methods (Access=protected) @@ -324,6 +325,14 @@ function setupInit(obj) writeFilterFile(obj); end + if (obj.CustomAGC) + % Initialize hardware to reflect debug attribute changes + obj.WriteDebugAttributes(); + obj.setDebugAttributeLongLong(); + obj.setDebugAttributeBool(); + obj.WriteToRegisters(); + end + end end diff --git a/+adi/+AD9361/TuneAGC.m b/+adi/+AD9361/TuneAGC.m new file mode 100644 index 0000000..101fcbb --- /dev/null +++ b/+adi/+AD9361/TuneAGC.m @@ -0,0 +1,288 @@ +classdef TuneAGC < adi.common.DebugAttribute & adi.common.RegisterReadWrite + properties (Nontunable, Hidden) + CustomAGC = 0; + + AttackDelay = 1; + PeakOverloadWaitTime = 10; + AGCLockLevel = 10; + DecStepSizeFullTableCase3 = 3; + ADCLargeOverloadThresh = 58; + ADCSmallOverloadThresh = 47; + DecStepSizeFullTableCase2 = 3; + DecStepSizeFullTableCase1 = 3; + LargeLMTOverloadThresh = 35; + SmallLMTOverloadThresh = 25; + SettlingDelay = 3; + EnergyLostThresh = 3; + LowPowerThresh = 15; + IncrementGainStep + FAGCLockLevelGainIncreaseUpperLimit = 7; + FAGCLPThreshIncrementTime = 3; + DecPowMeasurementDuration = 16; + end + + properties (Constant, Hidden, Access = private) + % Register addresses in hexadecimal + AttackDelay_Reg = '022'; + PeakOverloadWaitTime_Reg = '0FE'; + AGCLockLevel_Reg = '101'; + DecStepSizeFullTableCase3_Reg = '103'; + ADCSmallOverloadThresh_Reg = '104'; + ADCLargeOverloadThresh_Reg = '105'; + DecStepSizeFullTableCase2_Reg = '106'; + DecStepSizeFullTableCase1_Reg = '106'; + LargeLMTOverloadThresh_Reg = '108'; + SmallLMTOverloadThresh_Reg = '107'; + SettlingDelay_Reg = '111'; + EnergyLostThresh_Reg = '112'; + LowPowerThresh_Reg = '114'; + IncrementGainStep_Reg = '117'; + FAGCLockLevelGainIncreaseUpperLimit_Reg = '118'; + FAGCLPThreshIncrementTime_Reg = '11B'; + DecPowMeasurementDuration_Reg = '15C'; + + % Register mask in binary + AttackDelay_Mask = '11000000'; + PeakOverloadWaitTime_Mask = '11100000'; + AGCLockLevel_Mask = '10000000'; + DecStepSizeFullTableCase3_Mask = '11100011'; + DecStepSizeFullTableCase2_Mask = '10001111'; + DecStepSizeFullTableCase1_Mask = '11110000'; + LargeLMTOverloadThresh_Mask = '11000000'; + SmallLMTOverloadThresh_Mask = '11000000'; + SettlingDelay_Mask = '11100000'; + EnergyLostThresh_Mask = '11000000'; + LowPowerThresh_Mask = '10000000'; + IncrementGainStep_Mask = '00011111'; + FAGCLockLevelGainIncreaseUpperLimit_Mask = '11000000'; + DecPowMeasurementDuration_Mask = '11110000'; + + % Bit-shifts to be applied + DecStepSizeFullTableCase3_BitShift = 2; + DecStepSizeFullTableCase2_BitShift = 4; + IncrementGainStep_BitShift = 5; + end + + methods + function set.AttackDelay(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',63}, ... + '', 'AttackDelay'); + obj.AttackDelay = value; + if obj.ConnectedToDevice + obj.setRegister(value, obj.AttackDelay_Reg, obj.AttackDelay_Mask); + end + end + function set.PeakOverloadWaitTime(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',31}, ... + '', 'PeakOverloadWaitTime'); + obj.PeakOverloadWaitTime = value; + if obj.ConnectedToDevice + obj.setRegister(value, obj.PeakOverloadWaitTime_Reg, obj.PeakOverloadWaitTime_Mask); + end + end + function set.AGCLockLevel(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',127}, ... + '', 'AGCLockLevel'); + obj.AGCLockLevel = value; + if obj.ConnectedToDevice + obj.setRegister(value, obj.AGCLockLevel_Reg, obj.AGCLockLevel_Mask); + end + end + function set.DecStepSizeFullTableCase3(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',7}, ... + '', 'DecStepSizeFullTableCase3'); + obj.DecStepSizeFullTableCase3 = value; + if obj.ConnectedToDevice + obj.setRegister(value, obj.DecStepSizeFullTableCase3_Reg, obj.DecStepSizeFullTableCase3_Mask, obj.DecStepSizeFullTableCase3_BitShift); + end + end + function set.ADCLargeOverloadThresh(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',255}, ... + '', 'ADCLargeOverloadThresh'); + obj.ADCLargeOverloadThresh = value; + if obj.ConnectedToDevice + obj.setDebugAttributeLongLong('adi,gc-adc-large-overload-thresh',value); + end + end + function set.ADCSmallOverloadThresh(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',obj.ADCLargeOverloadThresh}, ... + '', 'ADCSmallOverloadThresh'); + obj.ADCSmallOverloadThresh = value; + if obj.ConnectedToDevice + obj.setDebugAttributeLongLong('adi,gc-adc-small-overload-thresh',value); + end + end + function set.DecStepSizeFullTableCase2(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',7}, ... + '', 'DecStepSizeFullTableCase2'); + obj.DecStepSizeFullTableCase2 = value; + if obj.ConnectedToDevice + obj.setRegister(value, obj.DecStepSizeFullTableCase2_Reg, obj.DecStepSizeFullTableCase2_Mask, obj.DecStepSizeFullTableCase2_BitShift); + end + end + function set.DecStepSizeFullTableCase1(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',15}, ... + '', 'DecStepSizeFullTableCase1'); + obj.DecStepSizeFullTableCase1 = value; + if obj.ConnectedToDevice + obj.setRegister(value, obj.DecStepSizeFullTableCase1_Reg, obj.DecStepSizeFullTableCase1_Mask); + end + end + function set.LargeLMTOverloadThresh(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',63}, ... + '', 'LargeLMTOverloadThresh'); + obj.LargeLMTOverloadThresh = value; + if obj.ConnectedToDevice + obj.setRegister(value, obj.LargeLMTOverloadThresh_Reg, obj.LargeLMTOverloadThresh_Mask); + end + end + function set.SmallLMTOverloadThresh(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',obj.LargeLMTOverloadThresh}, ... + '', 'SmallLMTOverloadThresh'); + obj.SmallLMTOverloadThresh = value; + if obj.ConnectedToDevice + obj.setRegister(value, obj.SmallLMTOverloadThresh_Reg, obj.SmallLMTOverloadThresh_Mask); + end + end + function set.SettlingDelay(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',31}, ... + '', 'SettlingDelay'); + obj.SettlingDelay = value; + if obj.ConnectedToDevice + obj.setRegister(value, obj.SettlingDelay_Reg, obj.SettlingDelay_Mask); + end + end + function set.EnergyLostThresh(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',63}, ... + '', 'SettlingDelay'); + obj.EnergyLostThresh = value; + if obj.ConnectedToDevice + obj.setRegister(value, obj.EnergyLostThresh_Reg, obj.EnergyLostThresh_Mask); + end + end + function set.LowPowerThresh(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',63}, ... + '', 'LowPowerThresh'); + obj.LowPowerThresh = value; + if obj.ConnectedToDevice + obj.setDebugAttributeLongLong('adi,gc-low-power-thresh',value); + end + end + function set.IncrementGainStep(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',7}, ... + '', 'IncrementGainStep'); + obj.IncrementGainStep = value; + if obj.ConnectedToDevice + obj.setRegister(value, obj.IncrementGainStep_Reg, obj.IncrementGainStep_Mask, obj.IncrementGainStep_BitShift); + end + end + function set.FAGCLockLevelGainIncreaseUpperLimit(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',63}, ... + '', 'FAGCLockLevelGainIncreaseUpperLimit'); + obj.FAGCLockLevelGainIncreaseUpperLimit = value; + if obj.ConnectedToDevice + obj.setDebugAttributeLongLong('adi,fagc-lock-level-gain-increase-upper-limit',value); + end + end + function set.FAGCLPThreshIncrementTime(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',255}, ... + '', 'FAGCLPThreshIncrementTime'); + obj.FAGCLPThreshIncrementTime = value; + if obj.ConnectedToDevice + obj.setDebugAttributeLongLong('adi,fagc-lp-thresh-increment-time',value); + end + end + function set.DecPowMeasurementDuration(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>=',0,'<=',15}, ... + '', 'DecPowMeasurementDuration'); + obj.DecPowMeasurementDuration = value; + if obj.ConnectedToDevice + obj.setRegister(value, obj.DecPowMeasurementDuration_Reg, obj.DecPowMeasurementDuration_Mask); + end + end + function WriteDebugAttributes(obj) + if obj.ConnectedToDevice + obj.setDebugAttributeLongLong('adi,gc-adc-large-overload-thresh',obj.ADCLargeOverloadThresh); + obj.setDebugAttributeLongLong('adi,gc-adc-small-overload-thresh',obj.ADCSmallOverloadThresh); + obj.setDebugAttributeLongLong('adi,gc-low-power-thresh',obj.LowPowerThresh); + obj.setDebugAttributeLongLong('adi,fagc-lock-level-gain-increase-upper-limit',obj.FAGCLockLevelGainIncreaseUpperLimit); + obj.setDebugAttributeLongLong('adi,fagc-lp-thresh-increment-time',obj.FAGCLPThreshIncrementTime); + end + end + function WriteToRegisters(obj) + if obj.ConnectedToDevice + obj.setRegister(obj.AttackDelay, obj.AttackDelay_Reg, obj.AttackDelay_Mask); + obj.setRegister(obj.PeakOverloadWaitTime, obj.PeakOverloadWaitTime_Reg, obj.PeakOverloadWaitTime_Mask); + obj.setRegister(obj.AGCLockLevel, obj.AGCLockLevel_Reg, obj.AGCLockLevel_Mask); + obj.setRegister(obj.DecStepSizeFullTableCase3, obj.DecStepSizeFullTableCase3_Reg, obj.DecStepSizeFullTableCase3_Mask, obj.DecStepSizeFullTableCase3_BitShift); + obj.setRegister(obj.DecStepSizeFullTableCase2, obj.DecStepSizeFullTableCase2_Reg, obj.DecStepSizeFullTableCase2_Mask, obj.DecStepSizeFullTableCase2_BitShift); + obj.setRegister(obj.DecStepSizeFullTableCase1, obj.DecStepSizeFullTableCase1_Reg, obj.DecStepSizeFullTableCase1_Mask); + obj.setRegister(obj.LargeLMTOverloadThresh, obj.LargeLMTOverloadThresh_Reg, obj.LargeLMTOverloadThresh_Mask); + obj.setRegister(obj.SmallLMTOverloadThresh, obj.SmallLMTOverloadThresh_Reg, obj.SmallLMTOverloadThresh_Mask); + obj.setRegister(obj.SettlingDelay, obj.SettlingDelay_Reg, obj.SettlingDelay_Mask); + obj.setRegister(obj.EnergyLostThresh, obj.EnergyLostThresh_Reg, obj.EnergyLostThresh_Mask); + obj.setRegister(obj.IncrementGainStep, obj.IncrementGainStep_Reg, obj.IncrementGainStep_Mask, obj.IncrementGainStep_BitShift); + obj.setRegister(obj.DecPowMeasurementDuration, obj.DecPowMeasurementDuration_Reg, obj.DecPowMeasurementDuration_Mask); + end + end + function value = ReadFromRegister(obj, prop_name) + if obj.ConnectedToDevice + switch prop_name + case 'AttackDelay' + value = obj.getRegister(obj.AttackDelay_Reg, obj.AttackDelay_Mask); + case 'PeakOverloadWaitTime' + value = obj.getRegister(obj.PeakOverloadWaitTime_Reg, obj.PeakOverloadWaitTime_Mask); + case 'AGCLockLevel' + value = obj.getRegister(obj.AGCLockLevel_Reg, obj.AGCLockLevel_Mask); + case 'DecStepSizeFullTableCase3' + value = obj.getRegister(obj.DecStepSizeFullTableCase3_Reg, obj.DecStepSizeFullTableCase3_Mask, obj.DecStepSizeFullTableCase3_BitShift); + case 'ADCSmallOverloadThresh' + value = obj.getRegister(obj.ADCSmallOverloadThresh_Reg); + case 'ADCLargeOverloadThresh' + value = obj.getRegister(obj.ADCLargeOverloadThresh_Reg); + case 'DecStepSizeFullTableCase2' + value = obj.getRegister(obj.DecStepSizeFullTableCase2_Reg, obj.DecStepSizeFullTableCase2_Mask, obj.DecStepSizeFullTableCase2_BitShift); + case 'DecStepSizeFullTableCase1' + value = obj.getRegister(obj.DecStepSizeFullTableCase1_Reg, obj.DecStepSizeFullTableCase1_Mask); + case 'LargeLMTOverloadThresh' + value = obj.getRegister(obj.LargeLMTOverloadThresh_Reg, obj.LargeLMTOverloadThresh_Mask); + case 'SmallLMTOverloadThresh' + value = obj.getRegister(obj.SmallLMTOverloadThresh_Reg, obj.SmallLMTOverloadThresh_Mask); + case 'SettlingDelay' + value = obj.getRegister(obj.SettlingDelay_Reg, obj.SettlingDelay_Mask); + case 'EnergyLostThresh' + value = obj.getRegister(obj.EnergyLostThresh_Reg, obj.EnergyLostThresh_Mask); + case 'LowPowerThresh' + value = obj.getRegister(obj.LowPowerThresh_Reg, obj.LowPowerThresh_Mask); + case 'IncrementGainStep' + value = obj.getRegister(obj.IncrementGainStep_Reg, obj.IncrementGainStep_Mask, obj.IncrementGainStep_BitShift); + case 'FAGCLockLevelGainIncreaseUpperLimit' + value = obj.getRegister(obj.FAGCLockLevelGainIncreaseUpperLimit_Reg, obj.FAGCLockLevelGainIncreaseUpperLimit_Mask); + case 'FAGCLPThreshIncrementTime' + value = obj.getRegister(obj.FAGCLPThreshIncrementTime_Reg); + case 'DecPowMeasurementDuration' + value = obj.getRegister(obj.DecPowMeasurementDuration_Reg, obj.DecPowMeasurementDuration_Mask); + otherwise + error('Attempted to read unknown property %s\n', prop_name); + end + end + end + end +end \ No newline at end of file diff --git a/+adi/+AD9371/Base.m b/+adi/+AD9371/Base.m index c18bef4..716978f 100644 --- a/+adi/+AD9371/Base.m +++ b/+adi/+AD9371/Base.m @@ -15,6 +15,19 @@ channelCount = 2; end + properties (Nontunable, Logical) + %EnableCustomProfile Enable Custom Profile + % Enable use of custom Profile file to set SamplingRate, + % RFBandwidth, and FIR in datapaths + EnableCustomProfile = false; + end + + properties (Nontunable) + %CustomProfileFileName Custom Profile File Name + % Path to custom Profile file created from profile wizard + CustomProfileFileName = ''; + end + properties (Hidden, Constant) %SamplingRate Sampling Rate % Baseband sampling rate in Hz, specified as a scalar @@ -72,6 +85,23 @@ function delete(~) obj.setAttributeLongLong(id,'frequency',value,true); end end + % Check EnableCustomProfile + function set.EnableCustomProfile(obj, value) + validateattributes( value, { 'logical' }, ... + { }, ... + '', 'EnableCustomProfile'); + obj.EnableCustomProfile = value; + end + % Check CustomFilterFileName + function set.CustomProfileFileName(obj, value) + validateattributes( value, { 'char' }, ... + { }, ... + '', 'CustomProfileFileName'); + obj.CustomProfileFileName = value; + if obj.EnableCustomProfile && obj.ConnectedToDevice %#ok + writeProfileFile(obj); + end + end end %% API Functions @@ -80,6 +110,12 @@ function delete(~) function icon = getIconImpl(obj) icon = sprintf(['AD9371 ',obj.Type]); end + + + function writeProfileFile(obj) + profle_data_str = fileread(obj.CustomProfileFileName); + obj.setDeviceAttributeRAW('profile_config',profle_data_str); + end end diff --git a/+adi/+AD9371/Rx.m b/+adi/+AD9371/Rx.m index d8b1ee5..13550ab 100644 --- a/+adi/+AD9371/Rx.m +++ b/+adi/+AD9371/Rx.m @@ -196,6 +196,10 @@ function setupInit(obj) id = sprintf('altvoltage%d',strcmp(obj.Type,'Tx')); obj.setAttributeLongLong(id,'RX_LO_frequency',obj.CenterFrequency ,true); + if obj.EnableCustomProfile + writeProfileFile(obj); + end + if strcmp(obj.GainControlMode,'manual') obj.setAttributeLongLong('voltage0','hardwaregain',obj.GainChannel0,false); obj.setAttributeLongLong('voltage1','hardwaregain',obj.GainChannel1,false); diff --git a/+adi/+common/Attribute.m b/+adi/+common/Attribute.m index 608014a..bbb2eeb 100644 --- a/+adi/+common/Attribute.m +++ b/+adi/+common/Attribute.m @@ -1,7 +1,7 @@ classdef (Abstract) Attribute < matlabshared.libiio.base % Attribute IIO attribute function calls - methods (Hidden, Access = protected) + methods (Hidden) function setAttributeLongLong(obj,id,attr,value,isOutput,tol) phydev = getDev(obj, obj.phyDevName); @@ -22,6 +22,15 @@ function setAttributeLongLong(obj,id,attr,value,isOutput,tol) end end + function rValue = getAttributeLongLong(obj,id,attr,isOutput) + phydev = getDev(obj, obj.phyDevName); + chanPtr = iio_device_find_channel(obj,phydev,id,isOutput);%FIXME (INVERSION) + status = cPtrCheck(obj,chanPtr); + cstatus(obj,status,['Channel: ' id ' not found']); + [status, rValue] = iio_channel_attr_read_longlong(obj,chanPtr,attr); + cstatus(obj,status,['Error reading attribute: ' attr]); + end + function setAttributeBool(obj,id,attr,value,isOutput) phydev = getDev(obj, obj.phyDevName); chanPtr = iio_device_find_channel(obj,phydev,id,isOutput);%FIXME (INVERSION) @@ -38,6 +47,15 @@ function setAttributeBool(obj,id,attr,value,isOutput) end end + function rValue = getAttributeBool(obj,id,attr,isOutput) + phydev = getDev(obj, obj.phyDevName); + chanPtr = iio_device_find_channel(obj,phydev,id,isOutput);%FIXME (INVERSION) + status = cPtrCheck(obj,chanPtr); + cstatus(obj,status,['Channel: ' id ' not found']); + [status, rValue] = iio_channel_attr_read_bool(obj,chanPtr,attr); + cstatus(obj,status,['Error reading attribute: ' attr]); + end + function setAttributeRAW(obj,id,attr,value,isOutput) phydev = getDev(obj, obj.phyDevName); chanPtr = iio_device_find_channel(obj,phydev,id,isOutput);%FIXME (INVERSION) @@ -50,6 +68,15 @@ function setAttributeRAW(obj,id,attr,value,isOutput) end end + function rValue = getAttributeRAW(obj,id,attr,isOutput) + phydev = getDev(obj, obj.phyDevName); + chanPtr = iio_device_find_channel(obj,phydev,id,isOutput);%FIXME (INVERSION) + status = cPtrCheck(obj,chanPtr); + cstatus(obj,status,['Channel: ' id ' not found']); + [status, rValue] = iio_channel_attr_read(obj,chanPtr,attr); + cstatus(obj,status,['Error reading attribute: ' attr]); + end + function setDeviceAttributeRAW(obj,attr,value) phydev = getDev(obj, obj.phyDevName); bytes = iio_device_attr_write(obj,phydev,attr,value); @@ -59,5 +86,11 @@ function setDeviceAttributeRAW(obj,attr,value) end end + function rValue = getDeviceAttributeRAW(obj,attr) + phydev = getDev(obj, obj.phyDevName); + [status, rValue] = iio_device_attr_read(obj,phydev,attr); + cstatus(obj,status,['Error reading attribute: ' attr]); + end + end end diff --git a/+adi/+common/DebugAttribute.m b/+adi/+common/DebugAttribute.m new file mode 100644 index 0000000..fb6e32c --- /dev/null +++ b/+adi/+common/DebugAttribute.m @@ -0,0 +1,38 @@ +classdef (Abstract) DebugAttribute < matlabshared.libiio.base + + methods (Hidden, Access = protected) + function setDebugAttributeLongLong(obj,attr,value) + phydev = getDev(obj, obj.phyDevName); + if (nargin == 1) + iio_device_debug_attr_write_longlong(obj,phydev, 'initialize',1); + return; + end + status = iio_device_debug_attr_write_longlong(obj,phydev,attr,value); + cstatus(obj,status,['Attribute write failed for : ' attr ' with value ' num2str(value)]); + % Check + [status, rValue] = iio_device_debug_attr_read_longlong(obj,phydev,attr); + cstatus(obj,status,['Error reading attribute: ' attr]); + if (value ~= rValue) + status = -1; + cstatus(obj,status,['Attribute ' attr ' return value ' num2str(rValue) ', expected ' num2str(value)]); + end + end + + function setDebugAttributeBool(obj,attr,value) + phydev = getDev(obj, obj.phyDevName); + if (nargin == 1) + iio_device_debug_attr_write_bool(obj,phydev, 'initialize',1); + return; + end + status = iio_device_debug_attr_write_bool(obj,phydev,attr,value); + cstatus(obj,status,['Attribute write failed for : ' attr]); + % Check + [status, rValue] = iio_device_debug_attr_read_bool(obj,phydev,attr); + cstatus(obj,status,['Error reading attribute: ' attr]); + if value ~= rValue + status = -1; + cstatus(obj,status,['Attribute ' attr ' return value ' num2str(rValue) ', expected ' num2str(value)]); + end + end + end +end \ No newline at end of file diff --git a/+adi/+common/RegisterReadWrite.m b/+adi/+common/RegisterReadWrite.m new file mode 100644 index 0000000..fe6e6f2 --- /dev/null +++ b/+adi/+common/RegisterReadWrite.m @@ -0,0 +1,40 @@ +classdef (Abstract) RegisterReadWrite < matlabshared.libiio.base + + methods (Hidden, Access = protected) + function setRegister(obj, value, addr, mask_bin, bit_shift) + phydev = getDev(obj, obj.phyDevName); + if (nargin == 5) + value = value*2^(bit_shift); + end + addr_dec = hex2dec(addr); + mask_dec = bin2dec(mask_bin); + [status, curr_val] = iio_device_reg_read(obj,phydev,addr_dec); + cstatus(obj,status,['Error reading address: ' addr]); + new_val = bitxor(value, bitand(bitxor(value, curr_val), mask_dec)); + status = iio_device_reg_write(obj,phydev,addr_dec,new_val); + cstatus(obj,status,['Address write failed for : ' addr ' with value ' num2str(value)]); + % Check + [status, rValue] = iio_device_reg_read(obj,phydev,addr_dec); + cstatus(obj,status,['Error reading address: ' addr]); + if (new_val ~= rValue) + status = -1; + cstatus(obj,status,['Address ' addr ' contents ' num2str(rValue) ', expected ' num2str(new_val)]); + end + end + + function value = getRegister(obj, addr, mask_bin, bit_shift) + phydev = getDev(obj, obj.phyDevName); + addr_dec = hex2dec(addr); + % Check + [status, value] = iio_device_reg_read(obj,phydev,addr_dec); + if (nargin >= 3) + mask_dec = 255-bin2dec(mask_bin); + value = bitand(value, mask_dec); + if (nargin == 4) + value = value/2^(bit_shift); + end + end + cstatus(obj,status,['Error reading address: ' addr]); + end + end +end \ No newline at end of file diff --git a/+adi/+common/RxTx.m b/+adi/+common/RxTx.m index b859199..6c04883 100644 --- a/+adi/+common/RxTx.m +++ b/+adi/+common/RxTx.m @@ -26,6 +26,13 @@ function flag = isInactivePropertyImpl(obj, prop) flag = strcmpi(prop,'enIO'); % TX/RX + if isprop(obj,'EnableCustomProfile') + flag = flag || strcmpi(prop,'CustomProfileFileName') && ~obj.EnableCustomProfile; + if obj.EnableCustomProfile + flag = flag || strcmpi(prop,'RFBandwidth'); + flag = flag || strcmpi(prop,'SamplingRate'); + end + end if isprop(obj,'EnableCustomFilter') flag = flag || strcmpi(prop,'CustomFilterFileName') && ~obj.EnableCustomFilter; if obj.EnableCustomFilter diff --git a/+adi/Version.m b/+adi/Version.m new file mode 100644 index 0000000..d82291b --- /dev/null +++ b/+adi/Version.m @@ -0,0 +1,20 @@ +classdef Version + %Version + % BSP Version information + properties(Constant) + HDL = 'hdl_2018_r1'; + Vivado = '2017.4.1'; + MATLAB = 'R2018b'; + Release = '18.2'; + end + properties(Dependent) + VivadoShort + end + + methods + function value = get.VivadoShort(obj) + value = obj.Vivado(1:6); + end + end +end + diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2cf3e2e..195be3f 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,7 +1,6 @@ stages: - build - test - - test_installer - test_hardware - deploy @@ -12,11 +11,9 @@ build:2018_R1: - matlab stage: build script: - - cd CI/scripts - - make build - - make add_libad9361 - - make gen_tlbx - - cd ../.. + - ./CI/scripts/dockermake build + - ./CI/scripts/dockermake add_libad9361 + - ./CI/scripts/dockermake gen_tlbx - mkdir mltbx - ls *.mltbx - cp *.mltbx mltbx/ @@ -33,9 +30,11 @@ build:master: - matlab stage: build script: - - cd CI/scripts - - make build MLRELEASE=R2018b HDLBRANCH=master - - cd ../.. + - export HDLBRANCH=master + - export MLRELEASE=R2018b + - ./CI/scripts/dockermake build + - export HDLBRANCH= + - export MLRELEASE= allow_failure: true artifacts: paths: @@ -50,9 +49,8 @@ test:2018_R1: dependencies: - build:2018_R1 script: - - cd CI/scripts - - make test - - make zip + - ./CI/scripts/dockermake test + - ./CI/scripts/dockermake zip artifacts: paths: - zip/ @@ -64,7 +62,7 @@ test_installer:2018_R1_Installer: tags: - vivado - matlab - stage: test_installer + stage: test dependencies: - build:2018_R1 script: @@ -72,8 +70,7 @@ test_installer:2018_R1_Installer: - pwd - ls - ls *.mltbx - - cd CI/scripts - - make test_installer + - ./CI/scripts/dockermake test_installer artifacts: paths: - mltbx/ @@ -81,10 +78,26 @@ test_installer:2018_R1_Installer: reports: junit: test/BSPTestResults.xml +# Test weekly fully sythesized design +test:Synthesize: + when: manual + tags: + - matlab + - vivado + stage: test + dependencies: + - build:2018_R1 + script: + - ./CI/scripts/dockermake test_synth + artifacts: + when: always + name: "$CI_COMMIT_REF_NAME" + paths: + - test/ + - Report.pdf + # Test streaming interfaces with hardware test_hardware:Streaming_Hardware: - only: - - schedules tags: - matlab - hardware @@ -97,17 +110,21 @@ test_hardware:Streaming_Hardware: artifacts: paths: - logs/ + - Report.pdf -# Test streaming interfaces with hardware manual -test_manual:Streaming_Hardware_Manual: - when: manual +# Test EVM performance with hardware +test_hardware:EVM_Hardware: + only: + - schedules tags: - matlab - hardware + stage: test_hardware + dependencies: + - build:2018_R1 script: - cd CI/scripts - - make add_libad9361 - - make test_streaming + - make test_evm artifacts: paths: - logs/ @@ -127,4 +144,3 @@ deploy: paths: - mltbx/ - diff --git a/CI/projects/adrv9371x/common/config_rxtx.tcl b/CI/projects/adrv9371x/common/config_rxtx.tcl index 985ad1d..85c44bf 100644 --- a/CI/projects/adrv9371x/common/config_rxtx.tcl +++ b/CI/projects/adrv9371x/common/config_rxtx.tcl @@ -1,5 +1,6 @@ global ref_design +global fpga_board if {$ref_design eq "Rx" || $ref_design eq "Rx & Tx"} { # Disconnect the ADC PACK pins @@ -18,13 +19,39 @@ connect_bd_net [get_bd_pins util_ad9371_rx_cpack/adc_valid_0] [get_bd_pins util_ connect_bd_net [get_bd_pins util_ad9371_rx_cpack/adc_valid_0] [get_bd_pins util_ad9371_rx_cpack/adc_valid_3] } + +# Tie clocks to only use RX clocks +if {$ref_design eq "Rx & Tx"} { + delete_bd_objs [get_bd_nets axi_ad9371_tx_clkgen_clk_0] + connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_0] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_1] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_2] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_3] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_ad9371_tx_jesd/device_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins util_ad9371_tx_upack/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_ad9371_tx_jesd_rstgen/slowest_sync_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_ad9371_dacfifo/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_ad9371_core/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] +} + # Connect clock +if {$fpga_board eq "ZC706"} { +if {$ref_design eq "Rx" || $ref_design eq "Rx & Tx"} { +connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M18_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] +} +if {$ref_design eq "Tx"} { +connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_interconnect/M18_ACLK] [get_bd_pins axi_ad9371_tx_clkgen/clk_0] +} +} + +if {$fpga_board eq "ZCU102"} { if {$ref_design eq "Rx" || $ref_design eq "Rx & Tx"} { connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0] } if {$ref_design eq "Tx"} { connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_ad9371_tx_clkgen/clk_0] } +} ######################## if {$ref_design eq "Tx" || $ref_design eq "Rx & Tx"} { diff --git a/CI/projects/adrv9371x/zc706/Makefile b/CI/projects/adrv9371x/zc706/Makefile new file mode 100644 index 0000000..d622914 --- /dev/null +++ b/CI/projects/adrv9371x/zc706/Makefile @@ -0,0 +1,31 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := adrv9371x_zc706 + +M_DEPS += ../common/adrv9371x_bd.tcl +M_DEPS += ../../common/zc706/zc706_system_constr.xdc +M_DEPS += ../../common/zc706/zc706_system_bd.tcl +M_DEPS += ../../common/zc706/zc706_plddr3_dacfifo_bd.tcl +M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl + +LIB_DEPS += axi_ad9371 +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_spdif_tx +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += util_cpack +LIB_DEPS += util_upack +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/axi_dacfifo +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/CI/projects/adrv9371x/zc706/boot/u-boot.elf b/CI/projects/adrv9371x/zc706/boot/u-boot.elf new file mode 100644 index 0000000..3d04955 Binary files /dev/null and b/CI/projects/adrv9371x/zc706/boot/u-boot.elf differ diff --git a/CI/projects/adrv9371x/zc706/boot/uEnv.txt b/CI/projects/adrv9371x/zc706/boot/uEnv.txt new file mode 100644 index 0000000..90654b0 --- /dev/null +++ b/CI/projects/adrv9371x/zc706/boot/uEnv.txt @@ -0,0 +1,5 @@ +uenvcmd=run adi_sdboot +adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi +bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait + + diff --git a/CI/projects/adrv9371x/zc706/boot/zynq.bif b/CI/projects/adrv9371x/zc706/boot/zynq.bif new file mode 100644 index 0000000..95024b2 --- /dev/null +++ b/CI/projects/adrv9371x/zc706/boot/zynq.bif @@ -0,0 +1,6 @@ +the_ROM_image: +{ +[bootloader] ./fsbl.elf +./system_top.bit +./u-boot-zc70x.elf +} diff --git a/CI/projects/adrv9371x/zc706/config_prj.tcl b/CI/projects/adrv9371x/zc706/config_prj.tcl new file mode 100644 index 0000000..8dbff15 --- /dev/null +++ b/CI/projects/adrv9371x/zc706/config_prj.tcl @@ -0,0 +1,4 @@ +# Add 1 extra AXI master ports to the interconnect +set_property -dict [list CONFIG.NUM_MI {19}] [get_bd_cells axi_cpu_interconnect] +#connect_bd_net -net [get_bd_nets axi_adrv9009_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0] +connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M18_ARESETN] diff --git a/CI/projects/adrv9371x/zc706/config_rxtx.tcl b/CI/projects/adrv9371x/zc706/config_rxtx.tcl new file mode 100644 index 0000000..24b2e6c --- /dev/null +++ b/CI/projects/adrv9371x/zc706/config_rxtx.tcl @@ -0,0 +1,7 @@ +set ad_hdl_dir [pwd] +set proj_dir $ad_hdl_dir/projects/adrv9371x/zc706 + +source $proj_dir/config_prj.tcl +source $ad_hdl_dir/projects/adrv9371x/common/config_rxtx.tcl + +regenerate_bd_layout diff --git a/CI/projects/adrv9371x/zc706/system_bd.tcl b/CI/projects/adrv9371x/zc706/system_bd.tcl new file mode 100644 index 0000000..201f65a --- /dev/null +++ b/CI/projects/adrv9371x/zc706/system_bd.tcl @@ -0,0 +1,16 @@ + +set dac_fifo_name axi_ad9371_dacfifo +set dac_fifo_address_width 10 +set dac_data_width 128 +set dac_dma_data_width 128 + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl + +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 200 + +source $ad_hdl_dir/projects/adrv9371x/common/adrv9371x_bd.tcl +#source ../common/adrv9371x_bd.tcl + +ad_connect sys_dma_clk sys_ps7/FCLK_CLK2 +ad_connect sys_ps7/FCLK_RESET2_N sys_dma_rstgen/ext_reset_in diff --git a/CI/projects/adrv9371x/zc706/system_constr.xdc b/CI/projects/adrv9371x/zc706/system_constr.xdc new file mode 100644 index 0000000..570b1f9 --- /dev/null +++ b/CI/projects/adrv9371x/zc706/system_constr.xdc @@ -0,0 +1,76 @@ + +# ad9371 + +set_property -dict {PACKAGE_PIN AD10} [get_ports ref_clk0_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC) +set_property -dict {PACKAGE_PIN AD9 } [get_ports ref_clk0_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC) +set_property -dict {PACKAGE_PIN AA8 } [get_ports ref_clk1_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN AA7 } [get_ports ref_clk1_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[0]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[0]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[1]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[1]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[2]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[2]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[0]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[3]) +set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[0]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[3]) +set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[0]) +set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[0]) +set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[2]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[1]) +set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[2]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[1]) +set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[2]) +set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[2]) +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_p] ; ## G27 FMC_HPC_LA25_P (Sniffer) +set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_n] ; ## G28 FMC_HPC_LA25_N (Sniffer) +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_p] ; ## G36 FMC_HPC_LA33_P +set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_n] ; ## G37 FMC_HPC_LA33_N + +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9528] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9371] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G12 FMC_HPC_LA08_P + +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports ad9528_reset_b] ; ## D26 FMC_HPC_LA26_P +set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports ad9528_sysref_req] ; ## D27 FMC_HPC_LA26_N +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports ad9371_tx1_enable] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports ad9371_tx2_enable] ; ## C18 FMC_HPC_LA14_P +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports ad9371_rx1_enable] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports ad9371_rx2_enable] ; ## C19 FMC_HPC_LA14_N +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports ad9371_test] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports ad9371_reset_b] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports ad9371_gpint] ; ## H11 FMC_HPC_LA04_N + +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_00] ; ## H19 FMC_HPC_LA15_P +set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_01] ; ## H20 FMC_HPC_LA15_N +set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_02] ; ## G18 FMC_HPC_LA16_P +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_03] ; ## G19 FMC_HPC_LA16_N +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_04] ; ## H25 FMC_HPC_LA21_P +set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_05] ; ## H26 FMC_HPC_LA21_N +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_06] ; ## C22 FMC_HPC_LA18_CC_P +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_07] ; ## C23 FMC_HPC_LA18_CC_N +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_15] ; ## G24 FMC_HPC_LA22_P (LVDS Pairs?) +set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_08] ; ## G25 FMC_HPC_LA22_N (LVDS Pairs?) +set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_09] ; ## H22 FMC_HPC_LA19_P (LVDS Pairs?) +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_10] ; ## H23 FMC_HPC_LA19_N (LVDS Pairs?) +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_11] ; ## G21 FMC_HPC_LA20_P (LVDS Pairs?) +set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_12] ; ## G22 FMC_HPC_LA20_N (LVDS Pairs?) +set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_14] ; ## G30 FMC_HPC_LA29_P (LVDS Pairs?) +set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_13] ; ## G31 FMC_HPC_LA29_N (LVDS Pairs?) +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_17] ; ## G15 FMC_HPC_LA12_P (LVDS Pairs?) +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_16] ; ## G16 FMC_HPC_LA12_N (LVDS Pairs?) +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_18] ; ## D12 FMC_HPC_LA05_N + +# clocks + +create_clock -name tx_ref_clk -period 8.00 [get_ports ref_clk0_p] +create_clock -name rx_ref_clk -period 8.00 [get_ports ref_clk1_p] +create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_os_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK] + diff --git a/CI/projects/adrv9371x/zc706/system_project.tcl b/CI/projects/adrv9371x/zc706/system_project.tcl new file mode 100644 index 0000000..6c2f97a --- /dev/null +++ b/CI/projects/adrv9371x/zc706/system_project.tcl @@ -0,0 +1,18 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_xilinx adrv9371x_zc706 +adi_project_files adrv9371x_zc706 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +adi_project_run adrv9371x_zc706 + + diff --git a/CI/projects/adrv9371x/zc706/system_project_rxtx.tcl b/CI/projects/adrv9371x/zc706/system_project_rxtx.tcl new file mode 100644 index 0000000..2e47a57 --- /dev/null +++ b/CI/projects/adrv9371x/zc706/system_project_rxtx.tcl @@ -0,0 +1,19 @@ +set ad_hdl_dir [pwd] +set ad_phdl_dir [pwd] +set proj_dir $ad_hdl_dir/projects/adrv9371x/zc706 + +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_xilinx adrv9371x_zc706 $proj_dir config_rxtx.tcl +adi_project_files adrv9371x_zc706 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +adi_project_run adrv9371x_zc706 + +# Copy the boot file to the root directory +file copy -force $proj_dir/boot $ad_hdl_dir/boot diff --git a/CI/projects/adrv9371x/zc706/system_top.v b/CI/projects/adrv9371x/zc706/system_top.v new file mode 100644 index 0000000..b5fc68e --- /dev/null +++ b/CI/projects/adrv9371x/zc706/system_top.v @@ -0,0 +1,343 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [14:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, + + output spdif, + + inout iic_scl, + inout iic_sda, + + input ref_clk0_p, + input ref_clk0_n, + input ref_clk1_p, + input ref_clk1_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, + output rx_sync_p, + output rx_sync_n, + output rx_os_sync_p, + output rx_os_sync_n, + input tx_sync_p, + input tx_sync_n, + input sysref_p, + input sysref_n, + + output spi_csn_ad9528, + output spi_csn_ad9371, + output spi_clk, + output spi_mosi, + input spi_miso, + + inout ad9528_reset_b, + inout ad9528_sysref_req, + inout ad9371_tx1_enable, + inout ad9371_tx2_enable, + inout ad9371_rx1_enable, + inout ad9371_rx2_enable, + inout ad9371_test, + inout ad9371_reset_b, + inout ad9371_gpint, + + inout ad9371_gpio_00, + inout ad9371_gpio_01, + inout ad9371_gpio_02, + inout ad9371_gpio_03, + inout ad9371_gpio_04, + inout ad9371_gpio_05, + inout ad9371_gpio_06, + inout ad9371_gpio_07, + inout ad9371_gpio_15, + inout ad9371_gpio_08, + inout ad9371_gpio_09, + inout ad9371_gpio_10, + inout ad9371_gpio_11, + inout ad9371_gpio_12, + inout ad9371_gpio_14, + inout ad9371_gpio_13, + inout ad9371_gpio_17, + inout ad9371_gpio_16, + inout ad9371_gpio_18, + + input sys_rst, + input sys_clk_p, + input sys_clk_n, + + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire ref_clk0; + wire ref_clk1; + wire rx_sync; + wire rx_os_sync; + wire tx_sync; + wire sysref; + + // instantiations + + IBUFDS_GTE2 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (ref_clk0_p), + .IB (ref_clk0_n), + .O (ref_clk0), + .ODIV2 ()); + + IBUFDS_GTE2 i_ibufds_ref_clk1 ( + .CEB (1'd0), + .I (ref_clk1_p), + .IB (ref_clk1_n), + .O (ref_clk1), + .ODIV2 ()); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + OBUFDS i_obufds_rx_os_sync ( + .I (rx_os_sync), + .O (rx_os_sync_p), + .OB (rx_os_sync_n)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + IBUFDS i_ibufds_sysref ( + .I (sysref_p), + .IB (sysref_n), + .O (sysref)); + + ad_iobuf #(.DATA_WIDTH(28)) i_iobuf ( + .dio_t ({gpio_t[59:32]}), + .dio_i ({gpio_o[59:32]}), + .dio_o ({gpio_i[59:32]}), + .dio_p ({ ad9528_reset_b, // 59 + ad9528_sysref_req, // 58 + ad9371_tx1_enable, // 57 + ad9371_tx2_enable, // 56 + ad9371_rx1_enable, // 55 + ad9371_rx2_enable, // 54 + ad9371_test, // 53 + ad9371_reset_b, // 52 + ad9371_gpint, // 51 + ad9371_gpio_00, // 50 + ad9371_gpio_01, // 49 + ad9371_gpio_02, // 48 + ad9371_gpio_03, // 47 + ad9371_gpio_04, // 46 + ad9371_gpio_05, // 45 + ad9371_gpio_06, // 44 + ad9371_gpio_07, // 43 + ad9371_gpio_15, // 42 + ad9371_gpio_08, // 41 + ad9371_gpio_09, // 40 + ad9371_gpio_10, // 39 + ad9371_gpio_11, // 38 + ad9371_gpio_12, // 37 + ad9371_gpio_14, // 36 + ad9371_gpio_13, // 35 + ad9371_gpio_17, // 34 + ad9371_gpio_16, // 33 + ad9371_gpio_18})); // 32 + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( + .dio_t (gpio_t[14:0]), + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_p (gpio_bd)); + + system_wrapper i_system_wrapper ( + .dac_fifo_bypass (gpio_o[60]), + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_odt (ddr3_odt), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (ref_clk1), + .rx_ref_clk_2 (ref_clk1), + .rx_sync_0 (rx_sync), + .rx_sync_2 (rx_os_sync), + .rx_sysref_0 (sysref), + .rx_sysref_2 (sysref), + .spdif (spdif), + .spi0_clk_i (spi_clk), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn_ad9528), + .spi0_csn_1_o (spi_csn_ad9371), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (spi_mosi), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'd0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'd0), + .spi1_sdo_i (1'd0), + .spi1_sdo_o (), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .sys_rst(sys_rst), + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (ref_clk1), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (sysref)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/CI/projects/common/boot/bl31.elf b/CI/projects/common/boot/bl31.elf new file mode 100644 index 0000000..9070408 Binary files /dev/null and b/CI/projects/common/boot/bl31.elf differ diff --git a/CI/projects/common/boot/zynq.bif b/CI/projects/common/boot/zynq.bif new file mode 100644 index 0000000..235acaa --- /dev/null +++ b/CI/projects/common/boot/zynq.bif @@ -0,0 +1,6 @@ +the_ROM_image: +{ +[bootloader]./fsbl.elf +./system_top.bit +./u-boot.elf +} diff --git a/CI/projects/common/boot/zynqmp.bif b/CI/projects/common/boot/zynqmp.bif new file mode 100644 index 0000000..08b9555 --- /dev/null +++ b/CI/projects/common/boot/zynqmp.bif @@ -0,0 +1,9 @@ +the_ROM_image: +{ +[fsbl_config] a53_x64 +[bootloader] ./fsbl.elf +[pmufw_image] ./pmufw.elf +[destination_device=pl] ./system_top.bit +[destination_cpu=a53-0,exception_level=el-3,trustzone] ./bl31.elf +[destination_cpu=a53-0,exception_level=el-2] ./u-boot-zcu.elf +} diff --git a/CI/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl b/CI/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl index f19c039..dc02741 100644 --- a/CI/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl +++ b/CI/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl @@ -4,9 +4,9 @@ ad_ip_instance proc_sys_reset axi_rstgen ad_ip_instance mig_7series axi_ddr_cntrl -file copy -force $ad_hdl_dir/projects/common/zc706/zc706_plddr3_mig.prj [get_property IP_DIR \ +file copy -force $ad_hdl_dir/projects/common/zc706/zc706_plddr3_mig.mk [get_property IP_DIR \ [get_ips [get_property CONFIG.Component_Name [get_bd_cells axi_ddr_cntrl]]]] -ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE zc706_plddr3_mig.prj +ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE zc706_plddr3_mig.mk create_bd_port -dir I -type rst sys_rst set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] diff --git a/CI/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl b/CI/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl index 31153fc..76727c2 100644 --- a/CI/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl +++ b/CI/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl @@ -4,9 +4,9 @@ ad_ip_instance proc_sys_reset axi_rstgen ad_ip_instance mig_7series axi_ddr_cntrl -file copy -force $ad_hdl_dir/projects/common/zc706/zc706_plddr3_mig.prj [get_property IP_DIR \ +file copy -force $ad_hdl_dir/projects/common/zc706/zc706_plddr3_mig.mk [get_property IP_DIR \ [get_ips [get_property CONFIG.Component_Name [get_bd_cells axi_ddr_cntrl]]]] -ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE zc706_plddr3_mig.prj +ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE zc706_plddr3_mig.mk create_bd_port -dir I -type rst sys_rst set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] diff --git a/CI/projects/common/zc706/zc706_plddr3_mig.prj b/CI/projects/common/zc706/zc706_plddr3_mig.mk similarity index 100% rename from CI/projects/common/zc706/zc706_plddr3_mig.prj rename to CI/projects/common/zc706/zc706_plddr3_mig.mk diff --git a/CI/projects/scripts/fixmake.sh b/CI/projects/scripts/fixmake.sh new file mode 100755 index 0000000..c14d8d2 --- /dev/null +++ b/CI/projects/scripts/fixmake.sh @@ -0,0 +1,3 @@ +grep "CC_FLAGS :=" pmufw/Makefile | grep -e "-Os" || sed -i '/-mxl-soft-mul/ s/$/ -Os -flto -ffat-lto-objects/' pmufw/Makefile +cd pmufw +make \ No newline at end of file diff --git a/CI/projects/scripts/fsbl_build.tcl b/CI/projects/scripts/fsbl_build.tcl index baee09d..653e591 100644 --- a/CI/projects/scripts/fsbl_build.tcl +++ b/CI/projects/scripts/fsbl_build.tcl @@ -1,3 +1,13 @@ + +if { $argc != 3 } { + set fpga_board "ZC706" +} else { + set fpga_board [lindex $argv 1] +} +puts "===========" +puts $fpga_board +puts "===========" + set cdir [pwd] set sdk_loc $cdir/vivado_prj.sdk @@ -6,9 +16,26 @@ hsi open_hw_design $sdk_loc/system_top.hdf set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0] sdk set_workspace $sdk_loc sdk create_hw_project -name hw_0 -hwspec $sdk_loc/system_top.hdf -sdk create_app_project -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL} + +# Create project +if {$fpga_board eq "ZCU102"} { + sdk create_app_project -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq MP FSBL} +} else { + sdk create_app_project -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL} +} + sdk configapp -app fsbl build-config release sdk build_project -type all +# Collect necessary files +file copy -force $cdir/projects/common/boot/zynq.bif $cdir/boot/zynq.bif +file copy -force $sdk_loc/fsbl/Release/fsbl.elf $cdir/boot/fsbl.elf +file copy -force $sdk_loc/hw_0/system_top.bit $cdir/boot/system_top.bit +cd $cdir/boot + # Create the BOOT.bin +if {$fpga_board eq "ZCU102"} { +exec bootgen -image $cdir/boot/zynqmp.bif -w -o i $cdir/boot/BOOT.BIN +} else { exec bootgen -image $cdir/boot/zynq.bif -w -o i $cdir/boot/BOOT.BIN +} diff --git a/CI/projects/scripts/fsbl_build_zynq.tcl b/CI/projects/scripts/fsbl_build_zynq.tcl new file mode 100644 index 0000000..92ae603 --- /dev/null +++ b/CI/projects/scripts/fsbl_build_zynq.tcl @@ -0,0 +1,29 @@ + + +### Calling script must have system_top.hdf u-boot.elf + + +set cdir [pwd] +set sdk_loc $cdir/vivado_prj.sdk + +### Create fsbl +hsi open_hw_design $sdk_loc/system_top.hdf +set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0] +sdk setws $sdk_loc +sdk createhw -name hw_0 -hwspec $sdk_loc/system_top.hdf +sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL} +configapp -app fsbl build-config release +sdk projects -build -type all + +### Copy common zynq.bif file +file copy -force $cdir/projects/common/boot/zynq.bif $cdir/boot/zynq.bif + +### Copy fsbl and system_top.bit into the output folder +file copy -force $sdk_loc/fsbl/Release/fsbl.elf $cdir/boot/fsbl.elf +file copy -force $sdk_loc/hw_0/system_top.bit $cdir/boot/system_top.bit + +### Build BOOT.BIN +cd $cdir/boot +exec bootgen -arch zynq -image zynq.bif -o BOOT.BIN -w +exit + diff --git a/CI/projects/scripts/fsbl_build_zynqmp.tcl b/CI/projects/scripts/fsbl_build_zynqmp.tcl new file mode 100644 index 0000000..e72cab8 --- /dev/null +++ b/CI/projects/scripts/fsbl_build_zynqmp.tcl @@ -0,0 +1,34 @@ + + +### Calling script must have system_top.hdf u-boot.elf + + +set cdir [pwd] +set sdk_loc $cdir/vivado_prj.sdk + +### Create fsbl +hsi open_hw_design $sdk_loc/system_top.hdf +set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0] +sdk setws $sdk_loc +sdk createhw -name hw_0 -hwspec $sdk_loc/system_top.hdf +sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq MP FSBL} +configapp -app fsbl build-config release +sdk projects -build -type all + +### Create create_pmufw_project.tcl +#set hwdsgn [open_hw_design $sdk_loc/system_top.hdf] +#generate_app -hw $hwdsgn -os standalone -proc psu_pmu_0 -app zynqmp_pmufw -sw pmufw -dir pmufw + +### Copy common zynqmp.bif and bl31.elf file +file copy -force $cdir/projects/common/boot/zynqmp.bif $cdir/boot/zynqmp.bif +file copy -force $cdir/projects/common/boot/bl31.elf $cdir/boot/bl31.elf + +### Copy fsbl and system_top.bit into the output folder +file copy -force $sdk_loc/fsbl/Release/fsbl.elf $cdir/boot/fsbl.elf +file copy -force $sdk_loc/hw_0/system_top.bit $cdir/boot/system_top.bit +file copy -force $cdir/pmufw/executable.elf $cdir/boot/pmufw.elf + +### Build BOOT.BIN +cd $cdir/boot +exec bootgen -arch zynqmp -image zynqmp.bif -o BOOT.BIN -w +exit diff --git a/CI/projects/scripts/pmufw_zynqmp.tcl b/CI/projects/scripts/pmufw_zynqmp.tcl new file mode 100644 index 0000000..ec456f8 --- /dev/null +++ b/CI/projects/scripts/pmufw_zynqmp.tcl @@ -0,0 +1,8 @@ + +set cdir [pwd] +set sdk_loc $cdir/vivado_prj.sdk + +### Create create_pmufw_project.tcl +set hwdsgn [open_hw_design $sdk_loc/system_top.hdf] +generate_app -hw $hwdsgn -os standalone -proc psu_pmu_0 -app zynqmp_pmufw -sw pmufw -dir pmufw +quit diff --git a/CI/scripts/Docker b/CI/scripts/Docker new file mode 100644 index 0000000..0183c15 --- /dev/null +++ b/CI/scripts/Docker @@ -0,0 +1,8 @@ +FROM ubuntu:16.04 + +MAINTAINER Travis Collins +RUN apt update +RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libpng-dev libfreetype6-dev libblas-dev liblapack-dev gfortran build-essential xorg +RUN DEBIAN_FRONTEND=noninteractive apt-get install -y openjdk-8-jre openjdk-8-jdk libgtk2.0-0 libxss1 libxt6 zip unzip curl wget tar git xvfb +RUN DEBIAN_FRONTEND=noninteractive dpkg --add-architecture i386 +RUN DEBIAN_FRONTEND=noninteractive apt-get install -y lib32stdc++6 diff --git a/CI/scripts/Makefile b/CI/scripts/Makefile index 78a4ef2..cdd0558 100644 --- a/CI/scripts/Makefile +++ b/CI/scripts/Makefile @@ -3,6 +3,10 @@ # Example # make build MLRELEASE=R2018b HDLBRANCH=hdl_2018_r1 +SHELL := /bin/bash + +MLFLAGS := -nodisplay -nodesktop -nosplash + ifeq ($(MLRELEASE),) MLRELEASE := R2018b endif @@ -12,7 +16,8 @@ HDLBRANCH := hdl_2018_r1 endif ifeq ($(OS),Windows_NT) -$(error Build system does not currently support Windows) +MLPATH := /cygdrive/c/Program\ Files/MATLAB +MLFLAGS := $(MLFLAGS) -wait else UNAME_S := $(shell uname -s) ifeq ($(UNAME_S),Linux) @@ -24,6 +29,7 @@ MLRELEASE := MATLAB_${MLRELEASE}.app endif endif + GITTAG := $(shell git describe --tags HEAD) .ONESHELL: @@ -68,27 +74,34 @@ test_installer: cp *.mltbx test/ ; \ cp hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m test/hdlcoder_board_customization_local.m ; \ sed -i "s/hdlcoder_board_customization/hdlcoder_board_customization_local/g" test/hdlcoder_board_customization_local.m ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab -nodisplay -r "cd('test');runInstallerTests;" + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "cd('test');runInstallerTests;" test: cd ../.. ; \ cp hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m test/hdlcoder_board_customization_local.m ; \ sed -i "s/hdlcoder_board_customization/hdlcoder_board_customization_local/g" test/hdlcoder_board_customization_local.m ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab -nodisplay -r "cd('test');runTests;" + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "cd('test');runTests;" test_streaming: cd ../.. ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab -nodisplay -r "addpath(genpath('test'));addpath(genpath('deps'));hwTestRunner;" + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('test'));addpath(genpath('deps'));runHWTests;" + +test_evm: + cd ../.. ; \ + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('test'));addpath(genpath('deps'));hwTestRunner;" test_modem: cd ../.. ; \ - ${MLPATH}/$(MLRELEASE)/bin/matlab -nodisplay -r "addpath(genpath('hdl_wa_bsp'));cd('targeting_models');addpath(genpath('modem-qpsk'))" + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('hdl_wa_bsp'));cd('targeting_models');addpath(genpath('modem-qpsk'))" + +test_synth: + bash synth_designs.sh gen_tlbx: - ${MLPATH}/$(MLRELEASE)/bin/matlab -nodisplay -r "genTlbx;exit();" + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "genTlbx;exit();" linter: - ${MLPATH}/$(MLRELEASE)/bin/matlab -nodisplay -r "linter;exit();" + ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "linter;exit();" zip: cd ../.. ; \ diff --git a/CI/scripts/adi_build.tcl b/CI/scripts/adi_build.tcl index 98032ec..f85bf7c 100644 --- a/CI/scripts/adi_build.tcl +++ b/CI/scripts/adi_build.tcl @@ -1,3 +1,14 @@ +global fpga_board + +if {[info exists fpga_board]} { + puts "===========" + puts $fpga_board + puts "===========" +} else { + # Set to something not ZCU102 + set fpga_board "ZYNQ" +} + # Build the project update_compile_order -fileset sources_1 reset_run impl_1 @@ -20,7 +31,45 @@ file copy -force vivado_prj.runs/impl_1/system_top.sysdef $sdk_loc/system_top.hd close_project # Create the BOOT.bin -exec xsdk -batch -source $cdir/projects/scripts/fsbl_build.tcl -wait +#exec xsdk -batch -source $cdir/projects/scripts/fsbl_build.tcl -tclargs $fpga_board -wait + +if {$fpga_board eq "ZCU102"} { + exec hsi -source $cdir/projects/scripts/pmufw_zynqmp.tcl + file copy -force $cdir/projects/scripts/fixmake.sh $cdir/fixmake.sh + exec chmod +x fixmake.sh + + #exec ./fixmake.sh + #cd pmufw + #exec make + #cd .. + if [catch "exec -ignorestderr ./fixmake.sh" ret opt] { + set makeRet [lindex [dict get $opt -errorcode] end] + puts "make returned with $makeRet" + } + if {[file exist pmufw/executable.elf] eq 0} { + puts "ERROR: pmufw not built" + return -code error 10 + } else { + puts "pmufw built correctly!" + } + + exec xsdk -batch -source $cdir/projects/scripts/fsbl_build_zynqmp.tcl + if {[file exist boot/BOOT.BIN] eq 0} { + puts "ERROR: BOOT.BIN not built" + return -code error 11 + } else { + puts "BOOT.BIN built correctly!" + } + +} else { + exec xsdk -batch -source $cdir/projects/scripts/fsbl_build_zynq.tcl + if {[file exist boot/BOOT.BIN] eq 0} { + puts "ERROR: BOOT.BIN not built" + return -code error 11 + } else { + puts "BOOT.BIN built correctly!" + } +} puts "------------------------------------" puts "Embedded system build completed." diff --git a/CI/scripts/bsp.prj b/CI/scripts/bsp.prj index d297c4b..2ce9591 100644 --- a/CI/scripts/bsp.prj +++ b/CI/scripts/bsp.prj @@ -130,29 +130,6 @@ test/* - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/hdlverifier/supportpackages/fpgadebug/+hdlverifier/FPGADataReader.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/libiio/axi/+matlabshared/+libiio/+aximm/read.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/libiio/axi/+matlabshared/+libiio/+aximm/write.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrpluginbase/host/+comm/+internal/SDRSystemBaseUpdateBuildInfo.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrpluginbase/host/+sdrplugin/+internal/SDRPluginManager.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrpluginbase/host/funcs/sdrdev.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrpluginbase/host/funcs/sdrrx.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrpluginbase/host/funcs/sdrtx.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/e310/manual/+comm/SDRRxE310.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/e310/manual/+comm/SDRTxE310.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/plutoradio/+comm/SDRRxPluto.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/plutoradio/+comm/SDRTxPluto.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/plutoradio/findPlutoRadio.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/xpicozedsdr/manual/+comm/SDRRxADIRFSOM.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/xpicozedsdr/manual/+comm/SDRTxADIRFSOM.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/xzc706afmc3/manual/+comm/SDRRxZC706FMC234.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/xzc706afmc3/manual/+comm/SDRTxZC706FMC234.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/xzedboardafmc3/manual/+comm/SDRRxZedBoardFMC234.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/xzedboardafmc3/manual/+comm/SDRTxZedBoardFMC234.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/zynqradio/+comm/SDRRxAD936x.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/zynqradio/+comm/SDRTxAD936x.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrz/sdrz/+comm/SDRRxZynqFMC234.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrz/sdrz/+comm/SDRTxZynqFMC234.p @@ -204,4 +181,4 @@ test/* true - \ No newline at end of file + diff --git a/CI/scripts/bsp.tmpl b/CI/scripts/bsp.tmpl index eb22762..2eaf97e 100644 --- a/CI/scripts/bsp.tmpl +++ b/CI/scripts/bsp.tmpl @@ -108,29 +108,7 @@ mltbx/* - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/hdlverifier/supportpackages/fpgadebug/+hdlverifier/FPGADataReader.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/libiio/axi/+matlabshared/+libiio/+aximm/read.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/libiio/axi/+matlabshared/+libiio/+aximm/write.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrpluginbase/host/+comm/+internal/SDRSystemBaseUpdateBuildInfo.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrpluginbase/host/+sdrplugin/+internal/SDRPluginManager.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrpluginbase/host/funcs/sdrdev.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrpluginbase/host/funcs/sdrrx.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrpluginbase/host/funcs/sdrtx.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/e310/manual/+comm/SDRRxE310.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/e310/manual/+comm/SDRTxE310.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/plutoradio/+comm/SDRRxPluto.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/plutoradio/+comm/SDRTxPluto.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/plutoradio/findPlutoRadio.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/xpicozedsdr/manual/+comm/SDRRxADIRFSOM.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/xpicozedsdr/manual/+comm/SDRTxADIRFSOM.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/xzc706afmc3/manual/+comm/SDRRxZC706FMC234.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/xzc706afmc3/manual/+comm/SDRTxZC706FMC234.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/xzedboardafmc3/manual/+comm/SDRRxZedBoardFMC234.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/xzedboardafmc3/manual/+comm/SDRTxZedBoardFMC234.m - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/zynqradio/+comm/SDRRxAD936x.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrplug/sdrplugins/zynqradio/+comm/SDRTxAD936x.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrz/sdrz/+comm/SDRRxZynqFMC234.p - /home/tcollins/Documents/MATLAB/SupportPackages/R2018b/toolbox/shared/sdr/sdrz/sdrz/+comm/SDRTxZynqFMC234.p + /mlhsp/toolbox/shared/sdr/sdrplug/sdrplugins/plutoradio/findPlutoRadio.p diff --git a/CI/scripts/dockermake b/CI/scripts/dockermake new file mode 100755 index 0000000..7bc4230 --- /dev/null +++ b/CI/scripts/dockermake @@ -0,0 +1,3 @@ +#!/bin/bash +docker build . -t matlabci -f CI/scripts/Docker +docker run --rm -e "LM_LICENSE_FILE=$LM_LICENSE_FILE" -e "XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE" -e "MLRELEASE=$MLRELEASE" -e "HDLBRANCH=$HDLBRANCH" -v "$(pwd):/work" -v /mlhsp:/mlhspro:ro -v /usr/local/MATLAB:/usr/local/MATLAB -v /root/.matlab:/root/.matlabro:ro -v /root/.Xilinx:/root/.Xilinxro:ro -v /opt/Xilinx:/opt/Xilinx --mac-address="$ADDR" matlabci /bin/bash -c "cd /work && chmod +x CI/scripts/setupDocker.sh && ./CI/scripts/setupDocker.sh && make -C CI/scripts '$@'" diff --git a/CI/scripts/genTlbx.m b/CI/scripts/genTlbx.m index b1abb12..fd57a75 100644 --- a/CI/scripts/genTlbx.m +++ b/CI/scripts/genTlbx.m @@ -19,7 +19,7 @@ fclose(fid); cd('../..'); -addpath(matlabshared.supportpkg.getSupportPackageRoot); +addpath(genpath(matlabshared.supportpkg.getSupportPackageRoot)); addpath(genpath('.')); rmpath(genpath('.')); ps = {'doc','hdl_wa_bsp','hil_models','targeting_models','deps'}; diff --git a/CI/scripts/setupDocker.sh b/CI/scripts/setupDocker.sh new file mode 100755 index 0000000..4e6fc05 --- /dev/null +++ b/CI/scripts/setupDocker.sh @@ -0,0 +1,9 @@ +#!/bin/bash +# This file is run inside of the docker container +echo "Copying HSP files" +cp -r /mlhspro /mlhsp +echo "Copying .matlab" +cp -r /root/.matlabro /root/.matlab +echo "Copying .Xilinx" +cp -r /root/.Xilinxro /root/.Xilinx +source /opt/Xilinx/Vivado/2017.4/settings64.sh diff --git a/CI/scripts/synth_designs.sh b/CI/scripts/synth_designs.sh new file mode 100644 index 0000000..661f3c1 --- /dev/null +++ b/CI/scripts/synth_designs.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +MLFLAGS="-nodisplay -nodesktop -nosplash" + +if [ -z "$MLRELEASE" ] +then + MLRELEASE=R2018b +fi + +MLPATH=/usr/local/MATLAB + +cd ../.. +cp hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m test/hdlcoder_board_customization_local.m +sed -i "s/hdlcoder_board_customization/hdlcoder_board_customization_local/g" test/hdlcoder_board_customization_local.m +source /opt/Xilinx/Vivado/2017.4/settings64.sh +Xvfb :77 & +export DISPLAY=:77 +export SWT_GTK3=0 +source /opt/Xilinx/Vivado/2017.4/settings64.sh +$MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "cd('test');runSynthTests;" +kill -9 `pidof Xvfb` diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9009/+common/plugin_rd.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9009/+common/plugin_rd.m index 8dbbb09..997d735 100644 --- a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9009/+common/plugin_rd.m +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9009/+common/plugin_rd.m @@ -53,7 +53,12 @@ hRD.CustomFiles = {... fullfile('projects')..., fullfile('library')..., - }; + }; + +hRD.addParameter( ... + 'ParameterID', 'fpga_board', ... + 'DisplayName', 'FPGA Boad', ... + 'DefaultValue', upper(board)); %% Add interfaces % add clock interface diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+common/plugin_board.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+common/plugin_board.m index b647ba9..e367c50 100644 --- a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+common/plugin_board.m +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+common/plugin_board.m @@ -8,22 +8,24 @@ % FPGA Device hB.FPGAVendor = 'Xilinx'; -hB.FPGAFamily = 'Zynq UltraScale+'; % Determine the device based on the board switch(upper(board)) -% case 'ZC706' -% hB.FPGADevice = sprintf('xc7%s', 'z045'); -% hB.FPGAPackage = 'ffg900'; -% hB.FPGASpeed = '-2'; - case 'ZCU102' - hB.FPGADevice = sprintf('xc%s', 'zu9eg-ffvb1156-2-e'); - hB.FPGAPackage = ''; - hB.FPGASpeed = ''; - otherwise - hB.FPGADevice = sprintf('xc%s', 'zu9eg-ffvb1156-2-e'); - hB.FPGAPackage = ''; - hB.FPGASpeed = ''; + case 'ZC706' + hB.FPGAFamily = 'Zynq'; + hB.FPGADevice = sprintf('xc7%s', 'z045'); + hB.FPGAPackage = 'ffg900'; + hB.FPGASpeed = '-2'; + case 'ZCU102' + hB.FPGAFamily = 'Zynq UltraScale+'; + hB.FPGADevice = sprintf('xc%s', 'zu9eg-ffvb1156-2-e'); + hB.FPGAPackage = ''; + hB.FPGASpeed = ''; + otherwise + hB.FPGAFamily = 'Zynq UltraScale+'; + hB.FPGADevice = sprintf('xc%s', 'zu9eg-ffvb1156-2-e'); + hB.FPGAPackage = ''; + hB.FPGASpeed = ''; end % Tool Info diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+common/plugin_rd.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+common/plugin_rd.m index 5ef0bd3..0194605 100644 --- a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+common/plugin_rd.m +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+common/plugin_rd.m @@ -46,6 +46,11 @@ 'DisplayName', 'Reference Type', ... 'DefaultValue', design); +hRD.addParameter( ... + 'ParameterID', 'fpga_board', ... + 'DisplayName', 'FPGA Boad', ... + 'DefaultValue', upper(board)); + %% Add interfaces % add clock interface switch(upper(design)) diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/add_io.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/add_io.m new file mode 100644 index 0000000..9c6b719 --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/add_io.m @@ -0,0 +1,154 @@ +function add_io(hRD, type) + +%% AXI Interface +% add AXI4 and AXI4-Lite slave interfaces +hRD.addAXI4SlaveInterface( ... + 'InterfaceConnection', 'axi_cpu_interconnect/M18_AXI', ... % ADC DMA BUS + 'BaseAddress', '0x45000000', ... + 'MasterAddressSpace', 'sys_ps7/Data'); + +if contains(lower(type),'rx') + %% RX ONLY + % Reference design interfaces + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data Valid OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_valid', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'util_ad9371_rx_cpack/adc_valid_0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9371_rx_cpack/adc_data_0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_1', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9371_rx_cpack/adc_data_1', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 2 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_2', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9371_rx_cpack/adc_data_2', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 3 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_3', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9371_rx_cpack/adc_data_3', ... + 'IsRequired', false); + % INPUTS axi_ad9371_v1_0 + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9371 ADC Data I0', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_0_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9371_core/adc_data_i0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9371 ADC Data Q0', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_1_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9371_core/adc_data_q0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9371 ADC Data I1', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_2_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9371_core/adc_data_i1', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9371 ADC Data Q1', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_3_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9371_core/adc_data_q1', ... + 'IsRequired', false); +end + +if contains(lower(type),'tx') + %% TX ONLY + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9371 DAC Data I0', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9371_dac_data_i0', ... + 'PortWidth', 32, ... + 'InterfaceConnection', 'axi_ad9371_core/dac_data_i0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9371 DAC Data Q0', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9371_dac_data_q0', ... + 'PortWidth', 32, ... + 'InterfaceConnection', 'axi_ad9371_core/dac_data_q0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9371 DAC Data I1', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9371_dac_data_i1', ... + 'PortWidth', 32, ... + 'InterfaceConnection', 'axi_ad9371_core/dac_data_i1', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9371 DAC Data Q1', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9371_dac_data_q1', ... + 'PortWidth', 32, ... + 'InterfaceConnection', 'axi_ad9371_core/dac_data_q1', ... + 'IsRequired', false); + + % Inputs to generated IP from upack core + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_00', ... + 'PortWidth', 32, ... + 'InterfaceConnection', 'util_ad9371_tx_upack/dac_data_0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_01', ... + 'PortWidth', 32, ... + 'InterfaceConnection', 'util_ad9371_tx_upack/dac_data_1', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 2 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_02', ... + 'PortWidth', 32, ... + 'InterfaceConnection', 'util_ad9371_tx_upack/dac_data_2', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 3 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_03', ... + 'PortWidth', 32, ... + 'InterfaceConnection', 'util_ad9371_tx_upack/dac_data_3', ... + 'IsRequired', false); + + +end diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/hdlcoder_ref_design_customization.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/hdlcoder_ref_design_customization.m new file mode 100644 index 0000000..b76bd46 --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/hdlcoder_ref_design_customization.m @@ -0,0 +1,22 @@ +function [rd, boardName] = hdlcoder_ref_design_customization +% Reference design plugin registration file +% 1. The registration file with this name inside of a board plugin folder +% will be picked up +% 2. Any registration file with this name on MATLAB path will also be picked up +% 3. The registration file returns a cell array pointing to the location of +% the reference design plugins +% 4. The registration file also returns its associated board name +% 5. Reference design plugin must be a package folder accessible from +% MATLAB path, and contains a reference design definition file + +% Copyright 2013-2014 The MathWorks, Inc. + +rd = {... + 'AnalogDevices.adrv9371x.zc706.plugin_rd_rx', ... + 'AnalogDevices.adrv9371x.zc706.plugin_rd_tx', ... + 'AnalogDevices.adrv9371x.zc706.plugin_rd_rxtx', ... + }; + +boardName = 'AnalogDevices ADRV9371 ZC706'; + +end diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_board.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_board.m new file mode 100644 index 0000000..601b7fe --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_board.m @@ -0,0 +1,8 @@ +function hP = plugin_board() +% Zynq Platform PCore +% Use Plugin API to create board plugin object + +% Copyright 2015 The MathWorks, Inc. + +% Call the common board definition function +hP = AnalogDevices.adrv9371x.common.plugin_board('ZC706'); diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_rd_rx.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_rd_rx.m new file mode 100644 index 0000000..4456e09 --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_rd_rx.m @@ -0,0 +1,6 @@ +function hRD = plugin_rd_rx +% Reference design definition + +% Call the common reference design definition function +hRD = AnalogDevices.adrv9371x.common.plugin_rd('ZC706', 'Rx'); +AnalogDevices.adrv9371x.zc706.add_io(hRD, 'Rx'); diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_rd_rxtx.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_rd_rxtx.m new file mode 100644 index 0000000..c5a91cd --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_rd_rxtx.m @@ -0,0 +1,8 @@ +function hRD = plugin_rd_rxtx +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Call the common reference design definition function +hRD = AnalogDevices.adrv9371x.common.plugin_rd('ZC706', 'Rx & Tx'); +AnalogDevices.adrv9371x.zc706.add_io(hRD, 'Rx & Tx'); diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_rd_tx.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_rd_tx.m new file mode 100644 index 0000000..81a67b0 --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9371x/+zc706/plugin_rd_tx.m @@ -0,0 +1,8 @@ +function hRD = plugin_rd_tx +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Call the common reference design definition function +hRD = AnalogDevices.adrv9371x.common.plugin_rd('ZC706', 'Tx'); +AnalogDevices.adrv9371x.zc706.add_io(hRD, 'Tx'); diff --git a/hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m b/hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m index 00e572e..42edb92 100644 --- a/hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m +++ b/hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m @@ -1,7 +1,7 @@ function r = hdlcoder_board_customization % Board plugin registration file % 1. Any registration file with this name on MATLAB path will be picked up -% 2. Registration file returns a cell array pointing to the location of +% 2. Registration file returns a cell array pointing to the location of % the board plugins % 3. Board plugin must be a package folder accessible from MATLAB path, % and contains a board definition file @@ -13,42 +13,43 @@ 'AnalogDevices.adrv9009.zcu102.tx.plugin_board', ... 'AnalogDevices.adrv9009.zcu102.rx_tx.plugin_board', ... 'AnalogDevices.adrv9371x.zcu102.plugin_board', ... - 'AnalogDevices.fmcomms2.zed.tx.plugin_board', ... - 'AnalogDevices.fmcomms2.zed.rx_tx.plugin_board', ... - 'AnalogDevices.fmcomms2.zc702.rx.plugin_board', ... - 'AnalogDevices.fmcomms2.zc702.tx.plugin_board', ... - 'AnalogDevices.fmcomms2.zc702.rx_tx.plugin_board', ... - 'AnalogDevices.fmcomms2.zc706.rx.plugin_board', ... - 'AnalogDevices.fmcomms2.zc706.tx.plugin_board', ... - 'AnalogDevices.fmcomms2.zc706.rx_tx.plugin_board', ... - 'AnalogDevices.fmcomms5.zc702.rx.plugin_board', ... - 'AnalogDevices.fmcomms5.zc702.tx.plugin_board', ... - 'AnalogDevices.fmcomms5.zc702.rx_tx.plugin_board', ... - 'AnalogDevices.fmcomms5.zc706.rx.plugin_board', ... - 'AnalogDevices.fmcomms5.zc706.tx.plugin_board', ... - 'AnalogDevices.fmcomms5.zc706.rx_tx.plugin_board', ... - 'AnalogDevices.adrv9364z7020.ccbox_lvds.rx.plugin_board', ... - 'AnalogDevices.adrv9364z7020.ccbox_lvds.tx.plugin_board', ... - 'AnalogDevices.adrv9364z7020.ccbox_lvds.rx_tx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccbox_lvds.modem.plugin_board', ... - 'AnalogDevices.adrv9364z7020.ccbob_cmos.rx.plugin_board', ... - 'AnalogDevices.adrv9364z7020.ccbob_cmos.tx.plugin_board', ... - 'AnalogDevices.adrv9364z7020.ccbob_cmos.rx_tx.plugin_board', ... - 'AnalogDevices.adrv9364z7020.ccbob_lvds.rx.plugin_board', ... - 'AnalogDevices.adrv9364z7020.ccbob_lvds.tx.plugin_board', ... - 'AnalogDevices.adrv9364z7020.ccbob_lvds.rx_tx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccbox_lvds.rx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccbox_lvds.tx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccbox_lvds.rx_tx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccbob_cmos.rx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccbob_cmos.tx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccbob_cmos.rx_tx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccbob_lvds.rx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccbob_lvds.tx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccbob_lvds.rx_tx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccfmc_lvds.rx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccfmc_lvds.tx.plugin_board', ... - 'AnalogDevices.adrv9361z7035.ccfmc_lvds.rx_tx.plugin_board', ... + 'AnalogDevices.adrv9371x.zc706.plugin_board', ... + 'AnalogDevices.fmcomms2.zed.tx.plugin_board', ... + 'AnalogDevices.fmcomms2.zed.rx_tx.plugin_board', ... + 'AnalogDevices.fmcomms2.zc702.rx.plugin_board', ... + 'AnalogDevices.fmcomms2.zc702.tx.plugin_board', ... + 'AnalogDevices.fmcomms2.zc702.rx_tx.plugin_board', ... + 'AnalogDevices.fmcomms2.zc706.rx.plugin_board', ... + 'AnalogDevices.fmcomms2.zc706.tx.plugin_board', ... + 'AnalogDevices.fmcomms2.zc706.rx_tx.plugin_board', ... + 'AnalogDevices.fmcomms5.zc702.rx.plugin_board', ... + 'AnalogDevices.fmcomms5.zc702.tx.plugin_board', ... + 'AnalogDevices.fmcomms5.zc702.rx_tx.plugin_board', ... + 'AnalogDevices.fmcomms5.zc706.rx.plugin_board', ... + 'AnalogDevices.fmcomms5.zc706.tx.plugin_board', ... + 'AnalogDevices.fmcomms5.zc706.rx_tx.plugin_board', ... + 'AnalogDevices.adrv9364z7020.ccbox_lvds.rx.plugin_board', ... + 'AnalogDevices.adrv9364z7020.ccbox_lvds.tx.plugin_board', ... + 'AnalogDevices.adrv9364z7020.ccbox_lvds.rx_tx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccbox_lvds.modem.plugin_board', ... + 'AnalogDevices.adrv9364z7020.ccbob_cmos.rx.plugin_board', ... + 'AnalogDevices.adrv9364z7020.ccbob_cmos.tx.plugin_board', ... + 'AnalogDevices.adrv9364z7020.ccbob_cmos.rx_tx.plugin_board', ... + 'AnalogDevices.adrv9364z7020.ccbob_lvds.rx.plugin_board', ... + 'AnalogDevices.adrv9364z7020.ccbob_lvds.tx.plugin_board', ... + 'AnalogDevices.adrv9364z7020.ccbob_lvds.rx_tx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccbox_lvds.rx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccbox_lvds.tx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccbox_lvds.rx_tx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccbob_cmos.rx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccbob_cmos.tx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccbob_cmos.rx_tx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccbob_lvds.rx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccbob_lvds.tx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccbob_lvds.rx_tx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccfmc_lvds.rx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccfmc_lvds.tx.plugin_board', ... + 'AnalogDevices.adrv9361z7035.ccfmc_lvds.rx_tx.plugin_board', ... }; end % LocalWords: Zynq ZC diff --git a/targeting_models/modem-qpsk/test/hdl/checkTimingReport.m b/targeting_models/modem-qpsk/test/hdl/checkTimingReport.m index af8ac6c..ce16de0 100644 --- a/targeting_models/modem-qpsk/test/hdl/checkTimingReport.m +++ b/targeting_models/modem-qpsk/test/hdl/checkTimingReport.m @@ -11,7 +11,14 @@ full = [path,'/',filename]; if ~isfile(full) - error(['No timing report found under: ',full]); + full1 = full; + % Try ZYNQMP naming + path = [hdl_prj,'/vivado_ip_prj/vivado_prj.runs/impl_1']; + filename = 'system_top_timing_summary_routed.rpt'; + full = [path,'/',filename]; + if ~isfile(full) + error(['No timing report found under: ',full,' or ',full1]); + end end fid = fopen(full); diff --git a/test/AD9361Tests.m b/test/AD9361Tests.m index b69b0f6..515b037 100644 --- a/test/AD9361Tests.m +++ b/test/AD9361Tests.m @@ -1,7 +1,16 @@ -classdef AD9361Tests < matlab.unittest.TestCase +classdef AD9361Tests < HardwareTests properties uri = 'ip:192.168.2.1'; + author = 'ADI'; + end + + methods(TestClassSetup) + % Check hardware connected + function CheckForHardware(testCase) + Device = @()adi.AD9361.Rx; + testCase.CheckDevice('ip',Device,testCase.uri(4:end),false); + end end methods (Static) diff --git a/test/AD9363Tests.m b/test/AD9363Tests.m index 62e471a..cdf757d 100644 --- a/test/AD9363Tests.m +++ b/test/AD9363Tests.m @@ -1,7 +1,16 @@ -classdef AD9363Tests < matlab.unittest.TestCase +classdef AD9363Tests < HardwareTests properties uri = 'ip:192.168.2.1'; + author = 'ADI'; + end + + methods(TestClassSetup) + % Check hardware connected + function CheckForHardware(testCase) + Device = @()adi.AD9363.Rx; + testCase.CheckDevice('ip',Device,testCase.uri(4:end),false); + end end methods (Static) @@ -33,6 +42,68 @@ function testAD9363LoOutOfRange(testCase) end end + function testAD9363AGCSettings(testCase) + rx = adi.AD9363.Rx('uri',testCase.uri); + % Update AGC settings + rx.CustomAGC = 1; + rx.AttackDelay = 47; + rx.PeakOverloadWaitTime = 20; + rx.AGCLockLevel = 101; + rx.DecStepSizeFullTableCase3 = 5; + rx.ADCLargeOverloadThresh = 199; + rx.ADCSmallOverloadThresh = 21; + rx.DecStepSizeFullTableCase2 = 5; + rx.DecStepSizeFullTableCase1 = 12; + rx.LargeLMTOverloadThresh = 12; + rx.SmallLMTOverloadThresh = 11; + rx.SettlingDelay = 4; + rx.EnergyLostThresh = 47; + rx.LowPowerThresh = 34; + rx.IncrementGainStep = 4; + rx.FAGCLockLevelGainIncreaseUpperLimit = 63; + rx.FAGCLPThreshIncrementTime = 102; + rx.DecPowMeasurementDuration = 7; + + rx(); + % Read AGC settings from hardware + rAttackDelay = ReadFromRegister(rx, 'AttackDelay'); + testCase.verifyEqual(rAttackDelay,rx.AttackDelay,'Unexpected value for AttackDelay returned'); + rPeakOverloadWaitTime = ReadFromRegister(rx, 'PeakOverloadWaitTime'); + testCase.verifyEqual(rPeakOverloadWaitTime,rx.PeakOverloadWaitTime,'Unexpected value for PeakOverloadWaitTime returned'); + rAGCLockLevel = ReadFromRegister(rx, 'AGCLockLevel'); + testCase.verifyEqual(rAGCLockLevel,rx.AGCLockLevel,'Unexpected value for AGCLockLevel returned'); + rDecStepSizeFullTableCase3 = ReadFromRegister(rx, 'DecStepSizeFullTableCase3'); + testCase.verifyEqual(rDecStepSizeFullTableCase3,rx.DecStepSizeFullTableCase3,'Unexpected value for DecStepSizeFullTableCase3 returned'); + rADCLargeOverloadThresh = ReadFromRegister(rx, 'ADCLargeOverloadThresh'); + testCase.verifyEqual(rADCLargeOverloadThresh,rx.ADCLargeOverloadThresh,'Unexpected value for ADCLargeOverloadThresh returned'); + rADCSmallOverloadThresh = ReadFromRegister(rx, 'ADCSmallOverloadThresh'); + testCase.verifyEqual(rADCSmallOverloadThresh,rx.ADCSmallOverloadThresh,'Unexpected value for ADCSmallOverloadThresh returned'); + rDecStepSizeFullTableCase2 = ReadFromRegister(rx, 'DecStepSizeFullTableCase2'); + testCase.verifyEqual(rDecStepSizeFullTableCase2,rx.DecStepSizeFullTableCase2,'Unexpected value for DecStepSizeFullTableCase2 returned'); + rDecStepSizeFullTableCase1 = ReadFromRegister(rx, 'DecStepSizeFullTableCase1'); + testCase.verifyEqual(rDecStepSizeFullTableCase1,rx.DecStepSizeFullTableCase1,'Unexpected value for DecStepSizeFullTableCase1 returned'); + rLargeLMTOverloadThresh = ReadFromRegister(rx, 'LargeLMTOverloadThresh'); + testCase.verifyEqual(rLargeLMTOverloadThresh,rx.LargeLMTOverloadThresh,'Unexpected value for LargeLMTOverloadThresh returned'); + rSmallLMTOverloadThresh = ReadFromRegister(rx, 'SmallLMTOverloadThresh'); + testCase.verifyEqual(rSmallLMTOverloadThresh,rx.SmallLMTOverloadThresh,'Unexpected value for SmallLMTOverloadThresh returned'); + rSettlingDelay = ReadFromRegister(rx, 'SettlingDelay'); + testCase.verifyEqual(rSettlingDelay,rx.SettlingDelay,'Unexpected value for SettlingDelay returned'); + rEnergyLostThresh = ReadFromRegister(rx, 'EnergyLostThresh'); + testCase.verifyEqual(rEnergyLostThresh,rx.EnergyLostThresh,'Unexpected value for EnergyLostThresh returned'); + rLowPowerThresh = ReadFromRegister(rx, 'LowPowerThresh'); + testCase.verifyEqual(rLowPowerThresh/2,rx.LowPowerThresh,'Unexpected value for LowPowerThresh returned'); + rIncrementGainStep = ReadFromRegister(rx, 'IncrementGainStep'); + testCase.verifyEqual(rIncrementGainStep,rx.IncrementGainStep,'Unexpected value for IncrementGainStep returned'); + rFAGCLockLevelGainIncreaseUpperLimit = ReadFromRegister(rx, 'FAGCLockLevelGainIncreaseUpperLimit'); + testCase.verifyEqual(rFAGCLockLevelGainIncreaseUpperLimit,rx.FAGCLockLevelGainIncreaseUpperLimit,'Unexpected value for FAGCLockLevelGainIncreaseUpperLimit returned'); + rFAGCLPThreshIncrementTime = ReadFromRegister(rx, 'FAGCLPThreshIncrementTime'); + testCase.verifyEqual(rFAGCLPThreshIncrementTime,rx.FAGCLPThreshIncrementTime,'Unexpected value for FAGCLPThreshIncrementTime returned'); + rDecPowMeasurementDuration = ReadFromRegister(rx, 'DecPowMeasurementDuration'); + testCase.verifyEqual(rDecPowMeasurementDuration,rx.DecPowMeasurementDuration,'Unexpected value for DecPowMeasurementDuration returned'); + + rx.release(); + end + function testAD9363RxWithTxDDS(testCase) % Test DDS output tx = adi.AD9363.Tx('uri',testCase.uri); diff --git a/test/AD9364Tests.m b/test/AD9364Tests.m index 640961a..41fadd1 100644 --- a/test/AD9364Tests.m +++ b/test/AD9364Tests.m @@ -1,7 +1,16 @@ -classdef AD9364Tests < matlab.unittest.TestCase +classdef AD9364Tests < HardwareTests properties uri = 'ip:192.168.2.1'; + author = 'ADI'; + end + + methods(TestClassSetup) + % Check hardware connected + function CheckForHardware(testCase) + Device = @()adi.AD9364.Rx; + testCase.CheckDevice('ip',Device,testCase.uri(4:end),false); + end end methods (Static) diff --git a/test/AD9371Tests.m b/test/AD9371Tests.m index 824ba9c..4575c04 100644 --- a/test/AD9371Tests.m +++ b/test/AD9371Tests.m @@ -1,8 +1,17 @@ -classdef AD9371Tests < matlab.unittest.TestCase +classdef AD9371Tests < HardwareTests properties - uri = 'ip:192.168.3.2'; + uri = 'ip:192.168.1.208'; SamplingRateRX = 122.88e6; + author = 'ADI'; + end + + methods(TestClassSetup) + % Check hardware connected + function CheckForHardware(testCase) + Device = @()adi.AD9371.Rx; + testCase.CheckDevice('ip',Device,testCase.uri(4:end),false); + end end methods (Static) @@ -26,6 +35,40 @@ function testAD9371Rx(testCase) testCase.verifyGreaterThan(sum(abs(double(out))),0); end + function testAD9371RxCustomProfile1(testCase) + % Test Rx custom profiles + rx = adi.AD9371.Rx('uri',testCase.uri); + rx.channelCount = 2; + rx.EnableCustomProfile = true; + rx.CustomProfileFileName = ... + 'profile_TxBW50_ORxBW50_RxBW50.txt'; + [out, valid] = rx(); + rxSampleRate = rx.getAttributeLongLong('voltage0',... + 'sampling_frequency',false); + rx.release(); + testCase.verifyTrue(valid); + testCase.verifyGreaterThan(sum(abs(double(out))),0); + testCase.verifyEqual(rxSampleRate,int64(61440000),... + 'Invalid sample rate after profile write'); + end + + function testAD9371RxCustomProfile2(testCase) + % Test Rx custom profiles + rx = adi.AD9371.Rx('uri',testCase.uri); + rx.channelCount = 2; + rx.EnableCustomProfile = true; + rx.CustomProfileFileName = ... + 'profile_TxBW100_ORxBW100_RxBW100.txt'; + [out, valid] = rx(); + rxSampleRate = rx.getAttributeLongLong('voltage0',... + 'sampling_frequency',false); + rx.release(); + testCase.verifyTrue(valid); + testCase.verifyGreaterThan(sum(abs(double(out))),0); + testCase.verifyEqual(rxSampleRate,int64(122880000),... + 'Invalid sample rate after profile write'); + end + function testAD9371RxWithTxDDS(testCase) % Test DDS output tx = adi.AD9371.Tx('uri',testCase.uri); diff --git a/test/ADRV9009Tests.m b/test/ADRV9009Tests.m index fc6c621..7329687 100644 --- a/test/ADRV9009Tests.m +++ b/test/ADRV9009Tests.m @@ -1,8 +1,17 @@ -classdef ADRV9009Tests < matlab.unittest.TestCase +classdef ADRV9009Tests < HardwareTests properties uri = 'ip:192.168.3.2'; SamplingRateRX = 245.76e6; + author = 'ADI'; + end + + methods(TestClassSetup) + % Check hardware connected + function CheckForHardware(testCase) + Device = @()adi.ADRV9009.Rx; + testCase.CheckDevice('ip',Device,testCase.uri(4:end),false); + end end methods (Static) diff --git a/test/BSPTestsBase.m b/test/BSPTestsBase.m index e64cc7f..6379f22 100644 --- a/test/BSPTestsBase.m +++ b/test/BSPTestsBase.m @@ -3,18 +3,44 @@ % Pull in board permutations configs = hdlcoder_board_customization_local; ignored_builds = {'AnalogDevices.adrv9361z7035.ccbox_lvds.modem.plugin_board'}; + SynthesizeDesign = {false}; + end + + properties + Count = 0; + TotalTests = 0; end methods(TestClassSetup) function disableWarnings(~) warning('off','hdlcommon:hdlcommon:InterfaceNotAssigned'); end + function testCount(testCase) + testCase.TotalTests = length(testCase.configs); + CountS = 0; + save('tc.mat','CountS'); + end end methods(TestClassTeardown) function enableWarnings(~) warning('on','hdlcommon:hdlcommon:InterfaceNotAssigned'); end + function collectLogs(~) + if ~exist([pwd,'../logs'],'dir') + mkdir('../logs','s'); + end + system('cp *.log ../logs'); + end + end + + methods(TestMethodSetup) + function loadTestCount(testCase) + l = load('tc.mat'); + CountS = l.CountS + 1; + testCase.Count = CountS; + save('tc.mat','CountS'); + end end methods(Static) @@ -76,7 +102,7 @@ function setVivadoPath(vivado) end methods(Test) - function testMain(testCase, configs) + function testMain(testCase, configs, SynthesizeDesign) % Filter out ignored configurations if ismember(configs,testCase.ignored_builds) assumeFail(testCase); @@ -91,18 +117,26 @@ function testMain(testCase, configs) % Set up vivado testCase.setVivadoPath(cfgb.vivado_version); % Build - disp(['Building: ',cfgb.Board.BoardName]); + disp(repmat('/',1,80)); + disp(['Building: ',cfgb.Board.BoardName,' | ',cfgb.mode,... + ' (',num2str(testCase.Count),' of ',num2str(testCase.TotalTests),')']); res = build_design(cfgb.Board,cfgb.ReferenceDesignName,... - cfgb.vivado_version,cfgb.mode,cfgb.Board.BoardName); + cfgb.vivado_version,cfgb.mode,cfgb.Board.BoardName,... + SynthesizeDesign); % Check if isfield(res,'message') || isa(res,'MException') disp(['Build error: ', cfgb.ReferenceDesignName]); - res - res.message + disp(res); + disp(res.message); + disp(res.stack); system("find hdl_prj/ -name 'workflow_task_CreateProject.log' | xargs -I '{}' cp {} ."); - %if exist('workflow_task_CreateProject.log','file') - % movefile('workflow_task_CreateProject.log',[cfgb.ReferenceDesignName,' ',cfgb.mode,'.log']); - %end + if exist('workflow_task_CreateProject.log','file') + movefile('workflow_task_CreateProject.log',[cfgb.ReferenceDesignName,'_CreateProject_',cfgb.mode,'.log']); + end + system("find hdl_prj/ -name 'workflow_task_BuildFPGABitstream.log' | xargs -I '{}' cp {} ."); + if exist('workflow_task_BuildFPGABitstream.log','file') + movefile('workflow_task_BuildFPGABitstream.log',[cfgb.ReferenceDesignName,'_BuildFPGABitstream_',cfgb.mode,'.log']); + end verifyEmpty(testCase,res,res.message); end end diff --git a/test/DAQ2Tests.m b/test/DAQ2Tests.m index 6de6eec..a0bd91b 100644 --- a/test/DAQ2Tests.m +++ b/test/DAQ2Tests.m @@ -1,7 +1,16 @@ -classdef DAQ2Tests < matlab.unittest.TestCase +classdef DAQ2Tests < HardwareTests properties uri = 'ip:192.168.3.2'; + author = 'ADI'; + end + + methods(TestClassSetup) + % Check hardware connected + function CheckForHardware(testCase) + Device = @()adi.ADRV9009.Rx; + testCase.CheckDevice('ip',Device,testCase.uri(4:end),false); + end end methods (Test) diff --git a/test/HardwareTests.m b/test/HardwareTests.m new file mode 100644 index 0000000..ee25e20 --- /dev/null +++ b/test/HardwareTests.m @@ -0,0 +1,40 @@ +classdef HardwareTests < matlab.unittest.TestCase + + properties (Abstract) + author + uri + end + + methods + % Check hardware connected + function CheckDevice(testCase,type,Dev,ip,istx) + try + switch type + case 'usb' + d = Dev(); + case 'ip' + if strcmp(testCase.author,'MathWorks') + d= Dev(); + d.IPAddress = ip; + else + d= Dev(); + d.uri = ['ip:',ip]; + end + otherwise + error('Unknown interface type'); + end + if istx + d(complex(randn(1024,1),randn(1024,1))); + else + d(); + end + + catch ME + disp(ME.message); + assumeFail(testCase,'Filtering test: No device found'); + end + end + + end + +end \ No newline at end of file diff --git a/test/build_design.m b/test/build_design.m index 784a7e6..e92225e 100644 --- a/test/build_design.m +++ b/test/build_design.m @@ -1,5 +1,5 @@ -function out = build_design(config,ReferenceDesignName,vivado_version,mode,board_name) +function out = build_design(config,ReferenceDesignName,vivado_version,mode,board_name,SynthesizeDesign) %% Load the Model @@ -38,7 +38,7 @@ hWC.RunTaskGenerateRTLCodeAndIPCore = true; hWC.RunTaskCreateProject = true; hWC.RunTaskGenerateSoftwareInterfaceModel = false; -hWC.RunTaskBuildFPGABitstream = false; % CHANGED +hWC.RunTaskBuildFPGABitstream = SynthesizeDesign; hWC.RunTaskProgramTargetDevice = false; % Set properties related to 'RunTaskGenerateRTLCodeAndIPCore' Task @@ -57,6 +57,7 @@ hWC.RunExternalBuild = false; %hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Default; %hWC.CustomBuildTclFile = ''; + hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Custom; hWC.CustomBuildTclFile = '../hdl_wa_bsp/vendor/AnalogDevices/vivado/projects/scripts/adi_build.tcl'; @@ -74,6 +75,9 @@ bdclose('all'); out = []; catch ME + if SynthesizeDesign && exist('hdl_prj/vivado_ip_prj/boot/BOOT.BIN','file') + ME = []; + end out = ME;%.identifier end diff --git a/test/perf/HardwareTests.m b/test/perf/HardwarePerformanceTests.m similarity index 99% rename from test/perf/HardwareTests.m rename to test/perf/HardwarePerformanceTests.m index f1f00eb..655816e 100644 --- a/test/perf/HardwareTests.m +++ b/test/perf/HardwarePerformanceTests.m @@ -1,4 +1,4 @@ -classdef HardwareTests < LTETests +classdef HardwarePerformanceTests < LTETests properties SamplingRate = 1e6; diff --git a/test/perf/hwTestRunner.m b/test/perf/hwTestRunner.m index 43a9e78..dd08fe9 100644 --- a/test/perf/hwTestRunner.m +++ b/test/perf/hwTestRunner.m @@ -7,7 +7,7 @@ 'IncludingPassingDiagnostics',true,'IncludingCommandWindowText',true)); runner.ArtifactsRootFolder = pwd; -suite = testsuite('HardwareTests'); +suite = testsuite('HardwarePerformanceTests'); if ~exist('logs', 'dir') mkdir('logs') diff --git a/test/profile_TxBW100_ORxBW100_RxBW100.txt b/test/profile_TxBW100_ORxBW100_RxBW100.txt new file mode 100644 index 0000000..92eaa93 --- /dev/null +++ b/test/profile_TxBW100_ORxBW100_RxBW100.txt @@ -0,0 +1,221 @@ + + + + + + + + + + + + + + + + + + + + -5 + -26 + 32 + 51 + -67 + -116 + 140 + 212 + -252 + -367 + 429 + 595 + -688 + -931 + 1072 + 1427 + -1650 + -2188 + 2612 + 3496 + -4802 + -7591 + 9656 + 32317 + 32317 + 9656 + -7591 + -4802 + 3496 + 2612 + -2188 + -1650 + 1427 + 1072 + -931 + -688 + 595 + 429 + -367 + -252 + 212 + 140 + -116 + -67 + 51 + 32 + -26 + -5 + + + + 534 + 386 + 201 + 98 + 1280 + 491 + 1591 + 279 + 1306 + 104 + 792 + 28 + 48 + 39 + 23 + 187 + + + + + + + + + + + + + + + 0 + -21 + 18 + 39 + -36 + -87 + 81 + 157 + -149 + -269 + 260 + 432 + -423 + -672 + 668 + 1025 + -1036 + -1570 + 1650 + 2547 + -2971 + -5686 + 4361 + 18361 + 18361 + 4361 + -5686 + -2971 + 2547 + 1650 + -1570 + -1036 + 1025 + 668 + -672 + -423 + 432 + 260 + -269 + -149 + 157 + 81 + -87 + -36 + 39 + 18 + -21 + 0 + + + + 534 + 386 + 201 + 98 + 1280 + 491 + 1591 + 279 + 1306 + 104 + 792 + 28 + 48 + 39 + 23 + 187 + + + + 599 + 357 + 201 + 98 + 1280 + 112 + 1505 + 53 + 1331 + 21 + 820 + 40 + 48 + 40 + 23 + 191 + + + + + + + + + + + + + + + + + 7 + -244 + 182 + -149 + -81 + 909 + -2806 + 20438 + -2806 + 909 + -81 + -149 + 182 + -244 + 7 + 0 + + + diff --git a/test/profile_TxBW50_ORxBW50_RxBW50.txt b/test/profile_TxBW50_ORxBW50_RxBW50.txt new file mode 100644 index 0000000..5c27b2e --- /dev/null +++ b/test/profile_TxBW50_ORxBW50_RxBW50.txt @@ -0,0 +1,285 @@ + + + + + + + + + + + + + + + + + + + + 0 + -1 + 2 + 3 + -5 + -7 + 11 + 15 + -23 + -29 + 43 + 54 + -75 + -92 + 125 + 150 + -198 + -235 + 302 + 355 + -447 + -524 + 646 + 759 + -920 + -1089 + 1302 + 1568 + -1864 + -2324 + 2763 + 3696 + -4513 + -7179 + 9583 + 31418 + 31418 + 9583 + -7179 + -4513 + 3696 + 2763 + -2324 + -1864 + 1568 + 1302 + -1089 + -920 + 759 + 646 + -524 + -447 + 355 + 302 + -235 + -198 + 150 + 125 + -92 + -75 + 54 + 43 + -29 + -23 + 15 + 11 + -7 + -5 + 3 + 2 + -1 + 0 + + + + 596 + 358 + 201 + 98 + 1280 + 134 + 1509 + 64 + 1329 + 25 + 818 + 39 + 48 + 40 + 23 + 190 + + + + + + + + + + + + + + + 0 + -1 + 1 + 2 + -2 + -6 + 6 + 12 + -13 + -24 + 25 + 43 + -45 + -73 + 77 + 118 + -124 + -183 + 193 + 274 + -289 + -402 + 423 + 579 + -607 + -826 + 866 + 1187 + -1244 + -1759 + 1842 + 2818 + -2970 + -5815 + 4337 + 18436 + 18436 + 4337 + -5815 + -2970 + 2818 + 1842 + -1759 + -1244 + 1187 + 866 + -826 + -607 + 579 + 423 + -402 + -289 + 274 + 193 + -183 + -124 + 118 + 77 + -73 + -45 + 43 + 25 + -24 + -13 + 12 + 6 + -6 + -2 + 2 + 1 + -1 + 0 + + + + 596 + 358 + 201 + 98 + 1280 + 134 + 1509 + 64 + 1329 + 25 + 818 + 39 + 48 + 40 + 23 + 190 + + + + 599 + 357 + 201 + 98 + 1280 + 112 + 1505 + 53 + 1331 + 21 + 820 + 40 + 48 + 40 + 23 + 191 + + + + + + + + + + + + + + + + + -118 + -122 + 242 + 240 + -429 + -499 + 730 + 900 + -1154 + -1615 + 1742 + 2957 + -2322 + -5354 + 3885 + 17211 + 17211 + 3885 + -5354 + -2322 + 2957 + 1742 + -1615 + -1154 + 900 + 730 + -499 + -429 + 240 + 242 + -122 + -118 + + + diff --git a/test/runHWTests.m b/test/runHWTests.m new file mode 100644 index 0000000..c3b4189 --- /dev/null +++ b/test/runHWTests.m @@ -0,0 +1,31 @@ +import matlab.unittest.TestRunner; +import matlab.unittest.TestSuite; +import matlab.unittest.plugins.TestReportPlugin; +import matlab.unittest.plugins.XMLPlugin + +try + suite = testsuite({'AD9361Tests','AD9363Tests','AD9364Tests'... + 'AD9371Tests','ADRV9009Tests','DAQ2Tests'}); + runner = TestRunner.withNoPlugins; + xmlFile = 'HWTestResults.xml'; + plugin = XMLPlugin.producingJUnitFormat(xmlFile); + + runner.addPlugin(plugin); + results = runner.run(suite); + + t = table(results); + disp(t); + disp(repmat('#',1,80)); + for test = results + if test.Failed + disp(test.Name); + end + end +catch e + disp(getReport(e,'extended')); + bdclose('all'); + exit(1); +end +save(['BSPTest_',datestr(now,'dd_mm_yyyy-HH:MM:SS'),'.mat'],'t'); +bdclose('all'); +exit(any([results.Failed])); diff --git a/test/runSynthTests.m b/test/runSynthTests.m new file mode 100644 index 0000000..8857002 --- /dev/null +++ b/test/runSynthTests.m @@ -0,0 +1,35 @@ +import matlab.unittest.TestRunner; +import matlab.unittest.TestSuite; +import matlab.unittest.plugins.TestReportPlugin; +import matlab.unittest.plugins.XMLPlugin +import matlab.unittest.parameters.Parameter + +SynthesizeDesign = {true}; + +param = Parameter.fromData('SynthesizeDesign',SynthesizeDesign); + +try + suite = TestSuite.fromClass(?BSPTests,'ExternalParameters',param); + runner = TestRunner.withNoPlugins; + xmlFile = 'BSPSynthTestResults.xml'; + plugin = XMLPlugin.producingJUnitFormat(xmlFile); + + runner.addPlugin(plugin); + results = runner.run(suite); + + t = table(results); + disp(t); + disp(repmat('#',1,80)); + for test = results + if test.Failed + disp(test.Name); + end + end +catch e + disp(getReport(e,'extended')); + bdclose('all'); + exit(1); +end +save(['BSPTest_',datestr(now,'dd_mm_yyyy-HH:MM:SS'),'.mat'],'t'); +bdclose('all'); +exit(any([results.Failed]));