From 3efe120db24c2c850da83ec04b8b883c73e39c3e Mon Sep 17 00:00:00 2001 From: Travis Collins Date: Mon, 20 May 2019 20:30:50 -0400 Subject: [PATCH] Add HDL targeting support for Pluto with fixes for AD9363 targeted devices. Signed-off-by: Travis Collins --- CI/projects/pluto/Makefile | 16 ++ CI/projects/pluto/config_prj.tcl | 79 ++++++ CI/projects/pluto/config_rxtx.tcl | 7 + CI/projects/pluto/config_rxtx_board.tcl | 24 ++ CI/projects/pluto/pluto_fpga.tcl | 26 ++ CI/projects/pluto/system_bd.tcl | 263 ++++++++++++++++++ CI/projects/pluto/system_constr.xdc | 204 ++++++++++++++ CI/projects/pluto/system_project.tcl | 17 ++ CI/projects/pluto/system_project_rxtx.tcl | 19 ++ CI/projects/pluto/system_top.v | 171 ++++++++++++ .../+AnalogDevices/+pluto/add_io.m | 134 +++++++++ .../hdlcoder_ref_design_customization.m | 23 ++ .../+AnalogDevices/+pluto/plugin_board.m | 28 ++ .../+AnalogDevices/+pluto/plugin_rd.m | 74 +++++ .../+AnalogDevices/+pluto/plugin_rd_rx.m | 8 + .../+AnalogDevices/+pluto/plugin_rd_rxtx.m | 8 + .../+AnalogDevices/+pluto/plugin_rd_tx.m | 8 + .../hdlcoder_board_customization.m | 1 + test/BSPTestsBase.m | 8 +- test/board_variants.m | 1 + test/setportmapping.m | 3 + 21 files changed, 1118 insertions(+), 4 deletions(-) create mode 100644 CI/projects/pluto/Makefile create mode 100644 CI/projects/pluto/config_prj.tcl create mode 100644 CI/projects/pluto/config_rxtx.tcl create mode 100644 CI/projects/pluto/config_rxtx_board.tcl create mode 100644 CI/projects/pluto/pluto_fpga.tcl create mode 100644 CI/projects/pluto/system_bd.tcl create mode 100644 CI/projects/pluto/system_constr.xdc create mode 100644 CI/projects/pluto/system_project.tcl create mode 100644 CI/projects/pluto/system_project_rxtx.tcl create mode 100644 CI/projects/pluto/system_top.v create mode 100644 hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/add_io.m create mode 100644 hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/hdlcoder_ref_design_customization.m create mode 100644 hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_board.m create mode 100644 hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd.m create mode 100644 hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_rx.m create mode 100644 hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_rxtx.m create mode 100644 hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_tx.m diff --git a/CI/projects/pluto/Makefile b/CI/projects/pluto/Makefile new file mode 100644 index 0000000..01b3b5e --- /dev/null +++ b/CI/projects/pluto/Makefile @@ -0,0 +1,16 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := pluto + +M_DEPS += ../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../library/axi_ad9361/axi_ad9361_delay.tcl + +LIB_DEPS += axi_ad9361 +LIB_DEPS += axi_dmac +LIB_DEPS += util_fir_dec +LIB_DEPS += util_fir_int + +include ../scripts/project-xilinx.mk diff --git a/CI/projects/pluto/config_prj.tcl b/CI/projects/pluto/config_prj.tcl new file mode 100644 index 0000000..3ec00c8 --- /dev/null +++ b/CI/projects/pluto/config_prj.tcl @@ -0,0 +1,79 @@ +global ref_design +global fpga_board +global dma + +# Add System Reset IP +startgroup +create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 +endgroup +connect_bd_net [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins sys_rstgen/peripheral_aresetn] +connect_bd_net [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins axi_ad9361/l_clk] + +# Add 1 extra AXI master ports to the interconnect +set_property -dict [list CONFIG.NUM_MI {5}] [get_bd_cells axi_cpu_interconnect] +connect_bd_net [get_bd_pins axi_cpu_interconnect/M04_ACLK] [get_bd_pins axi_ad9361/l_clk] +connect_bd_net [get_bd_pins axi_cpu_interconnect/M04_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] + +# Remove filters +delete_bd_objs [get_bd_cells fir_decimator] +delete_bd_objs [get_bd_cells fir_interpolator] + +# Configure DMA +if {$dma eq "Packetized"} { + set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32} CONFIG.DMA_DATA_WIDTH_DEST {256} CONFIG.SYNC_TRANSFER_START {false} CONFIG.DMA_AXI_PROTOCOL_DEST {0} CONFIG.DMA_TYPE_SRC {1} CONFIG.MAX_BYTES_PER_BURST {32768}] [get_bd_cells axi_ad9361_adc_dma] + connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_aclk] [get_bd_pins axi_ad9361/l_clk] +} + +# Insert pack cores +startgroup +create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_0 +endgroup +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16} CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_cpack_0] + +# Clocks and resets +connect_bd_net [get_bd_pins util_cpack_0/adc_clk] [get_bd_pins axi_ad9361/l_clk] +connect_bd_net [get_bd_pins util_cpack_0/adc_rst] [get_bd_pins proc_sys_reset_0/peripheral_reset] + +# Connect enables +connect_bd_net [get_bd_pins axi_ad9361/adc_enable_i0] [get_bd_pins util_cpack_0/adc_enable_0] +connect_bd_net [get_bd_pins axi_ad9361/adc_enable_q0] [get_bd_pins util_cpack_0/adc_enable_1] +# Connect valids together +connect_bd_net [get_bd_pins util_cpack_0/adc_valid_1] [get_bd_pins util_cpack_0/adc_valid_0] + + +############ DMA MODE +if {$dma eq "Packetized"} { + # Packetized DMA + connect_bd_net [get_bd_pins util_cpack_0/adc_data] [get_bd_pins axi_ad9361_adc_dma/s_axis_data] + connect_bd_net [get_bd_pins util_cpack_0/adc_valid] [get_bd_pins axi_ad9361_adc_dma/s_axis_valid] +} else { + # FIFO DMA + connect_bd_net [get_bd_pins util_cpack_0/adc_data] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din] + connect_bd_net [get_bd_pins util_cpack_0/adc_valid] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_en] +} + +###### UnPack +startgroup +create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_0 +endgroup +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16} CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_upack_0] +# Connect data +connect_bd_net [get_bd_pins util_upack_0/dac_data_0] [get_bd_pins axi_ad9361/dac_data_i0] +connect_bd_net [get_bd_pins util_upack_0/dac_data_1] [get_bd_pins axi_ad9361/dac_data_q0] +connect_bd_net [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout] [get_bd_pins util_upack_0/dac_data] +# Connect Clock +connect_bd_net [get_bd_pins util_upack_0/dac_clk] [get_bd_pins axi_ad9361/l_clk] +# Valid from pack to DMA +connect_bd_net [get_bd_pins util_upack_0/dac_valid] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en] + +# +#connect_bd_net [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid] [get_bd_pins util_upack_0/dac_valid_0] +#connect_bd_net [get_bd_pins util_upack_0/dac_valid_1] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid] + +# Input valids +connect_bd_net [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid] [get_bd_pins util_upack_0/dac_enable_0] +connect_bd_net [get_bd_pins util_upack_0/dac_valid_0] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid] +connect_bd_net [get_bd_pins util_upack_0/dac_valid_1] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid] +connect_bd_net [get_bd_pins util_upack_0/dac_enable_1] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid] + + diff --git a/CI/projects/pluto/config_rxtx.tcl b/CI/projects/pluto/config_rxtx.tcl new file mode 100644 index 0000000..58c2b0c --- /dev/null +++ b/CI/projects/pluto/config_rxtx.tcl @@ -0,0 +1,7 @@ +set ad_hdl_dir [pwd] +set proj_dir $ad_hdl_dir/projects/pluto + +source $proj_dir/config_prj.tcl +source $ad_hdl_dir/projects/pluto/config_rxtx_board.tcl + +regenerate_bd_layout \ No newline at end of file diff --git a/CI/projects/pluto/config_rxtx_board.tcl b/CI/projects/pluto/config_rxtx_board.tcl new file mode 100644 index 0000000..c467ba3 --- /dev/null +++ b/CI/projects/pluto/config_rxtx_board.tcl @@ -0,0 +1,24 @@ +global ref_design +global fpga_board + +# Configure DMA +#set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32} CONFIG.DMA_DATA_WIDTH_DEST {256} CONFIG.SYNC_TRANSFER_START {false} CONFIG.DMA_AXI_PROTOCOL_DEST {0} CONFIG.DMA_TYPE_SRC {1} CONFIG.MAX_BYTES_PER_BURST {32768}] [get_bd_cells axi_ad9361_adc_dma] +#connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_aclk] [get_bd_pins axi_ad9361/l_clk] +#connect_bd_net [get_bd_pins fir_decimator/m_axis_data_tdata] [get_bd_pins axi_ad9361_adc_dma/s_axis_data] +#connect_bd_net [get_bd_pins fir_decimator/m_axis_data_tvalid] [get_bd_pins axi_ad9361_adc_dma/s_axis_valid] + +if {$ref_design eq "Rx" || $ref_design eq "Rx & Tx"} { + # Disconnect the ADC PACK pins + delete_bd_objs [get_bd_nets axi_ad9361_adc_data_i0] + delete_bd_objs [get_bd_nets axi_ad9361_adc_data_q0] + # Disconnect valid + delete_bd_objs [get_bd_nets axi_ad9361_adc_valid_i0] +} + +if {$ref_design eq "Tx" || $ref_design eq "Rx & Tx"} { + # Disconnect the DAC UNPACK pins + delete_bd_objs [get_bd_nets fir_interpolator_channel_0] + delete_bd_objs [get_bd_nets fir_interpolator_channel_1] + # Disconnect valid + #delete_bd_objs [get_bd_nets axi_ad9361_dac_dma_fifo_rd_valid] +} \ No newline at end of file diff --git a/CI/projects/pluto/pluto_fpga.tcl b/CI/projects/pluto/pluto_fpga.tcl new file mode 100644 index 0000000..e08e31b --- /dev/null +++ b/CI/projects/pluto/pluto_fpga.tcl @@ -0,0 +1,26 @@ +# Build the project +update_compile_order -fileset sources_1 +reset_run impl_1 +reset_run synth_1 +launch_runs synth_1 +wait_on_run synth_1 +launch_runs impl_1 -to_step write_bitstream +wait_on_run impl_1 + +# Define local variables +set cdir [pwd] +set sdk_loc vivado_prj.sdk + +# Export the hdf +file delete -force $sdk_loc +file mkdir $sdk_loc +file copy -force vivado_prj.runs/impl_1/system_top.sysdef $sdk_loc/system_top.hdf + +# Close the Vivado project +close_project + +puts "------------------------------------" +puts "Embedded system build completed." +puts "You may close this shell." +puts "------------------------------------" +exit diff --git a/CI/projects/pluto/system_bd.tcl b/CI/projects/pluto/system_bd.tcl new file mode 100644 index 0000000..b85578a --- /dev/null +++ b/CI/projects/pluto/system_bd.tcl @@ -0,0 +1,263 @@ +# create board design +# default ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_2_o +create_bd_port -dir O spi0_csn_1_o +create_bd_port -dir O spi0_csn_0_o +create_bd_port -dir I spi0_csn_i +create_bd_port -dir I spi0_clk_i +create_bd_port -dir O spi0_clk_o +create_bd_port -dir I spi0_sdo_i +create_bd_port -dir O spi0_sdo_o +create_bd_port -dir I spi0_sdi_i + +create_bd_port -dir I -from 16 -to 0 gpio_i +create_bd_port -dir O -from 16 -to 0 gpio_o +create_bd_port -dir O -from 16 -to 0 gpio_t + +# interrupts + +create_bd_port -dir I -type intr ps_intr_00 +create_bd_port -dir I -type intr ps_intr_01 +create_bd_port -dir I -type intr ps_intr_02 +create_bd_port -dir I -type intr ps_intr_03 +create_bd_port -dir I -type intr ps_intr_04 +create_bd_port -dir I -type intr ps_intr_05 +create_bd_port -dir I -type intr ps_intr_06 +create_bd_port -dir I -type intr ps_intr_07 +create_bd_port -dir I -type intr ps_intr_08 +create_bd_port -dir I -type intr ps_intr_09 +create_bd_port -dir I -type intr ps_intr_10 +create_bd_port -dir I -type intr ps_intr_11 +create_bd_port -dir I -type intr ps_intr_12 +create_bd_port -dir I -type intr ps_intr_13 +create_bd_port -dir I -type intr ps_intr_14 +create_bd_port -dir I -type intr ps_intr_15 + +# instance: sys_ps7 + +ad_ip_instance processing_system7 sys_ps7 + +# ps7 settings + +ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} +ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} +ad_ip_parameter sys_ps7 CONFIG.PCW_PACKAGE_NAME clg225 +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 17 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13} +ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO +ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_IO MIO +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO {MIO 52} +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE + +# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks) + +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 0.048 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 0.050 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 0.241 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 0.240 + +ad_ip_instance xlconcat sys_concat_intc +ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16 + +ad_ip_instance proc_sys_reset sys_rstgen +ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +# system reset/clock definitions + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO + +# spi connections + +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 ps_intr_15 +ad_connect sys_concat_intc/In14 ps_intr_14 +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 ps_intr_11 +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 + +# iic + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main + +ad_ip_instance axi_iic axi_iic_main + +ad_connect iic_main axi_iic_main/iic +ad_cpu_interconnect 0x41600000 axi_iic_main +ad_cpu_interrupt ps-15 mb-15 axi_iic_main/iic2intc_irpt + +# ad9361 + +create_bd_port -dir I rx_clk_in +create_bd_port -dir I rx_frame_in +create_bd_port -dir I -from 11 -to 0 rx_data_in + +create_bd_port -dir O tx_clk_out +create_bd_port -dir O tx_frame_out +create_bd_port -dir O -from 11 -to 0 tx_data_out + +create_bd_port -dir O enable +create_bd_port -dir O txnrx +create_bd_port -dir I up_enable +create_bd_port -dir I up_txnrx + +# ad9361 core(s) + +ad_ip_instance axi_ad9361 axi_ad9361 +ad_ip_parameter axi_ad9361 CONFIG.ID 0 +ad_ip_parameter axi_ad9361 CONFIG.CMOS_OR_LVDS_N 1 +ad_ip_parameter axi_ad9361 CONFIG.MODE_1R1T 1 +ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 21 + +ad_ip_instance axi_dmac axi_ad9361_dac_dma +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 2 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 32 + +ad_ip_instance util_fir_int fir_interpolator +ad_ip_instance xlslice interp_slice + +ad_ip_instance axi_dmac axi_ad9361_adc_dma +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 32 + +ad_ip_instance util_fir_dec fir_decimator +ad_ip_instance xlslice decim_slice + +# connections + +ad_connect rx_clk_in axi_ad9361/rx_clk_in +ad_connect rx_frame_in axi_ad9361/rx_frame_in +ad_connect rx_data_in axi_ad9361/rx_data_in +ad_connect tx_clk_out axi_ad9361/tx_clk_out +ad_connect tx_frame_out axi_ad9361/tx_frame_out +ad_connect tx_data_out axi_ad9361/tx_data_out +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx + +ad_connect axi_ad9361/tdd_sync GND +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361/l_clk axi_ad9361/clk + +ad_connect axi_ad9361/l_clk fir_decimator/aclk +ad_connect axi_ad9361/adc_data_i0 fir_decimator/channel_0 +ad_connect axi_ad9361/adc_data_q0 fir_decimator/channel_1 +ad_connect axi_ad9361/adc_valid_i0 fir_decimator/s_axis_data_tvalid +ad_connect axi_ad9361_adc_dma/fifo_wr_din fir_decimator/m_axis_data_tdata +ad_connect axi_ad9361_adc_dma/fifo_wr_en fir_decimator/m_axis_data_tvalid +ad_connect axi_ad9361/up_adc_gpio_out decim_slice/Din +ad_connect fir_decimator/decimate decim_slice/Dout + +ad_connect axi_ad9361/l_clk fir_interpolator/aclk +ad_connect axi_ad9361_dac_dma/fifo_rd_dout fir_interpolator/s_axis_data_tdata +ad_connect axi_ad9361_dac_dma/fifo_rd_valid fir_interpolator/s_axis_data_tvalid +ad_connect axi_ad9361/dac_valid_i0 fir_interpolator/dac_read +ad_connect axi_ad9361_dac_dma/fifo_rd_en fir_interpolator/s_axis_data_tready +ad_connect axi_ad9361/dac_data_i0 fir_interpolator/channel_0 +ad_connect axi_ad9361/dac_data_q0 fir_interpolator/channel_1 +ad_connect axi_ad9361/up_dac_gpio_out interp_slice/Din +ad_connect fir_interpolator/interpolate interp_slice/Dout + +ad_connect axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk +ad_connect axi_ad9361_adc_dma/fifo_wr_overflow axi_ad9361/adc_dovf +ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/fifo_rd_clk +ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf +ad_connect axi_ad9361/dac_data_i1 GND +ad_connect axi_ad9361/dac_data_q1 GND + +# interconnects + +ad_cpu_interconnect 0x79020000 axi_ad9361 +ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma +ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq + + diff --git a/CI/projects/pluto/system_constr.xdc b/CI/projects/pluto/system_constr.xdc new file mode 100644 index 0000000..5659c6c --- /dev/null +++ b/CI/projects/pluto/system_constr.xdc @@ -0,0 +1,204 @@ +# constraints +# ad9361 (SWAP == 0x1) + +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18 } [get_ports rx_clk_in] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports rx_frame_in] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]] +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]] +set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]] +set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]] +set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]] +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]] +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]] +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]] +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]] +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]] + +set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS18} [get_ports tx_clk_out] +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18} [get_ports tx_frame_out] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]] +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]] +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]] +set_property -dict {PACKAGE_PIN P13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]] +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]] +set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] + +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] +set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] + +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] + +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] +set_property -dict {PACKAGE_PIN P9 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] + +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports enable] +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports txnrx] + +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda] + +set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports spi_clk] +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports spi_mosi] +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports spi_miso] + +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports gpio_bd] +set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS18} [get_ports clk_out] + +create_clock -name rx_clk -period 16.27 [get_ports rx_clk_in] + +# probably gone in 2016.4 + +create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"] +create_clock -name clk_fpga_1 -period 5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"] + +set_input_jitter clk_fpga_0 0.3 +set_input_jitter clk_fpga_1 0.15 + +set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_mio*] +set_property SLEW SLOW [get_ports *fixed_io_mio*] +set_property DRIVE 8 [get_ports *fixed_io_mio*] +set_property -dict {PACKAGE_PIN D8 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 0]] +set_property -dict {PACKAGE_PIN A5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 1]] +set_property -dict {PACKAGE_PIN A8 } [get_ports fixed_io_mio[ 2]] +set_property -dict {PACKAGE_PIN A7 } [get_ports fixed_io_mio[ 3]] +set_property -dict {PACKAGE_PIN C8 } [get_ports fixed_io_mio[ 4]] +set_property -dict {PACKAGE_PIN A9 } [get_ports fixed_io_mio[ 5]] +set_property -dict {PACKAGE_PIN A10 } [get_ports fixed_io_mio[ 6]] +set_property -dict {PACKAGE_PIN D9 } [get_ports fixed_io_mio[ 7]] +set_property -dict {PACKAGE_PIN B6 } [get_ports fixed_io_mio[ 8]] +set_property -dict {PACKAGE_PIN B5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 9]] +set_property -dict {PACKAGE_PIN D6 PULLTYPE PULLUP} [get_ports fixed_io_mio[10]] +set_property -dict {PACKAGE_PIN B10 PULLTYPE PULLUP} [get_ports fixed_io_mio[11]] +set_property -dict {PACKAGE_PIN B7 PULLTYPE PULLUP} [get_ports fixed_io_mio[12]] +set_property -dict {PACKAGE_PIN C6 PULLTYPE PULLUP} [get_ports fixed_io_mio[13]] +set_property -dict {PACKAGE_PIN B9 PULLTYPE PULLUP} [get_ports fixed_io_mio[14]] +set_property -dict {PACKAGE_PIN D10 PULLTYPE PULLUP} [get_ports fixed_io_mio[15]] +set_property -dict {PACKAGE_PIN A15 PULLTYPE PULLUP} [get_ports fixed_io_mio[16]] +set_property -dict {PACKAGE_PIN D11 PULLTYPE PULLUP} [get_ports fixed_io_mio[17]] +set_property -dict {PACKAGE_PIN B15 PULLTYPE PULLUP} [get_ports fixed_io_mio[18]] +set_property -dict {PACKAGE_PIN C12 PULLTYPE PULLUP} [get_ports fixed_io_mio[19]] +set_property -dict {PACKAGE_PIN E15 PULLTYPE PULLUP} [get_ports fixed_io_mio[20]] +set_property -dict {PACKAGE_PIN C11 PULLTYPE PULLUP} [get_ports fixed_io_mio[21]] +set_property -dict {PACKAGE_PIN D15 PULLTYPE PULLUP} [get_ports fixed_io_mio[22]] +set_property -dict {PACKAGE_PIN A14 PULLTYPE PULLUP} [get_ports fixed_io_mio[23]] +set_property -dict {PACKAGE_PIN B14 PULLTYPE PULLUP} [get_ports fixed_io_mio[24]] +set_property -dict {PACKAGE_PIN C14 PULLTYPE PULLUP} [get_ports fixed_io_mio[25]] +set_property -dict {PACKAGE_PIN A13 PULLTYPE PULLUP} [get_ports fixed_io_mio[26]] +set_property -dict {PACKAGE_PIN D14 PULLTYPE PULLUP} [get_ports fixed_io_mio[27]] +set_property -dict {PACKAGE_PIN B12 PULLTYPE PULLUP} [get_ports fixed_io_mio[28]] +set_property -dict {PACKAGE_PIN D13 PULLTYPE PULLUP} [get_ports fixed_io_mio[29]] +set_property -dict {PACKAGE_PIN A12 PULLTYPE PULLUP} [get_ports fixed_io_mio[30]] +set_property -dict {PACKAGE_PIN C13 PULLTYPE PULLUP} [get_ports fixed_io_mio[31]] + +set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_ps*] +set_property SLEW SLOW [get_ports *fixed_io_ps*] +set_property DRIVE 8 [get_ports *fixed_io_ps*] +set_property PACKAGE_PIN C7 [get_ports fixed_io_ps_clk] +set_property PACKAGE_PIN C9 [get_ports fixed_io_ps_porb] + +set_property IOSTANDARD SSTL15_T_DCI [get_ports *fixed_io_ddr_vr*] +set_property SLEW FAST [get_ports *fixed_io_ddr_vr*] +set_property PACKAGE_PIN H3 [get_ports fixed_io_ddr_vrp] +set_property PACKAGE_PIN J3 [get_ports fixed_io_ddr_vrn] + +set_property IOSTANDARD DIFF_SSTL15 [get_ports *ddr_ck*] +set_property SLEW FAST [get_ports *ddr_ck*] +set_property PACKAGE_PIN N3 [get_ports ddr_ck_p] +set_property PACKAGE_PIN N2 [get_ports ddr_ck_n] + +set_property IOSTANDARD SSTL15 [get_ports *ddr_addr*] +set_property SLEW SLOW [get_ports *ddr_addr*] +set_property PACKAGE_PIN P1 [get_ports ddr_addr[0]] +set_property PACKAGE_PIN N1 [get_ports ddr_addr[1]] +set_property PACKAGE_PIN M1 [get_ports ddr_addr[2]] +set_property PACKAGE_PIN M4 [get_ports ddr_addr[3]] +set_property PACKAGE_PIN P3 [get_ports ddr_addr[4]] +set_property PACKAGE_PIN P4 [get_ports ddr_addr[5]] +set_property PACKAGE_PIN P5 [get_ports ddr_addr[6]] +set_property PACKAGE_PIN M5 [get_ports ddr_addr[7]] +set_property PACKAGE_PIN P6 [get_ports ddr_addr[8]] +set_property PACKAGE_PIN N4 [get_ports ddr_addr[9]] +set_property PACKAGE_PIN J1 [get_ports ddr_addr[10]] +set_property PACKAGE_PIN L2 [get_ports ddr_addr[11]] +set_property PACKAGE_PIN M2 [get_ports ddr_addr[12]] +set_property PACKAGE_PIN K2 [get_ports ddr_addr[13]] +set_property PACKAGE_PIN K1 [get_ports ddr_addr[14]] + +set_property IOSTANDARD SSTL15 [get_ports *ddr_ba*] +set_property SLEW SLOW [get_ports *ddr_ba*] +set_property PACKAGE_PIN M6 [get_ports ddr_ba[0]] +set_property PACKAGE_PIN R1 [get_ports ddr_ba[1]] +set_property PACKAGE_PIN N6 [get_ports ddr_ba[2]] + +set_property IOSTANDARD SSTL15 [get_ports ddr_reset_n] +set_property SLEW FAST [get_ports ddr_reset_n] +set_property PACKAGE_PIN L4 [get_ports ddr_reset_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n] +set_property SLEW SLOW [get_ports ddr_cs_n] +set_property PACKAGE_PIN R2 [get_ports ddr_cs_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_ras_n] +set_property SLEW SLOW [get_ports ddr_ras_n] +set_property PACKAGE_PIN R6 [get_ports ddr_ras_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cas_n] +set_property SLEW SLOW [get_ports ddr_cas_n] +set_property PACKAGE_PIN R5 [get_ports ddr_cas_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_we_n] +set_property SLEW SLOW [get_ports ddr_we_n] +set_property PACKAGE_PIN R3 [get_ports ddr_we_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cke] +set_property SLEW SLOW [get_ports ddr_cke] +set_property PACKAGE_PIN L3 [get_ports ddr_cke] +set_property IOSTANDARD SSTL15 [get_ports ddr_odt] +set_property SLEW SLOW [get_ports ddr_odt] +set_property PACKAGE_PIN K3 [get_ports ddr_odt] + +set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dq[*]] +set_property SLEW FAST [get_ports *ddr_dq[*]] +set_property PACKAGE_PIN D4 [get_ports ddr_dq[0]] +set_property PACKAGE_PIN A2 [get_ports ddr_dq[1]] +set_property PACKAGE_PIN C4 [get_ports ddr_dq[2]] +set_property PACKAGE_PIN C1 [get_ports ddr_dq[3]] +set_property PACKAGE_PIN B4 [get_ports ddr_dq[4]] +set_property PACKAGE_PIN A4 [get_ports ddr_dq[5]] +set_property PACKAGE_PIN C3 [get_ports ddr_dq[6]] +set_property PACKAGE_PIN A3 [get_ports ddr_dq[7]] +set_property PACKAGE_PIN E1 [get_ports ddr_dq[8]] +set_property PACKAGE_PIN D1 [get_ports ddr_dq[9]] +set_property PACKAGE_PIN E2 [get_ports ddr_dq[10]] +set_property PACKAGE_PIN E3 [get_ports ddr_dq[11]] +set_property PACKAGE_PIN F3 [get_ports ddr_dq[12]] +set_property PACKAGE_PIN G1 [get_ports ddr_dq[13]] +set_property PACKAGE_PIN H1 [get_ports ddr_dq[14]] +set_property PACKAGE_PIN H2 [get_ports ddr_dq[15]] +set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dm[*]] +set_property SLEW FAST [get_ports *ddr_dm[*]] +set_property PACKAGE_PIN B1 [get_ports ddr_dm[0]] +set_property PACKAGE_PIN D3 [get_ports ddr_dm[1]] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports *ddr_dqs*] +set_property SLEW FAST [get_ports *ddr_dqs*] +set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]] +set_property PACKAGE_PIN B2 [get_ports ddr_dqs_n[0]] +set_property PACKAGE_PIN G2 [get_ports ddr_dqs_p[1]] +set_property PACKAGE_PIN F2 [get_ports ddr_dqs_n[1]] + +set_false_path -from [get_pins {i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/up_adc_gpio_out_int_reg[0]/C}] +set_false_path -from [get_pins {i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/up_dac_gpio_out_int_reg[0]/C}] + diff --git a/CI/projects/pluto/system_project.tcl b/CI/projects/pluto/system_project.tcl new file mode 100644 index 0000000..38531b1 --- /dev/null +++ b/CI/projects/pluto/system_project.tcl @@ -0,0 +1,17 @@ + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z010clg225-1" +adi_project_xilinx pluto + +adi_project_files pluto [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] + +set_property is_enabled false [get_files *system_sys_ps7_0.xdc] +adi_project_run pluto +source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl + diff --git a/CI/projects/pluto/system_project_rxtx.tcl b/CI/projects/pluto/system_project_rxtx.tcl new file mode 100644 index 0000000..b81e629 --- /dev/null +++ b/CI/projects/pluto/system_project_rxtx.tcl @@ -0,0 +1,19 @@ +set ad_hdl_dir [pwd] +set ad_phdl_dir [pwd] +set proj_dir $ad_hdl_dir/projects/pluto + +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_xilinx pluto $proj_dir config_rxtx.tcl + +adi_project_files pluto [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" ] + +adi_project_run pluto +#source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl + +# Copy the boot file to the root directory +#file copy -force $proj_dir/boot $ad_hdl_dir/boot \ No newline at end of file diff --git a/CI/projects/pluto/system_top.v b/CI/projects/pluto/system_top.v new file mode 100644 index 0000000..acb8470 --- /dev/null +++ b/CI/projects/pluto/system_top.v @@ -0,0 +1,171 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 1:0] ddr_dm, + inout [15:0] ddr_dq, + inout [ 1:0] ddr_dqs_n, + inout [ 1:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [31:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + inout gpio_bd, + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + + output enable, + output txnrx, + input clk_out, + + inout gpio_resetb, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [16:0] gpio_i; + wire [16:0] gpio_o; + wire [16:0] gpio_t; + + assign gpio_i[16:15] = gpio_o[16:15]; + // instantiations + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf ( + .dio_t (gpio_t[14:0]), + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_p ({ gpio_bd, // 14:14 + gpio_resetb, // 13:13 + gpio_en_agc, // 12:12 + gpio_ctl, // 11: 8 + gpio_status})); // 7: 0 + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_14 (1'b0), + .rx_clk_in (rx_clk_in), + .rx_data_in (rx_data_in), + .rx_frame_in (rx_frame_in), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .tx_clk_out (tx_clk_out), + .tx_data_out (tx_data_out), + .tx_frame_out (tx_frame_out), + .txnrx (txnrx), + .up_enable (gpio_o[15]), + .up_txnrx (gpio_o[16])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/add_io.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/add_io.m new file mode 100644 index 0000000..916b548 --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/add_io.m @@ -0,0 +1,134 @@ +function add_io(hRD,type) + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% add AXI4 and AXI4-Lite slave interfaces +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% add AXI4 and AXI4-Lite slave interfaces +hRD.addAXI4SlaveInterface( ... + 'InterfaceConnection', 'axi_cpu_interconnect/M04_AXI', ... + 'BaseAddress', '0x43C00000', ... + 'MasterAddressSpace', 'sys_ps7/Data'); + +% DMA Ready signal +hRD.addInternalIOInterface( ... + 'InterfaceID', 'DMA Ready', ... + 'InterfaceType', 'IN', ... + 'PortName', 'dma_rdy', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'axi_ad9361_adc_dma/s_axis_ready', ... + 'IsRequired', false); + +% % DMA Ready signal +% hRD.addInternalIOInterface( ... +% 'InterfaceID', 'DMA Ready', ... +% 'InterfaceType', 'IN', ... +% 'PortName', 'dma_rdy', ... +% 'PortWidth', 1, ... +% 'InterfaceConnection', 'util_cpack_0/adc_valid', ... +% 'IsRequired', false); + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Rx Reference design interfaces +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +if contains(lower(type),'rx') + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data Valid OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_valid', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'util_cpack_0/adc_valid_0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_cpack_0/adc_data_0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_1', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_cpack_0/adc_data_1', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Data I0', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_dma0_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361/adc_data_i0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Data Q0', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_dma1_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361/adc_data_q0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Valid', ... + 'InterfaceType', 'IN', ... + 'PortName', 'dut_valid_in', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'axi_ad9361/adc_valid_i0', ... + 'IsRequired', false); + +end +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Tx Reference design interfaces +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +if contains(lower(type),'tx') + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 DAC Data I0', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9361_dac_data_i0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361/dac_data_i0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 DAC Data Q0', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9361_dac_data_q0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361/dac_data_q0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_00', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_upack_0/dac_data_0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_01', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_upack_0/dac_data_1', ... + 'IsRequired', false); + +% hRD.addInternalIOInterface( ... +% 'InterfaceID', 'IP Load Tx Data OUT', ... +% 'InterfaceType', 'OUT', ... +% 'PortName', 'util_dac_unpack_dac_valid_00', ... +% 'PortWidth', 1, ... +% 'InterfaceConnection', 'util_ad9361_dac_upack/dac_valid_0', ... +% 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Valid Tx Data IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_upack_valid_00', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'util_upack_0/dac_valid_out_0', ... + 'IsRequired', false); +end \ No newline at end of file diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/hdlcoder_ref_design_customization.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/hdlcoder_ref_design_customization.m new file mode 100644 index 0000000..377a238 --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/hdlcoder_ref_design_customization.m @@ -0,0 +1,23 @@ +function [rd, boardName] = hdlcoder_ref_design_customization +% Reference design plugin registration file +% 1. The registration file with this name inside of a board plugin folder +% will be picked up +% 2. Any registration file with this name on MATLAB path will also be picked up +% 3. The registration file returns a cell array pointing to the location of +% the reference design plugins +% 4. The registration file also returns its associated board name +% 5. Reference design plugin must be a package folder accessible from +% MATLAB path, and contains a reference design definition file + +% Copyright 2013-2014 The MathWorks, Inc. + +rd = {... + 'AnalogDevices.pluto.plugin_rd_rx', ... + 'AnalogDevices.pluto.plugin_rd_tx', ... + 'AnalogDevices.pluto.plugin_rd_rxtx', ... + }; + +boardName = 'AnalogDevices ADALM-PLUTO'; + +end + diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_board.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_board.m new file mode 100644 index 0000000..834af58 --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_board.m @@ -0,0 +1,28 @@ +function hB = plugin_board() +% Use Plugin API to create board plugin object + +% Copyright 2015 The MathWorks, Inc. + +hB = hdlcoder.Board; + +% Target Board Information +hB.BoardName = 'AnalogDevices ADALM-PLUTO'; + +% FPGA Device +hB.FPGAVendor = 'Xilinx'; +hB.FPGAFamily = 'Zynq'; + +% Determine the device based on the board +hB.FPGADevice = sprintf('xc7%s', 'z010'); +hB.FPGAPackage = 'clg225'; +hB.FPGASpeed = '-1'; + +% Tool Info +hB.SupportedTool = {'Xilinx Vivado'}; + +% FPGA JTAG chain position +hB.JTAGChainPosition = 2; + +%% Add interfaces +% Standard "External Port" interface + diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd.m new file mode 100644 index 0000000..b80a8fb --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd.m @@ -0,0 +1,74 @@ +function hRD = plugin_rd(design) +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Construct reference design object +hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado'); + +% Create the reference design for the SOM-only +% This is the base reference design that other RDs can build upon +hRD.ReferenceDesignName = sprintf('AnalogDevices ADALM-PLUTO (%s)', upper(design)); + +% Determine the board name based on the design +hRD.BoardName = 'AnalogDevices ADALM-PLUTO'; + +% Tool information +hRD.SupportedToolVersion = {'2017.4'}; + +% Get the root directory +rootDir = fileparts(strtok(mfilename('fullpath'), '+')); + +% Design files are shared +hRD.SharedRD = true; +hRD.SharedRDFolder = fullfile(rootDir, 'vivado'); + +%% Add custom design files +% add custom Vivado design +hRD.addCustomVivadoDesign( ... + 'CustomBlockDesignTcl', fullfile('projects', 'pluto', 'system_project_rxtx.tcl'), ... + 'CustomTopLevelHDL', fullfile('projects', 'pluto', 'system_top.v')); + +hRD.BlockDesignName = 'system'; + +% custom constraint files +hRD.CustomConstraints = {... + fullfile('projects', 'pluto', 'system_constr.xdc'), ... + ...%fullfile('projects', 'common', lower(board), sprintf('%s_system_constr.xdc', lower(board))), ... + }; + +% custom source files +hRD.CustomFiles = {... + fullfile('projects')..., + fullfile('library')..., + }; + +hRD.addParameter( ... + 'ParameterID', 'ref_design', ... + 'DisplayName', 'Reference Type', ... + 'DefaultValue', design); + +board = 'PLUTO'; +hRD.addParameter( ... + 'ParameterID', 'fpga_board', ... + 'DisplayName', 'FPGA Boad', ... + 'DefaultValue', upper(board)); + +hRD.addParameter( ... + 'ParameterID', 'dma', ... + 'DisplayName', 'DMA Mode', ... + 'DefaultValue', 'Stream',... + 'ParameterType',hdlcoder.ParameterType.Dropdown,... + 'Choice',{'Packetized', 'Stream'} ); + +%% Add interfaces +% add clock interface +% axi_ad9361/l_clk +% hRD.addClockInterface( ... +% 'ClockConnection', 'sys_ps7/FCLK_CLK0', ... +% 'ResetConnection', 'sys_rstgen/peripheral_aresetn'); +hRD.addClockInterface( ... + 'ClockConnection', 'axi_ad9361/l_clk', ... + 'ResetConnection', 'proc_sys_reset_0/peripheral_aresetn'); % Added IP core +% 'ResetConnection', 'sys_rstgen/peripheral_aresetn'); + diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_rx.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_rx.m new file mode 100644 index 0000000..b613803 --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_rx.m @@ -0,0 +1,8 @@ +function hRD = plugin_rd_rx +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Call the common reference design definition function +hRD = AnalogDevices.pluto.plugin_rd('Rx'); +AnalogDevices.pluto.add_io(hRD,'Rx'); \ No newline at end of file diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_rxtx.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_rxtx.m new file mode 100644 index 0000000..29a2700 --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_rxtx.m @@ -0,0 +1,8 @@ +function hRD = plugin_rd_rxtx +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Call the common reference design definition function +hRD = AnalogDevices.pluto.plugin_rd('Rx & Tx'); +AnalogDevices.pluto.add_io(hRD,'Rx & Tx'); \ No newline at end of file diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_tx.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_tx.m new file mode 100644 index 0000000..e898b64 --- /dev/null +++ b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+pluto/plugin_rd_tx.m @@ -0,0 +1,8 @@ +function hRD = plugin_rd_tx +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Call the common reference design definition function +hRD = AnalogDevices.pluto.plugin_rd('Tx'); +AnalogDevices.pluto.add_io(hRD,'Tx'); \ No newline at end of file diff --git a/hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m b/hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m index a6cc65d..30e3699 100644 --- a/hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m +++ b/hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m @@ -9,6 +9,7 @@ % Copyright 2012-2013 The MathWorks, Inc. r = { ... + 'AnalogDevices.pluto.plugin_board', ... 'AnalogDevices.fmcomms2.zed.plugin_board', ... 'AnalogDevices.fmcomms2.zc702.plugin_board', ... 'AnalogDevices.fmcomms2.zc706.plugin_board', ... diff --git a/test/BSPTestsBase.m b/test/BSPTestsBase.m index b47cbaf..8761928 100644 --- a/test/BSPTestsBase.m +++ b/test/BSPTestsBase.m @@ -51,7 +51,7 @@ function loadTestCount(testCase) methods - function CollectLogs(testCase,cfgb) + function CollectLogs(testCase,~) disp('Log collector called'); system(["find '",testCase.Folder,"' -name 'workflow_task_VivadoIPPackager.log' | xargs -I '{}' cp {} ."]); if exist('workflow_task_VivadoIPPackager.log','file') @@ -70,7 +70,7 @@ function CollectLogs(testCase,cfgb) end end - function cfg = ADRV9361_Variants(testCase,s) + function cfg = ADRV9361_Variants(~,s) variants = {... 'ccbob_cmos','ccbob_lvds',... @@ -111,9 +111,9 @@ function CollectLogs(testCase,cfgb) end - function cfg = extractConfigs(testCase,config) + function cfg = extractConfigs(~,config) s = strsplit(config,'.'); - modes = strsplit(s{4},'_'); + modes = strsplit(s{end},'_'); mode = modes{end}; h1 = str2func(config);h1 = h1(); diff --git a/test/board_variants.m b/test/board_variants.m index 0f91382..0d969f7 100644 --- a/test/board_variants.m +++ b/test/board_variants.m @@ -9,6 +9,7 @@ % Copyright 2012-2013 The MathWorks, Inc. r = { ... + 'AnalogDevices.pluto.plugin_rd_rxtx', ... ... 'AnalogDevices.fmcomms2.zed.plugin_rd_rx', ... 'AnalogDevices.fmcomms2.zed.plugin_rd_rxtx', ... diff --git a/test/setportmapping.m b/test/setportmapping.m index 03df304..6e933f6 100644 --- a/test/setportmapping.m +++ b/test/setportmapping.m @@ -11,6 +11,9 @@ if contains(lower(ReferenceDesignName),'936') dev = 'AD9361'; +elseif contains(lower(ReferenceDesignName),'pluto') + dev = 'AD9361'; + numChannels = 2; elseif contains(lower(ReferenceDesignName),'fmcomms') dev = 'AD9361'; if contains(lower(ReferenceDesignName),'fmcomms5')