diff --git a/+adi/+common/DebugAttribute.m b/+adi/+common/DebugAttribute.m index fb6e32c..8b306b0 100644 --- a/+adi/+common/DebugAttribute.m +++ b/+adi/+common/DebugAttribute.m @@ -1,6 +1,6 @@ classdef (Abstract) DebugAttribute < matlabshared.libiio.base - methods (Hidden, Access = protected) + methods (Hidden) function setDebugAttributeLongLong(obj,attr,value) phydev = getDev(obj, obj.phyDevName); if (nargin == 1) @@ -26,13 +26,13 @@ function setDebugAttributeBool(obj,attr,value) end status = iio_device_debug_attr_write_bool(obj,phydev,attr,value); cstatus(obj,status,['Attribute write failed for : ' attr]); - % Check - [status, rValue] = iio_device_debug_attr_read_bool(obj,phydev,attr); - cstatus(obj,status,['Error reading attribute: ' attr]); - if value ~= rValue - status = -1; - cstatus(obj,status,['Attribute ' attr ' return value ' num2str(rValue) ', expected ' num2str(value)]); - end + % Check (Not implemented yet) +% [status, rValue] = iio_device_debug_attr_read_bool(obj,phydev,attr); +% cstatus(obj,status,['Error reading attribute: ' attr]); +% if value ~= rValue +% status = -1; +% cstatus(obj,status,['Attribute ' attr ' return value ' num2str(rValue) ', expected ' num2str(value)]); +% end end end end \ No newline at end of file diff --git a/+adi/+common/Rx.m b/+adi/+common/Rx.m index 7d734e9..c61a69d 100644 --- a/+adi/+common/Rx.m +++ b/+adi/+common/Rx.m @@ -7,15 +7,20 @@ function varargout = stepImpl(obj) % Get the data - [dataRAW, valid] = getData(obj); - index = 1; c = obj.channelCount/2; - varargout = cell(c+1,1); - for k = 1:c - varargout{k} = complex(dataRAW(index,:),dataRAW(index+1,:)).'; - index = index+2; + if c > 0 + [dataRAW, valid] = getData(obj); + index = 1; + varargout = cell(c+1,1); + for k = 1:c + varargout{k} = complex(dataRAW(index,:),dataRAW(index+1,:)).'; + index = index+2; + end + varargout{end} = valid; + else + varargout = cell(1,1); + varargout{1} = true; end - varargout{end} = valid; end end diff --git a/+adi/+common/RxTx.m b/+adi/+common/RxTx.m index 6c04883..e2da1d5 100644 --- a/+adi/+common/RxTx.m +++ b/+adi/+common/RxTx.m @@ -106,14 +106,18 @@ function releaseChanBuffers(obj) obj.enabledChannels = true; % Create the buffers - status = createBuf(obj); - if status - for k=1:obj.channelCount - disableChannel(obj, obj.channel_names{k}, obj.isOutput); + if obj.channelCount>0 + status = createBuf(obj); + if status + for k=1:obj.channelCount + disableChannel(obj, obj.channel_names{k}, obj.isOutput); + end + releaseChanBuffers(obj); + cerrmsg(obj,status,['Failed to create buffer for: ' obj.devName]); + return end - releaseChanBuffers(obj); - cerrmsg(obj,status,['Failed to create buffer for: ' obj.devName]); - return + else + status = 0; end end diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index e3a0cdb..750354f 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -30,7 +30,7 @@ build:master: - matlab stage: build script: - - export HDLBRANCH=master + - export HDLBRANCH=hdl_2018_r2 - export MLRELEASE=R2018b - ./CI/scripts/dockermake build - export HDLBRANCH= @@ -82,9 +82,27 @@ test_installer:2018_R1_Installer: reports: junit: test/BSPTestResults.xml -# Test weekly fully sythesized design -test:Synthesize: - when: manual +# Test HWA no install +test:2018_R1: + tags: + - vivado + - matlab + stage: test + dependencies: + - build:2018_R1 + script: + - ./CI/scripts/dockermake test + - ./CI/scripts/dockermake zip + artifacts: + when: always + paths: + - zip/ + - test/logs/ + reports: + junit: test/BSPTestResults.xml + +# Test targeting demos (no hardware) +test:targeting_demos: tags: - matlab - vivado @@ -92,7 +110,7 @@ test:Synthesize: dependencies: - build:2018_R1 script: - - ./CI/scripts/dockermake test_synth + - ./CI/scripts/dockermake test_targeting_demos artifacts: when: always name: "$CI_COMMIT_REF_NAME" diff --git a/CI/projects/adrv9361z7035/common/config_rx.tcl b/CI/projects/adrv9361z7035/common/config_rx.tcl index 949226a..837220a 100644 --- a/CI/projects/adrv9361z7035/common/config_rx.tcl +++ b/CI/projects/adrv9361z7035/common/config_rx.tcl @@ -13,3 +13,14 @@ disconnect_bd_net /util_ad9361_adc_fifo_dout_data_3 [get_bd_pins util_ad9361_adc connect_bd_net [get_bd_pins util_ad9361_adc_pack/adc_valid_0] [get_bd_pins util_ad9361_adc_pack/adc_valid_1] connect_bd_net [get_bd_pins util_ad9361_adc_pack/adc_valid_0] [get_bd_pins util_ad9361_adc_pack/adc_valid_2] connect_bd_net [get_bd_pins util_ad9361_adc_pack/adc_valid_0] [get_bd_pins util_ad9361_adc_pack/adc_valid_3] + +global dma_config +# Configure DMA +if {[info exists dma_config]} { + if {$dma_config eq "Packetized"} { + set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64} CONFIG.DMA_DATA_WIDTH_DEST {256} CONFIG.SYNC_TRANSFER_START {false} CONFIG.DMA_AXI_PROTOCOL_DEST {0} CONFIG.DMA_TYPE_SRC {1} CONFIG.MAX_BYTES_PER_BURST {32768}] [get_bd_cells axi_ad9361_adc_dma] + connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_aclk] [get_bd_pins util_ad9361_divclk/clk_out] + connect_bd_net [get_bd_pins util_ad9361_adc_pack/adc_data] [get_bd_pins axi_ad9361_adc_dma/s_axis_data] + connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_valid] [get_bd_pins util_ad9361_adc_pack/adc_valid] + } +} diff --git a/CI/scripts/Docker b/CI/scripts/Docker index 0183c15..6c95c6f 100644 --- a/CI/scripts/Docker +++ b/CI/scripts/Docker @@ -1,8 +1,10 @@ FROM ubuntu:16.04 MAINTAINER Travis Collins -RUN apt update +RUN DEBIAN_FRONTEND=noninteractive apt update RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libpng-dev libfreetype6-dev libblas-dev liblapack-dev gfortran build-essential xorg RUN DEBIAN_FRONTEND=noninteractive apt-get install -y openjdk-8-jre openjdk-8-jdk libgtk2.0-0 libxss1 libxt6 zip unzip curl wget tar git xvfb +RUN DEBIAN_FRONTEND=noninteractive apt-get install -y fakeroot libncurses5-dev libssl-dev ccache dfu-util u-boot-tools device-tree-compiler +RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libssl-dev mtools bc python cpio zip unzip rsync file wget RUN DEBIAN_FRONTEND=noninteractive dpkg --add-architecture i386 RUN DEBIAN_FRONTEND=noninteractive apt-get install -y lib32stdc++6 diff --git a/CI/scripts/Makefile b/CI/scripts/Makefile index cdd0558..601dd25 100644 --- a/CI/scripts/Makefile +++ b/CI/scripts/Makefile @@ -97,6 +97,9 @@ test_modem: test_synth: bash synth_designs.sh +test_targeting_demos: + bash targeting_designs.sh + gen_tlbx: ${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "genTlbx;exit();" diff --git a/CI/scripts/targeting_designs.sh b/CI/scripts/targeting_designs.sh new file mode 100644 index 0000000..0225575 --- /dev/null +++ b/CI/scripts/targeting_designs.sh @@ -0,0 +1,19 @@ +#!/bin/bash + +MLFLAGS="-nodisplay -nodesktop -nosplash" + +if [ -z "$MLRELEASE" ] +then + MLRELEASE=R2018b +fi + +MLPATH=/usr/local/MATLAB + +cd ../.. +source /opt/Xilinx/Vivado/2017.4/settings64.sh +Xvfb :77 & +export DISPLAY=:77 +export SWT_GTK3=0 +source /opt/Xilinx/Vivado/2017.4/settings64.sh +$MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "addpath(genpath('test'));addpath(genpath('deps'));runDemoTests;" +kill -9 `pidof Xvfb` diff --git a/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/add_rx_tx_io.m b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/add_rx_tx_io.m new file mode 100644 index 0000000..5e806cf --- /dev/null +++ b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/add_rx_tx_io.m @@ -0,0 +1,201 @@ +function add_rx_tx_io(hRD) + +% add AXI4 and AXI4-Lite slave interfaces +hRD.addAXI4SlaveInterface( ... + 'InterfaceConnection', 'axi_cpu_interconnect/M11_AXI', ... + 'BaseAddress', '0x43C00000', ... + 'MasterAddressSpace', 'sys_ps7/Data'); + +% % AGC control input for transceiver +% hRD.addInternalIOInterface( ... +% 'InterfaceID', 'Enable AGC', ... +% 'InterfaceType', 'OUT', ... +% 'PortName', 'en_agc', ... +% 'PortWidth', 1, ... +% 'InterfaceConnection', 'gpio_en_agc', ... +% 'IsRequired', false); + +% GPIO status output for transceiver +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CTRL_STATUS', ... + 'InterfaceType', 'IN', ... + 'PortName', 'gpio_status', ... + 'PortWidth', 8, ... + 'InterfaceConnection', 'gpio_status', ... + 'IsRequired', false); + +% GPIO Control input for transceiver +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 CTRL IN', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'gpio_ctl', ... + 'PortWidth', 4, ... + 'InterfaceConnection', 'gpio_ctl', ... + 'IsRequired', false); + +% DMA Ready signal +hRD.addInternalIOInterface( ... + 'InterfaceID', 'DMA Ready', ... + 'InterfaceType', 'IN', ... + 'PortName', 'dma_rdy', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'axi_ad9361_adc_dma/s_axis_ready', ... + 'IsRequired', false); + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Rx Reference design interfaces +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data Valid OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_valid', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/adc_valid_0', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_0', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_1', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_1', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 2 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_2', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_2', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 3 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_3', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_3', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Data I0', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_0_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_0', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Data Q0', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_1_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_1', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Data I1', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_2_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_2', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Data Q1', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_3_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_3', ... + 'IsRequired', false); + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Tx Reference design interfaces +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 DAC Data I0', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9361_dac_data_i0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_0', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 DAC Data Q0', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9361_dac_data_q0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_1', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 DAC Data I1', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9361_dac_data_i1', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_2', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 DAC Data Q1', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9361_dac_data_q1', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_3', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_00', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_0', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_01', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_1', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 2 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_02', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_2', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 3 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_03', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_3', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Load Tx Data OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'util_dac_unpack_dac_valid_00', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/dac_valid_0', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Valid Tx Data IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_upack_valid_00', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/upack_valid_0', ... + 'IsRequired', false); \ No newline at end of file diff --git a/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/hdlcoder_ref_design_customization.m b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/hdlcoder_ref_design_customization.m new file mode 100644 index 0000000..74050c7 --- /dev/null +++ b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/hdlcoder_ref_design_customization.m @@ -0,0 +1,20 @@ +function [rd, boardName] = hdlcoder_ref_design_customization +% Reference design plugin registration file +% 1. The registration file with this name inside of a board plugin folder +% will be picked up +% 2. Any registration file with this name on MATLAB path will also be picked up +% 3. The registration file returns a cell array pointing to the location of +% the reference design plugins +% 4. The registration file also returns its associated board name +% 5. Reference design plugin must be a package folder accessible from +% MATLAB path, and contains a reference design definition file + +% Copyright 2013-2014 The MathWorks, Inc. + +rd = {'AnalogDevicesDemo.adrv9361z7035.ccfmc_lvds_hop.rxtx.plugin_rd', ... + }; + +boardName = 'AnalogDevicesDemo adrv9361z7035 fmc lvds hop (Rx & Tx)'; + +end + diff --git a/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/plugin_board.m b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/plugin_board.m new file mode 100644 index 0000000..42946c0 --- /dev/null +++ b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/plugin_board.m @@ -0,0 +1,9 @@ +function hP = plugin_board() +% Zynq Platform PCore +% Use Plugin API to create board plugin object + +% Copyright 2015 The MathWorks, Inc. + +% Call the common board definition function +hP = AnalogDevices.adrv9361z7035.common.plugin_board('fmc lvds hop', 'Rx & Tx'); + diff --git a/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/plugin_rd.m b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/plugin_rd.m new file mode 100644 index 0000000..c276544 --- /dev/null +++ b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/plugin_rd.m @@ -0,0 +1,8 @@ +function hRD = plugin_rd +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Call the common reference design definition function +hRD = AnalogDevicesDemo.adrv9361z7035.common.plugin_rd('ccfmc_lvds_hop', 'Rx & Tx'); +AnalogDevicesDemo.adrv9361z7035.ccfmc_lvds_hop.rxtx.add_rx_tx_io(hRD); \ No newline at end of file diff --git a/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/add_io.m b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/add_io.m new file mode 100644 index 0000000..d7f30ae --- /dev/null +++ b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/add_io.m @@ -0,0 +1,189 @@ +function add_io(hRD,design,board) + +% add AXI4 and AXI4-Lite slave interfaces +switch lower(board) + case 'ccfmc_lvds' + hRD.addAXI4SlaveInterface( ... + 'InterfaceConnection', 'axi_cpu_interconnect/M11_AXI', ... + 'BaseAddress', '0x43C00000', ... + 'MasterAddressSpace', 'sys_ps7/Data'); + case 'ccbob_cmos' + hRD.addAXI4SlaveInterface( ... + 'InterfaceConnection', 'axi_cpu_interconnect/M06_AXI', ... + 'BaseAddress', '0x43C00000', ... + 'MasterAddressSpace', 'sys_ps7/Data'); + case 'ccbob_lvds' + hRD.addAXI4SlaveInterface( ... + 'InterfaceConnection', 'axi_cpu_interconnect/M06_AXI', ... + 'BaseAddress', '0x43C00000', ... + 'MasterAddressSpace', 'sys_ps7/Data'); + case 'ccbox_lvds' + hRD.addAXI4SlaveInterface( ... + 'InterfaceConnection', 'axi_cpu_interconnect/M05_AXI', ... + 'BaseAddress', '0x43C00000', ... + 'MasterAddressSpace', 'sys_ps7/Data'); +end + + +if ~strcmp(design,'Tx') + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + % Rx Reference design interfaces + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data Valid OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_valid', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/adc_valid_0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_1', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_1', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 2 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_2', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_2', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 3 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_3', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_3', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Data I0', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_0_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Data Q0', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_1_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_1', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Data I1', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_2_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_2', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Data Q1', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_3_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_3', ... + 'IsRequired', false); +end + +if ~strcmp(design,'Rx') + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + % Tx Reference design interfaces + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 DAC Data I0', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9361_dac_data_i0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 DAC Data Q0', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9361_dac_data_q0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_1', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 DAC Data I1', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9361_dac_data_i1', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_2', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 DAC Data Q1', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9361_dac_data_q1', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_3', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_00', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_01', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_1', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 2 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_02', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_2', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 3 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_03', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_3', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Load Tx Data OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'util_dac_unpack_dac_valid_00', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/dac_valid_0', ... + 'IsRequired', false); + + hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Valid Tx Data IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_upack_valid_00', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/upack_valid_0', ... + 'IsRequired', false); + +end diff --git a/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/hdlcoder_ref_design_customization.m b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/hdlcoder_ref_design_customization.m new file mode 100644 index 0000000..fe2d456 --- /dev/null +++ b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/hdlcoder_ref_design_customization.m @@ -0,0 +1,20 @@ +function [rd,boardName] = hdlcoder_ref_design_customization +% Reference design plugin registration file +% 1. The registration file with this name inside of a board plugin folder +% will be picked up +% 2. Any registration file with this name on MATLAB path will also be picked up +% 3. The registration file returns a cell array pointing to the location of +% the reference design plugins +% 4. The registration file also returns its associated board name +% 5. Reference design plugin must be a package folder accessible from +% MATLAB path, and contains a reference design definition file + +% Copyright 2013-2014 The MathWorks, Inc. + +rd = {... + 'AnalogDevicesDemo.adrv9361z7035.ccfmc_lvds_hop.rxtx.plugin_rd', ... + }; + +boardName = 'AnalogDevices ADRV9361-Z7035 Frequency Hopping'; + +end diff --git a/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/plugin_board.m b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/plugin_board.m new file mode 100644 index 0000000..d09af3f --- /dev/null +++ b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/plugin_board.m @@ -0,0 +1,29 @@ +function hB = plugin_board() +% Use Plugin API to create board plugin object + +% Copyright 2015 The MathWorks, Inc. + +hB = hdlcoder.Board; + +% Target Board Information +hB.BoardName = sprintf('AnalogDevices ADRV9361-Z7035 Frequency Hopping'); + +% FPGA Device +hB.FPGAVendor = 'Xilinx'; +hB.FPGAFamily = 'Zynq'; + +% Determine the device based on the board +hB.FPGADevice = sprintf('xc7%s', 'z035i'); +hB.FPGAPackage = 'fbg676'; +hB.FPGASpeed = '-2L'; + + +% Tool Info +hB.SupportedTool = {'Xilinx Vivado'}; + +% FPGA JTAG chain position +hB.JTAGChainPosition = 2; + +%% Add interfaces +% Standard "External Port" interface + diff --git a/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/plugin_rd.m b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/plugin_rd.m new file mode 100644 index 0000000..771a0a9 --- /dev/null +++ b/targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+common/plugin_rd.m @@ -0,0 +1,72 @@ +function hRD = plugin_rd(board, design) +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Construct reference design object +hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado'); + +% Create the reference design for the SOM-only +% This is the base reference design that other RDs can build upon +hRD.ReferenceDesignName = sprintf('ADRV9361 %s (%s)', upper(board), design); + +% Determine the board name based on the design +hRD.BoardName = sprintf('AnalogDevices ADRV9361-Z7035 Frequency Hopping'); + +% Tool information +hRD.SupportedToolVersion = {'2017.4'}; + +% DMA Configuration +hRD.addParameter( ... + 'ParameterID', 'dma_config', ... + 'DisplayName', 'DMA Config', ... + 'DefaultValue', 'Stream', ... + 'ParameterType', hdlcoder.ParameterType.Dropdown, ... + 'Choice', {'Stream', 'Packetized'}); + +% Get the root directories +rootDirExample = fileparts(strtok(mfilename('fullpath'), '+')); +tmp = strsplit(rootDirExample,'/'); + +rootDir = fullfile('/',tmp{1:end-2}); +rootDirBSP = fullfile('hdl_wa_bsp','vendor','AnalogDevices','vivado'); + +% Design files are shared +hRD.SharedRD = true; +hRD.SharedRDFolder = rootDir; + +%% Add custom design files +% add custom Vivado design +hRD.addCustomVivadoDesign( ... + 'CustomBlockDesignTcl', fullfile('targeting_models', 'frequency-hopping', 'ccfmc_lvds_hop', 'system_project_rx_tx.tcl'), ... + 'CustomTopLevelHDL', fullfile('targeting_models', 'frequency-hopping', 'ccfmc_lvds_hop', 'system_top.v')); + + +%% Standard reference design pieces +hRD.BlockDesignName = 'system'; + +% custom constraint files +board_type = strsplit(board,'_'); +hRD.CustomConstraints = {... + fullfile(rootDirBSP, 'projects', 'adrv9361z7035', 'common', strcat(board_type{1}, '_constr.xdc')), ... + fullfile(rootDirBSP, 'projects', 'adrv9361z7035', 'common', 'adrv9361z7035_constr.xdc'), ... + fullfile(rootDirBSP, 'projects', 'adrv9361z7035', 'common', strcat('adrv9361z7035_constr_', board_type{2}, '.xdc')), ... + }; + +% custom source files +hRD.CustomFiles = {... + fullfile(rootDirBSP, 'library')..., + fullfile(rootDirBSP, 'library','xilinx')..., + fullfile(rootDirBSP, 'projects','common')..., + fullfile(rootDirBSP, 'projects','scripts')..., + fullfile(rootDirBSP, 'projects','fmcomms2')..., + fullfile(rootDirBSP, 'projects','adrv9361z7035', 'common')..., + fullfile('targeting_models', 'frequency-hopping', 'ccfmc_lvds_hop')..., + }; + +%% Add interfaces +% add clock interface +hRD.addClockInterface( ... + 'ClockConnection', 'util_ad9361_divclk/clk_out', ... + 'ResetConnection', 'util_ad9361_divclk_reset/peripheral_aresetn'); + diff --git a/targeting_models/frequency-hopping/FrequencyHopper.m b/targeting_models/frequency-hopping/FrequencyHopper.m new file mode 100644 index 0000000..b6f0318 --- /dev/null +++ b/targeting_models/frequency-hopping/FrequencyHopper.m @@ -0,0 +1,118 @@ +classdef FrequencyHopper < adi.common.Attribute & ... + adi.common.DebugAttribute & adi.common.Rx & ... + matlabshared.libiio.base + %FrequencyHopper Frequency Hopper controller + properties + DwellSamples = 1024; + ManualProfileIndex = 0; + end + + properties (Logical) + ManualProfileEnable = false; + HoppingEnable = false; + ForcedEnabled = true; + end + + properties(Nontunable, Hidden) + Timeout = Inf; + kernelBuffersCount = 0; + dataTypeStr = 'int16'; + phyDevName = 'axi-hopper'; + iioDevPHY + channelCount = 0; + devName = 'axi-hopper'; + SamplesPerFrame = 0; + end + + properties(Nontunable, Hidden, Constant) + Type = 'Rx'; + end + + properties (Hidden, Nontunable, Access = protected) + isOutput = false; + end + + methods + %% Constructor + function obj = FrequencyHopper(varargin) + coder.allowpcode('plain'); + obj = obj@matlabshared.libiio.base(varargin{:}); + end + % Destructor + function delete(obj) + end + % Check SamplesPerFrame + function set.DwellSamples(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>',0,'<=',2^32}, ... + '', 'DwellSamples'); + obj.DwellSamples = value; + if obj.ConnectedToDevice + obj.setDeviceAttributeRAW('dwell_samples',num2str(value)); + end + end + % Check ManualProfileIndex + function set.ManualProfileIndex(obj, value) + validateattributes( value, { 'double','single' }, ... + { 'real', 'positive','scalar', 'finite', 'nonnan', 'nonempty','integer','>',0,'<=',7}, ... + '', 'DwellSamples'); + obj.ManualProfileIndex = value; + if obj.ConnectedToDevice + obj.setDeviceAttributeRAW('manual_profile_indx',num2str(value)); + end + end + + % Check ManualProfileEnable + function set.ManualProfileEnable(obj, value) + obj.ManualProfileEnable = value; + if obj.ConnectedToDevice + obj.setDeviceAttributeRAW('manual_profile_enable',num2str(value)); + end + end + % Check HoppingEnable + function set.HoppingEnable(obj, value) + obj.HoppingEnable = value; + if obj.ConnectedToDevice + obj.setDeviceAttributeRAW('hopping_enable',num2str(value)); + end + end + % Check HoppingEnable + function set.ForcedEnabled(obj, value) + obj.ForcedEnabled = value; + if obj.ConnectedToDevice + obj.setDeviceAttributeRAW('forced_enable',num2str(value)); + end + end + end + + %% API Functions + methods (Hidden, Access = protected) + function setupInit(obj) + % Do writes directly to hardware without using set methods. + % This is required sine Simulink support doesn't support + % modification to nontunable variables at SetupImpl + obj.setDeviceAttributeRAW('dwell_samples',num2str(obj.DwellSamples)); + obj.setDeviceAttributeRAW('manual_profile_indx',num2str(obj.ManualProfileIndex)); + obj.setDeviceAttributeRAW('manual_profile_enable',num2str(obj.ManualProfileEnable)); + obj.setDeviceAttributeRAW('hopping_enable',num2str(obj.HoppingEnable)); + obj.setDeviceAttributeRAW('forced_enable',num2str(obj.ForcedEnabled)); + end + end + + %% External Dependency Methods + methods (Hidden, Static) + + function tf = isSupportedContext(bldCfg) + tf = matlabshared.libiio.ExternalDependency.isSupportedContext(bldCfg); + end + + function updateBuildInfo(buildInfo, bldCfg) + % Call the matlabshared.libiio.method first + matlabshared.libiio.ExternalDependency.updateBuildInfo(buildInfo, bldCfg); + end + + end +end + + + diff --git a/targeting_models/frequency-hopping/adi_build.tcl b/targeting_models/frequency-hopping/adi_build.tcl new file mode 100644 index 0000000..98032ec --- /dev/null +++ b/targeting_models/frequency-hopping/adi_build.tcl @@ -0,0 +1,29 @@ +# Build the project +update_compile_order -fileset sources_1 +reset_run impl_1 +reset_run synth_1 +launch_runs synth_1 +wait_on_run synth_1 +launch_runs impl_1 -to_step write_bitstream +wait_on_run impl_1 + +# Define local variables +set cdir [pwd] +set sdk_loc vivado_prj.sdk + +# Export the hdf +file delete -force $sdk_loc +file mkdir $sdk_loc +file copy -force vivado_prj.runs/impl_1/system_top.sysdef $sdk_loc/system_top.hdf + +# Close the Vivado project +close_project + +# Create the BOOT.bin +exec xsdk -batch -source $cdir/projects/scripts/fsbl_build.tcl -wait + +puts "------------------------------------" +puts "Embedded system build completed." +puts "You may close this shell." +puts "------------------------------------" +exit diff --git a/targeting_models/frequency-hopping/build_kernel.sh b/targeting_models/frequency-hopping/build_kernel.sh new file mode 100755 index 0000000..d9d4ce9 --- /dev/null +++ b/targeting_models/frequency-hopping/build_kernel.sh @@ -0,0 +1,13 @@ +#!/bin/bash + +# Build kernel +git clone https://github.com/analogdevicesinc/linux.git +cd linux +git checkout 2018_R1 +export ARCH=arm +export CROSS_COMPILE=arm-linux-gnueabihf- +source /opt/Xilinx/Vivado/2017.4/settings64.sh +cp ../hopper.patch . +git apply hopper.patch +make zynq_xcomm_adv7511_defconfig +make -j4 UIMAGE_LOADADDR=0x8000 uImage diff --git a/targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/u-boot.elf b/targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/u-boot.elf new file mode 100644 index 0000000..d074293 Binary files /dev/null and b/targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/u-boot.elf differ diff --git a/targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/uEnv.txt b/targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/uEnv.txt new file mode 100644 index 0000000..1ecc474 --- /dev/null +++ b/targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/uEnv.txt @@ -0,0 +1,4 @@ +uenvcmd=run adi_sdboot +adi_sdboot=echo Copying Linux from SD to RAM... && fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && if fatload mmc 0 0x2000000 ${ramdisk_image}; then bootm 0x3000000 0x2000000 0x2A00000; else bootm 0x3000000 - 0x2A00000; fi +bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait + diff --git a/targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/zynq.bif b/targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/zynq.bif new file mode 100644 index 0000000..185abfd --- /dev/null +++ b/targeting_models/frequency-hopping/ccfmc_lvds_hop/boot/zynq.bif @@ -0,0 +1,6 @@ +the_ROM_image: +{ +[bootloader]./vivado_prj.sdk/fsbl/Release/fsbl.elf +./vivado_prj.sdk/hw_0/system_top.bit +./boot/u-boot.elf +} diff --git a/targeting_models/frequency-hopping/ccfmc_lvds_hop/config_prj.tcl b/targeting_models/frequency-hopping/ccfmc_lvds_hop/config_prj.tcl new file mode 100644 index 0000000..49bfa5c --- /dev/null +++ b/targeting_models/frequency-hopping/ccfmc_lvds_hop/config_prj.tcl @@ -0,0 +1,4 @@ +# Add 1 extra AXI master ports to the interconnect +set_property -dict [list CONFIG.NUM_MI {12}] [get_bd_cells axi_cpu_interconnect] +connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M11_ACLK] [get_bd_pins util_ad9361_divclk/clk_out] +connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M11_ARESETN] diff --git a/targeting_models/frequency-hopping/ccfmc_lvds_hop/config_rx.tcl b/targeting_models/frequency-hopping/ccfmc_lvds_hop/config_rx.tcl new file mode 100644 index 0000000..d74a1a6 --- /dev/null +++ b/targeting_models/frequency-hopping/ccfmc_lvds_hop/config_rx.tcl @@ -0,0 +1,7 @@ +set ad_hdl_dir [pwd] +set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_agc + +source $proj_dir/config_prj.tcl +source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl + +regenerate_bd_layout \ No newline at end of file diff --git a/targeting_models/frequency-hopping/ccfmc_lvds_hop/config_rx_tx.tcl b/targeting_models/frequency-hopping/ccfmc_lvds_hop/config_rx_tx.tcl new file mode 100644 index 0000000..2381829 --- /dev/null +++ b/targeting_models/frequency-hopping/ccfmc_lvds_hop/config_rx_tx.tcl @@ -0,0 +1,8 @@ +set ad_hdl_dir [pwd] +set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_hop + +source $proj_dir/config_prj.tcl +source $ad_hdl_dir/projects/adrv9361z7035/common/config_rx.tcl +source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl + +regenerate_bd_layout \ No newline at end of file diff --git a/targeting_models/frequency-hopping/ccfmc_lvds_hop/config_tx.tcl b/targeting_models/frequency-hopping/ccfmc_lvds_hop/config_tx.tcl new file mode 100644 index 0000000..9c69506 --- /dev/null +++ b/targeting_models/frequency-hopping/ccfmc_lvds_hop/config_tx.tcl @@ -0,0 +1,7 @@ +set ad_hdl_dir [pwd] +set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_agc + +source $proj_dir/config_prj.tcl +source $ad_hdl_dir/projects/adrv9361z7035/common/config_tx.tcl + +regenerate_bd_layout \ No newline at end of file diff --git a/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_bd.tcl b/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_bd.tcl new file mode 100644 index 0000000..3836fd4 --- /dev/null +++ b/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_bd.tcl @@ -0,0 +1,19 @@ + +source $ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_bd.tcl +source $ad_hdl_dir/projects/adrv9361z7035/common/ccfmc_bd.tcl + +cfg_ad9361_interface LVDS + +create_bd_port -dir O sys_cpu_clk_out +ad_connect sys_cpu_clk sys_cpu_clk_out + +ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 29 + +# Add external pin for EN_AGC +create_bd_port -dir O gpio_en_agc + +# Add external pins for CTRL_IN +create_bd_port -from 0 -to 7 -dir I gpio_status + +# Add external pins for CTRL_OUT +create_bd_port -from 0 -to 3 -dir O gpio_ctl \ No newline at end of file diff --git a/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_project_rx.tcl b/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_project_rx.tcl new file mode 100644 index 0000000..263e661 --- /dev/null +++ b/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_project_rx.tcl @@ -0,0 +1,26 @@ +set ad_hdl_dir [pwd] +set ad_phdl_dir [pwd] +set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_agc + +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z035ifbg676-2L" +adi_project_xilinx adrv9361z7035_ccfmc_lvds_agc $proj_dir config_rx.tcl +adi_project_files adrv9361z7035_ccfmc_lvds_agc [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_adl5904_rst.v" \ + "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc" \ + "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc" \ + "$ad_hdl_dir/projects/adrv9361z7035/common/ccfmc_constr.xdc" \ + "system_top.v" ] + +adi_project_run adrv9361z7035_ccfmc_lvds_agc +#source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl +# Copy the boot file to the root directory +file copy -force $proj_dir/boot $ad_hdl_dir/boot + +# Add external pin for EN_AGC +#create_bd_port -dir O gpio_en_agc + + diff --git a/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_project_rx_tx.tcl b/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_project_rx_tx.tcl new file mode 100644 index 0000000..857967c --- /dev/null +++ b/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_project_rx_tx.tcl @@ -0,0 +1,30 @@ +set ad_hdl_dir [pwd] +set ad_phdl_dir [pwd] +set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_hop + +#### Move files +file rename -force $ad_hdl_dir/hdl_wa_bsp/vendor/AnalogDevices/vivado/projects $ad_hdl_dir/projects +file rename -force $ad_hdl_dir/hdl_wa_bsp/vendor/AnalogDevices/vivado/library $ad_hdl_dir/library +file copy -force $ad_hdl_dir/targeting_models/frequency-hopping/ccfmc_lvds_hop $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_hop +#### + +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z035ifbg676-2L" +adi_project_xilinx adrv9361z7035_ccfmc_lvds_hop $proj_dir config_rx_tx.tcl +adi_project_files adrv9361z7035_ccfmc_lvds_hop [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_adl5904_rst.v" \ + "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc" \ + "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc" \ + "$ad_hdl_dir/projects/adrv9361z7035/common/ccfmc_constr.xdc" \ + "system_top.v" ] + +adi_project_run adrv9361z7035_ccfmc_lvds_hop +#source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl +# Copy the boot file to the root directory +file copy -force $proj_dir/boot $ad_hdl_dir/boot + +# Add external pin for EN_AGC +#create_bd_port -dir O gpio_en_agc diff --git a/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_project_tx.tcl b/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_project_tx.tcl new file mode 100644 index 0000000..26ab5a9 --- /dev/null +++ b/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_project_tx.tcl @@ -0,0 +1,22 @@ +set ad_hdl_dir [pwd] +set ad_phdl_dir [pwd] +set proj_dir $ad_hdl_dir/projects/adrv9361z7035/ccfmc_lvds_agc + +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z035ifbg676-2L" +adi_project_xilinx adrv9361z7035_ccfmc_lvds_agc $proj_dir config_tx.tcl +adi_project_files adrv9361z7035_ccfmc_lvds_agc [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_adl5904_rst.v" \ + "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc" \ + "$ad_hdl_dir/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc" \ + "$ad_hdl_dir/projects/adrv9361z7035/common/ccfmc_constr.xdc" \ + "system_top.v" ] + +adi_project_run adrv9361z7035_ccfmc_lvds_agc +#source $ad_hdl_dir/library/analog.com_user_axi_ad9361_1.0/axi_ad9361_delay.tcl +# Copy the boot file to the root directory +file copy -force $proj_dir/boot $ad_hdl_dir/boot + diff --git a/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_top.v b/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_top.v new file mode 100644 index 0000000..9608a95 --- /dev/null +++ b/targeting_models/frequency-hopping/ccfmc_lvds_hop/system_top.v @@ -0,0 +1,429 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + output eth1_mdc, + inout eth1_mdio, + input eth1_rgmii_rxclk, + input eth1_rgmii_rxctl, + input [ 3:0] eth1_rgmii_rxdata, + output eth1_rgmii_txclk, + output eth1_rgmii_txctl, + output [ 3:0] eth1_rgmii_txdata, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + output hdmi_pd, + input hdmi_intn, + + output spdif, + input spdif_in, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + inout iic_scl, + inout iic_sda, + + inout [20:0] gpio_bd, + + output fan_pwm, + input fan_tach, + + input clk_0_p, + input clk_0_n, + input clk_1_p, + input clk_1_n, + output [53:0] gp_out, + input [53:0] gp_in, + + input gt_ref_clk_0_p, + input gt_ref_clk_0_n, + input gt_ref_clk_1_p, + input gt_ref_clk_1_n, + output [ 1:0] gt_tx_p, + output [ 1:0] gt_tx_n, + input [ 1:0] gt_rx_p, + input [ 1:0] gt_rx_n, + + output ad9517_csn, + output ad9517_clk, + output ad9517_mosi, + input ad9517_miso, + inout ad9517_pdn, + inout ad9517_ref_sel, + inout ad9517_ld, + inout ad9517_status, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + input clkout_in, + inout tdd_sync, + + inout gpio_rf0, + output gpio_rf1, + output gpio_rf2, + input gpio_rf3, + input gpio_rf4, + inout gpio_rf5, + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + output gpio_en_agc, + output [ 3:0] gpio_ctl, + input [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [ 1:0] spi_csn_s; + wire spi_clk_s; + wire spi_mosi_s; + wire spi_miso_s; + wire sys_cpu_clk; + wire clk_0; + wire clk_1; + wire gt_ref_clk_1; + wire gt_ref_clk_0; + wire [63:0] gp_out_s; + wire [63:0] gp_in_s; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire tdd_sync_i; + wire tdd_sync_o; + wire tdd_sync_t; + + // assignments + + assign fan_pwm = 1'b1; + assign hdmi_pd = 1'b0; + assign spi_csn = spi_csn_s[0]; + assign spi_clk = spi_clk_s; + assign spi_mosi = spi_mosi_s; + assign ad9517_csn = spi_csn_s[1]; + assign ad9517_clk = spi_clk_s; + assign ad9517_mosi = spi_mosi_s; + assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso); + + // loopback signals + + assign gp_out[53:0] = gp_out_s[53:0]; + assign gp_in_s[63:54] = gp_out_s[63:54]; + assign gp_in_s[53:0] = gp_in[53:0]; + + // instantiations + + IBUFDS i_ibufds_clk_0 ( + .I (clk_0_p), + .IB (clk_0_n), + .O (clk_0)); + + IBUFDS i_ibufds_clk_1 ( + .I (clk_1_p), + .IB (clk_1_n), + .O (clk_1)); + + IBUFDS_GTE2 i_ibufds_gt_ref_clk_0 ( + .CEB (1'd0), + .I (gt_ref_clk_0_p), + .IB (gt_ref_clk_0_n), + .O (gt_ref_clk_0), + .ODIV2 ()); + + IBUFDS_GTE2 i_ibufds_gt_ref_clk_1 ( + .CEB (1'd0), + .I (gt_ref_clk_1_p), + .IB (gt_ref_clk_1_n), + .O (gt_ref_clk_1), + .ODIV2 ()); + + ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync ( + .dio_t (tdd_sync_t), + .dio_i (tdd_sync_o), + .dio_o (tdd_sync_i), + .dio_p (tdd_sync)); + + // board gpio - 31-0 + + assign gpio_i[31:21] = gpio_o[31:21]; + + ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd ( + .dio_t (gpio_t[20:0]), + .dio_i (gpio_o[20:0]), + .dio_o (gpio_i[20:0]), + .dio_p (gpio_bd)); + + // unused gpio - 63-61 + + assign gpio_i[63:61] = gpio_o[63:61]; + + // rf & ad9517 gpio - 60:56 + + ad_iobuf #(.DATA_WIDTH(5)) i_iobuf ( + .dio_t (gpio_t[60:56]), + .dio_i (gpio_o[60:56]), + .dio_o (gpio_i[60:56]), + .dio_p ({ ad9517_pdn, // 60:60 + ad9517_ref_sel, // 59:59 + ad9517_ld, // 58:58 + ad9517_status, // 57:57 + gpio_rf0})); // 56:56 + + // unused gpio - 55:53 + + assign gpio_i[55:53] = gpio_o[55:53]; + + // rf & clock-select gpio - 52:51 + + ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_rf_1 ( + .dio_t (gpio_t[52:51]), + .dio_i (gpio_o[52:51]), + .dio_o (gpio_i[52:51]), + .dio_p ({ gpio_rf5, // 52:52 + gpio_clksel})); // 51:51 + + // unused gpio - 50:47 + + assign gpio_i[50:47] = gpio_o[50:47]; + + // ad9361 gpio - 46:32 + +// ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_ad9361 ( +// .dio_t (gpio_t[46:32]), +// .dio_i (gpio_o[46:32]), +// .dio_o (gpio_i[46:32]), +// .dio_p ({ gpio_resetb, // 46:46 +// gpio_sync, // 45:45 +// gpio_en_agc, // 44:44 +// gpio_ctl, // 43:40 +// gpio_status})); // 39:32 + +// ad_iobuf #(.DATA_WIDTH(14)) i_iobuf_ad9361 ( +// .dio_t ({gpio_t[46:45], gpio_t[43:32]}), +// .dio_i ({gpio_o[46:45], gpio_o[43:32]}), +// .dio_o ({gpio_i[46:45], gpio_i[43:32]}), +// .dio_p ({ gpio_resetb, // 46:46 +// gpio_sync, // 45:45 +// gpio_ctl, // 43:40 +// gpio_status})); // 39:32 + + ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_ad9361 ( + .dio_t ({gpio_t[46:45]}), + .dio_i ({gpio_o[46:45]}), + .dio_o ({gpio_i[46:45]}), + .dio_p ({ gpio_resetb, // 46:46 + gpio_sync })); // 45:45 + + // ad9361 input protection + + ad_adl5904_rst i_adl5904_rst_a ( + .sys_cpu_clk (sys_cpu_clk), + .rf_peak_det_n (gpio_rf4), + .rf_peak_rst (gpio_rf2)); + + ad_adl5904_rst i_adl5904_rst_b ( + .sys_cpu_clk (sys_cpu_clk), + .rf_peak_det_n (gpio_rf3), + .rf_peak_rst (gpio_rf1)); + + // instantiations + + system_wrapper i_system_wrapper ( + .clk_0 (clk_0), + .clk_1 (clk_1), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .eth1_intn (1'b1), + .eth1_mdio_mdc (eth1_mdc), + .eth1_mdio_mdio_io (eth1_mdio), + .eth1_rgmii_rd (eth1_rgmii_rxdata), + .eth1_rgmii_rx_ctl (eth1_rgmii_rxctl), + .eth1_rgmii_rxc (eth1_rgmii_rxclk), + .eth1_rgmii_td (eth1_rgmii_txdata), + .eth1_rgmii_tx_ctl (eth1_rgmii_txctl), + .eth1_rgmii_txc (eth1_rgmii_txclk), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gp_in_0 (gp_in_s[31:0]), + .gp_in_1 (gp_in_s[63:32]), + .gp_out_0 (gp_out_s[31:0]), + .gp_out_1 (gp_out_s[63:32]), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .gt_ref_clk_0 (gt_ref_clk_0), + .gt_ref_clk_1 (gt_ref_clk_1), + .gt_rx_n (gt_rx_n), + .gt_rx_p (gt_rx_p), + .gt_tx_n (gt_tx_n), + .gt_tx_p (gt_tx_p), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk_s), + .spi0_csn_0_o (spi_csn_s[0]), + .spi0_csn_1_o (spi_csn_s[1]), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso_s), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi_s), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .sys_cpu_clk_out (sys_cpu_clk), + .tdd_sync_i (tdd_sync_i), + .tdd_sync_o (tdd_sync_o), + .tdd_sync_t (tdd_sync_t), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48]), + .gpio_en_agc (gpio_en_agc), + .gpio_status (gpio_status), + .gpio_ctl (gpio_ctl)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/targeting_models/frequency-hopping/devicetree.dtb b/targeting_models/frequency-hopping/devicetree.dtb new file mode 100644 index 0000000..08250c9 Binary files /dev/null and b/targeting_models/frequency-hopping/devicetree.dtb differ diff --git a/targeting_models/frequency-hopping/fastlock.m b/targeting_models/frequency-hopping/fastlock.m new file mode 100644 index 0000000..6e8a5b0 --- /dev/null +++ b/targeting_models/frequency-hopping/fastlock.m @@ -0,0 +1,53 @@ +clear all +uri = 'ip:192.168.86.35'; + +%% Turn on DDS +tx = adi.AD9361.Tx('uri',uri); +tx.DataSource = 'DDS'; +tx.SamplingRate = 20e6; +tx.RFBandwidth = 20e6; +toneFreq = 4e6; +tx.DDSFrequencies = repmat(toneFreq,2,4); +tx.AttenuationChannel0 = -10; +tx(); +pause(1); +%% Set up fastlock profiles +freqs = 2.4e9+(1:8).*1e6; +for f = 0:length(freqs)-1 + % Update LO + tx.CenterFrequency = freqs(f+1); + pause(1); + % Save profile + tx.setAttributeLongLong('altvoltage1','fastlock_store',int64(f),true,8); + fprintf('Saving profile at LO %d\n',freqs(f+1)); +end +% Set pin control mode +tx.setDebugAttributeBool('adi,tx-fastlock-pincontrol-enable',1); +tx.setAttributeLongLong('altvoltage1','fastlock_recall',int64(0),true,8); +%% Configure Hop mode +h = FrequencyHopper; +h.uri = uri; +h.DwellSamples = 20000; +h.HoppingEnable = true; +h(); +%% Capture +rx = adi.AD9361.Rx('uri',uri); +rx.SamplingRate = 20e6; +rx.CenterFrequency = 2.4e9+0.5e6; +rx.RFBandwidth = 20e6; +rx.SamplesPerFrame = 1e6; +rx.channelCount = 2; +rx.kernelBuffersCount = 1; +for k=1:10 + valid = false; + while ~valid + [out, valid] = rx(); + end +end +rx.release(); +%% Plot +spectrogram(double(out),128,80,100,20e6,'yaxis','centered') +view(-77,72) +shading interp +colorbar off + diff --git a/targeting_models/frequency-hopping/frequency_hopping.slx b/targeting_models/frequency-hopping/frequency_hopping.slx new file mode 100644 index 0000000..c6286bc Binary files /dev/null and b/targeting_models/frequency-hopping/frequency_hopping.slx differ diff --git a/targeting_models/frequency-hopping/hdlcoder_board_customization.m b/targeting_models/frequency-hopping/hdlcoder_board_customization.m new file mode 100644 index 0000000..c7e7db3 --- /dev/null +++ b/targeting_models/frequency-hopping/hdlcoder_board_customization.m @@ -0,0 +1,15 @@ +function r = hdlcoder_board_customization +% Board plugin registration file +% 1. Any registration file with this name on MATLAB path will be picked up +% 2. Registration file returns a cell array pointing to the location of +% the board plugins +% 3. Board plugin must be a package folder accessible from MATLAB path, +% and contains a board definition file + +% Copyright 2012-2013 The MathWorks, Inc. + +r = { ... + 'AnalogDevicesDemo.adrv9361z7035.common.plugin_board', ... + }; +end +% LocalWords: Zynq ZC diff --git a/targeting_models/frequency-hopping/hdlworkflow.m b/targeting_models/frequency-hopping/hdlworkflow.m new file mode 100644 index 0000000..486022f --- /dev/null +++ b/targeting_models/frequency-hopping/hdlworkflow.m @@ -0,0 +1,180 @@ +%-------------------------------------------------------------------------- +% HDL Workflow Script +% Generated with MATLAB 9.5 (R2018b) at 16:05:58 on 14/05/2019 +% This script was generated using the following parameter values: +% Filename : '/work/mwt-hopper/targeting_models/frequency-hopping/hdlworkflow2.m' +% Overwrite : true +% Comments : true +% Headers : true +% DUT : 'frequency_hopping/HDL_DUT' +% To view changes after modifying the workflow, run the following command: +% >> hWC.export('DUT','frequency_hopping/HDL_DUT'); +%-------------------------------------------------------------------------- + +%% Load the Model +load_system('frequency_hopping'); + +%% Restore the Model to default HDL parameters +%hdlrestoreparams('frequency_hopping/HDL_DUT'); + +%% Model HDL Parameters +%% Set Model 'frequency_hopping' HDL parameters +hdlset_param('frequency_hopping', 'HDLSubsystem', 'frequency_hopping/HDL_DUT'); +hdlset_param('frequency_hopping', 'ReferenceDesign', 'ADRV9361 CCFMC_LVDS_HOP (Rx & Tx)'); +hdlset_param('frequency_hopping', 'ReferenceDesignParameter', {'dma_config','Packetized'}); +hdlset_param('frequency_hopping', 'SynthesisTool', 'Xilinx Vivado'); +hdlset_param('frequency_hopping', 'SynthesisToolChipFamily', 'Zynq'); +hdlset_param('frequency_hopping', 'SynthesisToolDeviceName', 'xc7z035i'); +hdlset_param('frequency_hopping', 'SynthesisToolPackageName', 'fbg676'); +hdlset_param('frequency_hopping', 'SynthesisToolSpeedValue', '-2L'); +hdlset_param('frequency_hopping', 'TargetDirectory', 'hdl_prj/hdlsrc'); +hdlset_param('frequency_hopping', 'TargetLanguage', 'Verilog'); +hdlset_param('frequency_hopping', 'TargetPlatform', 'AnalogDevices ADRV9361-Z7035 Frequency Hopping'); +hdlset_param('frequency_hopping', 'Workflow', 'IP Core Generation'); + +% Set SubSystem HDL parameters +hdlset_param('frequency_hopping/HDL_DUT', 'ProcessorFPGASynchronization', 'Free running'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/inReal1', 'IOInterface', 'AD9361 ADC Data I0 [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/inReal1', 'IOInterfaceMapping', '[0:15]'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/inImag1', 'IOInterface', 'AD9361 ADC Data Q0 [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/inImag1', 'IOInterfaceMapping', '[0:15]'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/inReal', 'IOInterface', 'IP Data 0 IN [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/inReal', 'IOInterfaceMapping', '[0:15]'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/inImag', 'IOInterface', 'IP Data 1 IN [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/inImag', 'IOInterfaceMapping', '[0:15]'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/ctrl_out', 'IOInterface', 'CTRL_STATUS [0:7]'); +hdlset_param('frequency_hopping/HDL_DUT/ctrl_out', 'IOInterfaceMapping', '[0:7]'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/dwell_samples', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/dwell_samples', 'IOInterfaceMapping', 'x"100"'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/enableHopping', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/enableHopping', 'IOInterfaceMapping', 'x"104"'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/TxDMAEnable', 'IOInterface', 'DMA Ready'); +hdlset_param('frequency_hopping/HDL_DUT/TxDMAEnable', 'IOInterfaceMapping', '[0]'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/manual_profile', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/manual_profile', 'IOInterfaceMapping', 'x"120"'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/use_manual', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/use_manual', 'IOInterfaceMapping', 'x"124"'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/force_enable', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/force_enable', 'IOInterfaceMapping', 'x"108"'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/outReal1', 'IOInterface', 'IP Data 0 OUT [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/outReal1', 'IOInterfaceMapping', '[0:15]'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/outImag1', 'IOInterface', 'IP Data 1 OUT [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/outImag1', 'IOInterfaceMapping', '[0:15]'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/outReal', 'IOInterface', 'AD9361 DAC Data I0 [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/outReal', 'IOInterfaceMapping', '[0:15]'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/outImag', 'IOInterface', 'AD9361 DAC Data Q0 [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/outImag', 'IOInterfaceMapping', '[0:15]'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/enable', 'IOInterface', 'IP Data Valid OUT'); +hdlset_param('frequency_hopping/HDL_DUT/enable', 'IOInterfaceMapping', '[0]'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/ctrl_in', 'IOInterface', 'AD9361 CTRL IN [0:3]'); +hdlset_param('frequency_hopping/HDL_DUT/ctrl_in', 'IOInterfaceMapping', '[0:3]'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/profile', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/profile', 'IOInterfaceMapping', 'x"10C"'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/hop_delay', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/hop_delay', 'IOInterfaceMapping', 'x"110"'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/pll_status', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/pll_status', 'IOInterfaceMapping', 'x"114"'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/hop_count', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/hop_count', 'IOInterfaceMapping', 'x"118"'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/state', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/state', 'IOInterfaceMapping', 'x"11C"'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/pll_unlocks', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/pll_unlocks', 'IOInterfaceMapping', 'x"128"'); + + +%% Workflow Configuration Settings +% Construct the Workflow Configuration Object with default settings +hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx Vivado','TargetWorkflow','IP Core Generation'); + +% Specify the top level project directory +hWC.ProjectFolder = 'hdl_prj'; +hWC.ReferenceDesignToolVersion = '2017.4'; +hWC.IgnoreToolVersionMismatch = false; + +% Set Workflow tasks to run +hWC.RunTaskGenerateRTLCodeAndIPCore = true; +hWC.RunTaskCreateProject = true; +hWC.RunTaskGenerateSoftwareInterfaceModel = false; +hWC.RunTaskBuildFPGABitstream = true; +hWC.RunTaskProgramTargetDevice = false; + +% Set properties related to 'RunTaskGenerateRTLCodeAndIPCore' Task +hWC.IPCoreRepository = ''; +hWC.GenerateIPCoreReport = false; + +% Set properties related to 'RunTaskCreateProject' Task +hWC.Objective = hdlcoder.Objective.None; +hWC.AdditionalProjectCreationTclFiles = ''; +hWC.EnableIPCaching = false; + +% Set properties related to 'RunTaskGenerateSoftwareInterfaceModel' Task +hWC.OperatingSystem = ''; + +% Set properties related to 'RunTaskBuildFPGABitstream' Task +hWC.RunExternalBuild = false; +hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Custom; +hWC.CustomBuildTclFile = 'adi_build.tcl'; + +% Set properties related to 'RunTaskProgramTargetDevice' Task +hWC.ProgrammingMethod = hdlcoder.ProgrammingMethod.Download; + +% Validate the Workflow Configuration Object +hWC.validate; + +%% Run the workflow +try + hdlcoder.runWorkflow('frequency_hopping/HDL_DUT', hWC); + bdclose('all'); + out = []; +catch ME + if exist('hdl_prj/vivado_ip_prj/boot/BOOT.BIN','file') + ME = []; + end + out = ME;%.identifier +end diff --git a/targeting_models/frequency-hopping/hop_result.bmp b/targeting_models/frequency-hopping/hop_result.bmp new file mode 100644 index 0000000..46ee963 Binary files /dev/null and b/targeting_models/frequency-hopping/hop_result.bmp differ diff --git a/targeting_models/frequency-hopping/hopper.patch b/targeting_models/frequency-hopping/hopper.patch new file mode 100644 index 0000000..3815610 --- /dev/null +++ b/targeting_models/frequency-hopping/hopper.patch @@ -0,0 +1,413 @@ +commit 0909bedc1a1a096463a714d18a57aae02ccff8a1 +Author: Travis Collins +Date: Tue May 14 16:08:49 2019 -0400 + + Add IIO driver for AD936x frequency hopping controller + + Signed-off-by: Travis Collins + +diff --git a/arch/arm/configs/zynq_xcomm_adv7511_defconfig b/arch/arm/configs/zynq_xcomm_adv7511_defconfig +index 173e195..25bac3a 100644 +--- a/arch/arm/configs/zynq_xcomm_adv7511_defconfig ++++ b/arch/arm/configs/zynq_xcomm_adv7511_defconfig +@@ -359,6 +359,8 @@ CONFIG_ADXRS450=y + CONFIG_ADIS16400=y + CONFIG_ADIS16460=y + CONFIG_ADIS16480=y ++# Custom IP ++CONFIG_HOPPER=y + CONFIG_JESD204=y + CONFIG_AXI_ADXCVR=y + CONFIG_AXI_JESD204B=y +diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig +index 9a3b28d..368a492 100644 +--- a/drivers/iio/Kconfig ++++ b/drivers/iio/Kconfig +@@ -80,6 +80,7 @@ source "drivers/iio/gyro/Kconfig" + source "drivers/iio/health/Kconfig" + source "drivers/iio/humidity/Kconfig" + source "drivers/iio/imu/Kconfig" ++source "drivers/iio/ip/Kconfig" + source "drivers/iio/jesd204/Kconfig" + source "drivers/iio/light/Kconfig" + source "drivers/iio/logic/Kconfig" +diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile +index 68971fe..f568551 100644 +--- a/drivers/iio/Makefile ++++ b/drivers/iio/Makefile +@@ -25,6 +25,7 @@ obj-y += frequency/ + obj-y += health/ + obj-y += humidity/ + obj-y += imu/ ++obj-y += ip/ + obj-y += jesd204/ + obj-y += light/ + obj-y += logic/ +diff --git a/drivers/iio/ip/Kconfig b/drivers/iio/ip/Kconfig +new file mode 100644 +index 0000000..f8dd3af +--- /dev/null ++++ b/drivers/iio/ip/Kconfig +@@ -0,0 +1,16 @@ ++# ++# Custom IP ++# ++# When adding new entries keep the list in alphabetical order ++ ++menu "Custom IP" ++ ++config HOPPER ++ tristate "Analog Devices Custom IP" ++ help ++ Say yes here to build support for Analog Devices Hopper ++ ++ To compile this driver as a module, choose M here: the ++ module will be called hopper. ++ ++endmenu +diff --git a/drivers/iio/ip/Makefile b/drivers/iio/ip/Makefile +new file mode 100644 +index 0000000..7f78566 +--- /dev/null ++++ b/drivers/iio/ip/Makefile +@@ -0,0 +1,6 @@ ++# ++# Makefile iio/amplifiers ++# ++ ++# When adding new entries keep the list in alphabetical order ++obj-$(CONFIG_HOPPER) += hopper.o +diff --git a/drivers/iio/ip/hopper.c b/drivers/iio/ip/hopper.c +new file mode 100644 +index 0000000..eba8fa9 +--- /dev/null ++++ b/drivers/iio/ip/hopper.c +@@ -0,0 +1,328 @@ ++/* ++ * Frequency Hopping HDL CORE driver ++ * ++ * Copyright 2019 Analog Devices Inc. ++ * ++ * Licensed under the GPL-2. ++ */ ++ ++#include ++// #include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* Transceiver Frequency Hopping Control */ ++ ++// Writable ++#define HOPPER_DWELL_SAMPLES 0x100 ++#define HOPPER_ENABLE_HOPPING 0x104 ++#define HOPPER_FORCE_OUT_ENABLE 0x108 ++#define HOPPER_MANUAL_PROFILE 0x120 ++#define HOPPER_MANUAL_PROFILE_ENABLE 0x124 ++// Read only ++#define HOPPER_PROFILE 0x10C ++#define HOPPER_HOPE_DELAY 0x110 ++#define HOPPER_PLL_STATUS 0x114 ++#define HOPPER_HOP_COUNT 0x118 ++#define HOPPER_STATE 0x11C ++#define HOPPER_PLL_UNLOCK_COUNT 0x128 ++ ++struct cf_axi_hopper_state { ++ struct iio_info iio_info; ++ void __iomem *regs; ++ unsigned int dwell_samples; ++ bool hopping_enable; ++ bool forced_enable; ++ bool manual_profile_enable; ++ unsigned int manual_profile_indx; ++}; ++ ++enum { ++ CF_AXI_HOPPER_DWELL_SAMPLES, ++ CF_AXI_HOPPER_HOPPING_ENABLE, ++ CF_AXI_HOPPER_FORCED_ENABLE, ++ CF_AXI_HOPPER_MANUAL_PROFILE_ENABLE, ++ CF_AXI_HOPPER_PROFILE_INDEX, ++}; ++ ++static inline void hopper_write(struct cf_axi_hopper_state *st, ++ unsigned reg, unsigned val) ++{ ++ iowrite32(val, st->regs + reg); ++} ++ ++static inline unsigned int hopper_read(struct cf_axi_hopper_state *st, unsigned reg) ++{ ++ return ioread32(st->regs + reg); ++} ++ ++static inline void hopper_write_config(struct cf_axi_hopper_state *st) ++{ ++ // Set defaults ++ st->dwell_samples = 1024; ++ st->hopping_enable = false; ++ st->forced_enable = true; ++ st->manual_profile_enable = false; ++ st->manual_profile_indx = 0; ++ ++ hopper_write(st, HOPPER_DWELL_SAMPLES, st->dwell_samples); ++ hopper_write(st, HOPPER_ENABLE_HOPPING, st->hopping_enable); ++ hopper_write(st, HOPPER_FORCE_OUT_ENABLE, st->forced_enable); ++ hopper_write(st, HOPPER_MANUAL_PROFILE, st->manual_profile_indx); ++ hopper_write(st, HOPPER_MANUAL_PROFILE_ENABLE, st->manual_profile_enable); ++} ++ ++static ssize_t cf_axi_hopper_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t len) ++{ ++ struct iio_dev *indio_dev = dev_to_iio_dev(dev); ++ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); ++ struct cf_axi_hopper_state *st = iio_priv(indio_dev); ++ bool state; ++ unsigned long readin; ++ int ret = 0; ++ ++ mutex_lock(&indio_dev->mlock); ++ switch ((u32)this_attr->address) { ++ case CF_AXI_HOPPER_DWELL_SAMPLES: ++ ret = kstrtoul(buf, 0, &readin); ++ if (ret) ++ break; ++ if (readin > 2147483648) ++ { ++ ret = -EINVAL; ++ break; ++ } ++ st->dwell_samples = readin; ++ hopper_write(st, HOPPER_DWELL_SAMPLES, readin); ++ break; ++ case CF_AXI_HOPPER_HOPPING_ENABLE: ++ ret = strtobool(buf, &state); ++ if (ret < 0) ++ break; ++ st->hopping_enable = (state ? 1 : 0); ++ hopper_write(st, HOPPER_ENABLE_HOPPING, st->hopping_enable); ++ break; ++ case CF_AXI_HOPPER_FORCED_ENABLE: ++ ret = strtobool(buf, &state); ++ if (ret < 0) ++ break; ++ st->forced_enable = (state ? 1 : 0); ++ hopper_write(st, HOPPER_FORCE_OUT_ENABLE, st->forced_enable); ++ break; ++ case CF_AXI_HOPPER_MANUAL_PROFILE_ENABLE: ++ ret = strtobool(buf, &state); ++ if (ret < 0) ++ break; ++ st->manual_profile_enable = (state ? 1 : 0); ++ hopper_write(st, HOPPER_MANUAL_PROFILE_ENABLE, st->manual_profile_enable); ++ break; ++ case CF_AXI_HOPPER_PROFILE_INDEX: ++ ret = kstrtoul(buf, 0, &readin); ++ if (ret) ++ break; ++ if (readin > 7) ++ { ++ ret = -EINVAL; ++ break; ++ } ++ st->manual_profile_indx = readin; ++ hopper_write(st, HOPPER_MANUAL_PROFILE, readin+readin);// Indexes go in two's ++ break; ++ default: ++ ret = -ENODEV; ++ } ++ mutex_unlock(&indio_dev->mlock); ++ ++ return ret ? ret : len; ++} ++ ++static ssize_t cf_axi_hopper_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct iio_dev *indio_dev = dev_to_iio_dev(dev); ++ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); ++ struct cf_axi_hopper_state *st = iio_priv(indio_dev); ++ int ret; ++ ++ mutex_lock(&indio_dev->mlock); ++ switch ((u32)this_attr->address) { ++ case CF_AXI_HOPPER_DWELL_SAMPLES: ++ ret = sprintf(buf, "%d\n", st->dwell_samples); ++ break; ++ case CF_AXI_HOPPER_HOPPING_ENABLE: ++ ret = sprintf(buf, "%d\n", st->hopping_enable); ++ break; ++ case CF_AXI_HOPPER_FORCED_ENABLE: ++ ret = sprintf(buf, "%d\n", st->forced_enable); ++ break; ++ case CF_AXI_HOPPER_MANUAL_PROFILE_ENABLE: ++ ret = sprintf(buf, "%d\n", st->manual_profile_enable); ++ break; ++ case CF_AXI_HOPPER_PROFILE_INDEX: ++ ret = sprintf(buf, "%d\n", st->manual_profile_indx); ++ break; ++ default: ++ ret = -ENODEV; ++ } ++ mutex_unlock(&indio_dev->mlock); ++ ++ return ret; ++} ++ ++static IIO_DEVICE_ATTR(dwell_samples, S_IRUGO | S_IWUSR, ++ cf_axi_hopper_show, ++ cf_axi_hopper_store, ++ CF_AXI_HOPPER_DWELL_SAMPLES); ++ ++static IIO_DEVICE_ATTR(hopping_enable, S_IRUGO | S_IWUSR, ++ cf_axi_hopper_show, ++ cf_axi_hopper_store, ++ CF_AXI_HOPPER_HOPPING_ENABLE); ++ ++static IIO_DEVICE_ATTR(forced_enable, S_IRUGO | S_IWUSR, ++ cf_axi_hopper_show, ++ cf_axi_hopper_store, ++ CF_AXI_HOPPER_FORCED_ENABLE); ++ ++static IIO_DEVICE_ATTR(manual_profile_enable, S_IRUGO | S_IWUSR, ++ cf_axi_hopper_show, ++ cf_axi_hopper_store, ++ CF_AXI_HOPPER_MANUAL_PROFILE_ENABLE); ++ ++static IIO_DEVICE_ATTR(manual_profile_indx, S_IRUGO | S_IWUSR, ++ cf_axi_hopper_show, ++ cf_axi_hopper_store, ++ CF_AXI_HOPPER_PROFILE_INDEX); ++ ++static struct attribute *cf_axi_hopper_attributes[] = { ++ &iio_dev_attr_dwell_samples.dev_attr.attr, ++ &iio_dev_attr_hopping_enable.dev_attr.attr, ++ &iio_dev_attr_forced_enable.dev_attr.attr, ++ &iio_dev_attr_manual_profile_enable.dev_attr.attr, ++ &iio_dev_attr_manual_profile_indx.dev_attr.attr, ++ NULL, ++}; ++ ++static const struct attribute_group cf_axi_hopper_attribute_group = { ++ .attrs = cf_axi_hopper_attributes, ++}; ++ ++static int cf_axi_hopper_reg_access(struct iio_dev *indio_dev, ++ unsigned reg, unsigned writeval, ++ unsigned *readval) ++{ ++ struct cf_axi_hopper_state *st = iio_priv(indio_dev); ++ int ret; ++ ++ mutex_lock(&indio_dev->mlock); ++ if (readval == NULL) { ++ hopper_write(st, reg & 0xFFFF, writeval); ++ ret = 0; ++ } else { ++ ret = hopper_read(st, reg & 0xFFFF); ++ *readval = ret; ++ ret = 0; ++ } ++ ++ mutex_unlock(&indio_dev->mlock); ++ ++ return ret; ++} ++ ++static const struct iio_info cf_axi_hopper_info = { ++ .driver_module = THIS_MODULE, ++ .debugfs_reg_access = &cf_axi_hopper_reg_access, ++ .attrs = &cf_axi_hopper_attribute_group, ++}; ++ ++/* Match table for of_platform binding */ ++static const struct of_device_id cf_axi_hopper_of_match[] = { ++ { .compatible = "adi,axi-hopper-1.00", .data = 0}, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, cf_axi_hopper_of_match); ++ ++static int cf_axi_hopper_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct cf_axi_hopper_state *st; ++ struct iio_dev *indio_dev; ++ struct resource *res; ++ int ret; ++ ++ dev_err(&pdev->dev, "Device Tree Probing \'%s\'\n", ++ np->name); ++ ++ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); ++ if (!indio_dev) ++ return -ENOMEM; ++ ++ st = iio_priv(indio_dev); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ st->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); ++ if (!st->regs) ++ return -ENOMEM; ++ ++ indio_dev->dev.parent = &pdev->dev; ++ indio_dev->name = np->name; ++ indio_dev->modes = INDIO_DIRECT_MODE; ++ ++ indio_dev->info = &cf_axi_hopper_info; ++ ++ hopper_write_config(st); ++ ++ ret = iio_device_register(indio_dev); ++ if (ret < 0) ++ return ret; ++ ++ dev_info(&pdev->dev, "Analog Devices CF_AXI_HOPPER Mapped\n"); ++ ++ platform_set_drvdata(pdev, indio_dev); ++ ++ return 0; ++} ++ ++static int cf_axi_hopper_remove(struct platform_device *pdev) ++{ ++ struct iio_dev *indio_dev = platform_get_drvdata(pdev); ++ ++ iio_device_unregister(indio_dev); ++ ++ return 0; ++} ++ ++static struct platform_driver cf_axi_hopper_driver = { ++ .driver = { ++ .name = "cf_axi_hopper", ++ .owner = THIS_MODULE, ++ .of_match_table = cf_axi_hopper_of_match, ++ }, ++ .probe = cf_axi_hopper_probe, ++ .remove = cf_axi_hopper_remove, ++}; ++module_platform_driver(cf_axi_hopper_driver); ++ ++MODULE_AUTHOR("Travis Collins "); ++MODULE_DESCRIPTION("Analog Devices Frequency Hopper HDL CORE driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/test/DemoTests.m b/test/DemoTests.m new file mode 100644 index 0000000..a2c415b --- /dev/null +++ b/test/DemoTests.m @@ -0,0 +1,60 @@ +classdef DemoTests < matlab.unittest.TestCase + + properties + root = ''; + end + + methods(TestClassSetup) + function addpaths(testCase) + here = mfilename('fullpath'); + here = strsplit(here,'/'); + here = fullfile('/',here{1:end-2}); + testCase.root = here; + addpath(genpath(fullfile(here,'targeting_models/frequency-hopping'))); + addpath(genpath(fullfile(here,'hdl_wa_bsp'))); + end + function setupVivado(~) + v=ver('matlab'); Release = v.Release; + switch Release + case '(R2017a)' + vivado = '2016.2'; + case '(R2017b)' + vivado = '2017.4'; + case '(R2018b)' + vivado = '2017.4'; + end + if ispc + hdlsetuptoolpath('ToolName', 'Xilinx Vivado', ... + 'ToolPath', ['C:\Xilinx\Vivado\',vivado,'\bin\vivado.bat']); + elseif isunix + hdlsetuptoolpath('ToolName', 'Xilinx Vivado', ... + 'ToolPath', ['/opt/Xilinx/Vivado/',vivado,'/bin/vivado']); + end + + end + end + + methods(Test) + function buildHDLFrequencyHopper(testCase) + cd(fullfile(testCase.root,'targeting_models/frequency-hopping')); + hdlworkflow; + if ~isempty(out) + disp(out.message); + end + % Check for BOOT.BIN + if exist('hdl_prj/vivado_ip_prj/boot/BOOT.BIN', 'file') ~= 2 + error('BOOT.BIN Failed'); + end + end + function buildKernelFrequencyHopper(testCase) + cd(fullfile(testCase.root,'targeting_models/frequency-hopping')); + system('chmod +x build_kernel.sh'); + system('./build_kernel.sh'); + % Check for uImage + if exist('linux/arch/arm/boot/uImage', 'file') ~= 2 + error('Kernel Build Failed'); + end + end + end + +end diff --git a/test/runDemoTests.m b/test/runDemoTests.m new file mode 100644 index 0000000..afd5387 --- /dev/null +++ b/test/runDemoTests.m @@ -0,0 +1,35 @@ +import matlab.unittest.TestRunner; +import matlab.unittest.TestSuite; +import matlab.unittest.plugins.TestReportPlugin; +import matlab.unittest.plugins.XMLPlugin +import matlab.unittest.plugins.DiagnosticsValidationPlugin + +try + suite = testsuite({'DemoTests'}); + + runner = matlab.unittest.TestRunner.withTextOutput('OutputDetail',1); + runner.addPlugin(DiagnosticsValidationPlugin) + + xmlFile = 'BSPDemoTests.xml'; + plugin = XMLPlugin.producingJUnitFormat(xmlFile); + runner.addPlugin(plugin); + + results = runner.run(suite); + + t = table(results); + disp(t); + disp(repmat('#',1,80)); + for test = results + if test.Failed + disp(test.Name); + end + end +catch e + disp(getReport(e,'extended')); + bdclose('all'); + exit(1); +end + +save(['BSPInstallerTest_',datestr(now,'dd_mm_yyyy-HH:MM:SS'),'.mat'],'t'); +bdclose('all'); +exit(any([results.Failed]));