diff --git a/CI/scripts/matlab_processors.tcl b/CI/scripts/matlab_processors.tcl
index 6a9208c3..c2812e4b 100644
--- a/CI/scripts/matlab_processors.tcl
+++ b/CI/scripts/matlab_processors.tcl
@@ -206,11 +206,13 @@ proc preprocess_bd {project carrier rxtx} {
                 delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_5]
                 delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_6]
                 delete_bd_objs [get_bd_nets util_ad9361_dac_upack_fifo_rd_data_7]
-            }            
+            }
+			# set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect] 
             # Add 1 extra AXI master ports to the interconnect
             set_property -dict [list CONFIG.NUM_MI {11}] [get_bd_cells axi_cpu_interconnect]
             connect_bd_net -net [get_bd_nets util_ad9361_divclk_clk_out] [get_bd_pins axi_cpu_interconnect/M10_ACLK] [get_bd_pins util_ad9361_divclk/clk_out]
             connect_bd_net [get_bd_pins util_ad9361_divclk_reset/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M10_ARESETN]
+			#connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins util_ad9361_divclk/clk_out]
         }
         pluto {
             if {$rxtx == "rx" || $rxtx == "rxtx"} {
@@ -299,18 +301,18 @@ proc preprocess_bd {project carrier rxtx} {
                     # RX ONLY
                     # IPCORE_RESETN ->     adrv9009_rx_device_clk_rstgen/peripheral_aresetn
                     # AXI4_LITE_ARESETN -> adrv9009_rx_device_clk_rstgen/peripheral_aresetn
-                    # M16_RESET -> adrv9009_rx_device_clk_rstgen/peripheral_aresetn
+					set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect] # M16_RESET -> adrv9009_rx_device_clk_rstgen/peripheral_aresetn
                     # M16 -> rx_clkgen/clk_0
 
                     # Add 1 extra AXI master ports to the interconnect
 					set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect]
-                    set_property -dict [list CONFIG.NUM_MI {17}] [get_bd_cells axi_cpu_interconnect]
                     #connect_bd_net [get_bd_pins axi_cpu_interconnect/M16_ARESETN] [get_bd_pins sys_rstgen/peripheral_aresetn]
                     #connect_bd_net -net [get_bd_nets axi_adrv9009_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M16_ACLK] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0]
                     #connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M16_ARESETN]
 
                     if {$rxtx == "rx" || $rxtx == "rxtx"} {
-						connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins util_adrv9009_xcvr/rx_out_clk_0]
+						set_property -dict [list CONFIG.NUM_MI {17}] [get_bd_cells axi_cpu_interconnect]
+						connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0]
                     }
                     if {$rxtx == "tx" || $rxtx == "rxtx"} {
                         # Remove valid combiner
@@ -319,6 +321,7 @@ proc preprocess_bd {project carrier rxtx} {
                     if {$rxtx == "rxtx"} {
                         # Map all TX clocks to RX
                         delete_bd_objs [get_bd_nets adrv9009_tx_device_clk]
+						connect_bd_net [get_bd_pins axi_adrv9009_tx_jesd/link_clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0]
 
                         connect_bd_net [get_bd_pins axi_adrv9009_tx_jesd/device_clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0]
                         connect_bd_net [get_bd_pins util_adrv9009_tx_upack/clk] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0]
@@ -332,7 +335,7 @@ proc preprocess_bd {project carrier rxtx} {
                         connect_bd_net [get_bd_pins util_adrv9009_xcvr/tx_clk_3] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0]
                     }
                     if {$rxtx == "tx"} {
-                        connect_bd_net [get_bd_pins axi_cpu_interconnect/M16_ACLK] [get_bd_pins axi_adrv9009_tx_clkgen/clk_0]
+                        # connect_bd_net [get_bd_pins axi_cpu_interconnect/M16_ACLK] [get_bd_pins axi_adrv9009_tx_clkgen/clk_0]
                     }
                 }
             }
@@ -355,14 +358,16 @@ proc preprocess_bd {project carrier rxtx} {
             }
             switch $carrier {
                 zcu102 {
+					set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect] 
                     # Add 1 extra AXI master ports to the interconnect
                     set_property -dict [list CONFIG.NUM_MI {14}] [get_bd_cells axi_cpu_interconnect]
-                    connect_bd_net [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins sys_ps8/pl_clk0]
-                    connect_bd_net [get_bd_pins axi_cpu_interconnect/M13_ARESETN] [get_bd_pins sys_rstgen/peripheral_aresetn]
+                    #connect_bd_net [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins sys_ps8/pl_clk0]
+                    #connect_bd_net [get_bd_pins axi_cpu_interconnect/M13_ARESETN] [get_bd_pins sys_rstgen/peripheral_aresetn]
                     
                     if {$rxtx == "rx" || $rxtx == "rxtx"} {
                         # connect_bd_net [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins core_clk_d]
                         # connect_bd_net [get_bd_pins core_clk_d_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M13_ARESETN]
+						connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0]
                     }
                     if {$rxtx == "tx" || $rxtx == "rxtx"} {
                         # Remove valid combiner
@@ -391,13 +396,15 @@ proc preprocess_bd {project carrier rxtx} {
                 delete_bd_objs [get_bd_nets util_dac_1_upack_fifo_rd_data_2]
                 delete_bd_objs [get_bd_nets util_dac_1_upack_fifo_rd_data_3]
             }
-            switch $carrier {                
-                zcu102 {                    
+            switch $carrier {
+                zcu102 {
+					set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect] 
                     # Add 1 extra AXI master ports to the interconnect
-					set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect]
                     set_property -dict [list CONFIG.NUM_MI {7}] [get_bd_cells axi_cpu_interconnect]
                     # Connect clock and reset
-					connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins sys_ps8/pl_clk0]
+					connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_adrv9001/adc_1_clk]
+                    # connect_bd_net [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins sys_ps8/pl_clk0]
+                    # connect_bd_net [get_bd_pins axi_cpu_interconnect/M06_ARESETN] [get_bd_pins sys_rstgen/peripheral_aresetn]
                 }                
             }
         }
@@ -441,34 +448,42 @@ proc preprocess_bd {project carrier rxtx} {
                 connect_bd_net [get_bd_pins ad9371_tx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
                 connect_bd_net [get_bd_pins axi_ad9371_dacfifo/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
                 connect_bd_net [get_bd_pins tx_ad9371_tpl_core/link_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+				connect_bd_net [get_bd_pins axi_ad9371_tx_jesd/link_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
             }
             switch $carrier {
                 zc706 {
+					set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect] 
                     # Add 1 extra AXI master ports to the interconnect
                     set_property -dict [list CONFIG.NUM_MI {22}] [get_bd_cells axi_cpu_interconnect]
                     #connect_bd_net -net [get_bd_nets axi_adrv9009_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0]
                     connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M21_ARESETN]
 
                     if {$rxtx == "rx" || $rxtx == "rxtx"} {
-                        connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M21_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+						connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+                        #connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M21_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
                     }
                     if {$rxtx == "tx"} {
-                        connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_interconnect/M21_ACLK] [get_bd_pins axi_ad9371_tx_clkgen/clk_0]
+						connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_ad9371_tx_clkgen/clk_0]
+                        #connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_interconnect/M21_ACLK] [get_bd_pins axi_ad9371_tx_clkgen/clk_0]
                     }
                 }
                 zcu102 {
+					set_property -dict [list CONFIG.NUM_CLKS {2}] [get_bd_cells axi_cpu_interconnect]
+					# connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
                     # Add 1 extra AXI master ports to the interconnect
                     set_property -dict [list CONFIG.NUM_MI {17}] [get_bd_cells axi_cpu_interconnect]
                     #connect_bd_net -net [get_bd_nets axi_adrv9009_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M16_ACLK] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0]
-                    connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M16_ARESETN]
+                    # connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M16_ARESETN]
                     
                     if {$rxtx == "rx" || $rxtx == "rxtx"} {
-                        connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M16_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+						connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+                        #connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M16_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
                     }                    
                     if {$rxtx == "tx"} {
+						connect_bd_net [get_bd_pins axi_cpu_interconnect/aclk1] [get_bd_pins axi_ad9371_tx_clkgen/clk_0]
                         # Remove valid combiner
-                        delete_bd_objs [get_bd_nets tx_fir_interpolator_valid_out_0] [get_bd_nets tx_fir_interpolator_valid_out_2] [get_bd_nets logic_or_Res] [get_bd_cells logic_or]
-                        connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_interconnect/M16_ACLK] [get_bd_pins axi_ad9371_tx_clkgen/clk_0]
+                        # delete_bd_objs [get_bd_nets tx_fir_interpolator_valid_out_0] [get_bd_nets tx_fir_interpolator_valid_out_2] [get_bd_nets logic_or_Res] [get_bd_cells logic_or]
+                        # connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_interconnect/M16_ACLK] [get_bd_pins axi_ad9371_tx_clkgen/clk_0]
                     }                    
                 }
             }
diff --git a/test/board_variants.m b/test/board_variants.m
index f62b8e8e..a8c81a39 100644
--- a/test/board_variants.m
+++ b/test/board_variants.m
@@ -7,7 +7,6 @@
 %    and contains a board definition file
 
 r = { ...
-	%{
     'AnalogDevices.adrv9002.zcu102.plugin_rd_rx', ...
     'AnalogDevices.adrv9002.zcu102.plugin_rd_rxtx', ...
     'AnalogDevices.adrv9002.zcu102.plugin_rd_tx', ...
@@ -17,9 +16,7 @@
     'AnalogDevices.adrv9009.zc706.plugin_rd_tx', ...
     ...
     'AnalogDevices.adrv9009.zcu102.plugin_rd_rx', ...
-	%}
     'AnalogDevices.adrv9009.zcu102.plugin_rd_rxtx', ...
-	%{
     'AnalogDevices.adrv9009.zcu102.plugin_rd_tx', ...
     ...
     'AnalogDevices.fmcomms8.zcu102.plugin_rd_rx', ...
@@ -80,7 +77,6 @@
     'AnalogDevices.pluto.plugin_rd_rx', ...
     'AnalogDevices.pluto.plugin_rd_rxtx', ...
     'AnalogDevices.pluto.plugin_rd_tx', ...
-	%}
     };
 end
 % LocalWords:  Zynq ZC