diff --git a/docs/learning/index.rst b/docs/learning/index.rst
index 011d1fd42..52bdda46e 100644
--- a/docs/learning/index.rst
+++ b/docs/learning/index.rst
@@ -56,6 +56,14 @@ Workshops
workshop_what_sw_for_sdr/index
+
+.. toctree::
+ :caption: A Precision Converter FPGA Integration Journey
+ :maxdepth: 1
+
+ workshop_a_precision_converter_fpga_integration_journey/index
+
+
Academic Workshops
-------------------------------------------------------------------------------
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diff --git a/docs/learning/workshop_a_precision_converter_fpga_integration_journey/index.rst b/docs/learning/workshop_a_precision_converter_fpga_integration_journey/index.rst
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+A Precision Converter FPGA Integration Journey
+==============================================
+
+This workshop goes through the whole stack for the integration of a precision
+converter using an FPGA.
+
+Introduction
+------------
+
+**Customer Journey**
+
+.. figure:: intro_customer_journey_1.png
+ :align: center
+
+Tools / Platforms are a customer choice, ADI ports to "current" development
+environment/kit.
+
+.. figure:: intro_customer_journey_2.png
+ :align: center
+
+Maintenance is an ADI burden. Customer don't start their designs at the same
+time, and want to use the latest and greatest.
+
+**COS Reference Design "Donut Hole" Strategy**
+
+*Surround others processor, FPGA, micro ADI components*
+*Reference design creates stickiness*
+*Customer experiences low friction*
+*Leverage ecosystems*
+*Develop/participate in viable communities / ecosystems:*
+
+- Linux kernel (1.3 Billion users)
+- GitHub (40 Million users)
+- Python (100 Million users)
+- MATLAB (1 Million users)
+
+.. figure:: intro_donut.png
+ :width: 500
+ :align: center
+
+**COS Full Stack High Level Overview**
+
+.. figure:: intro_full_stack_overview.png
+ :align: center
+
+**COS Full Stack HDL Designs**
+
+*Common HDL across all IIO reference designs*
+
+*Full stack reference Designs include JESD204 physical layers (XCVR), link layers, and transport layers.*
+
+- Termination to DMA via an AXI-STREAM or FIFO interface
+- Runs across different Intel and Xilinx carriers
+
+*Are designed to be disconnected to "insert custom signal processing"*
+
+- Your modem, your signals intelligence, etc.
+
+*Example designs show how to use MUX in different places in design, to stream debug data (I/Q samples, or payload (data buffers)) as IIO streams.*
+
+*Works with industry standard debug tools:*
+
+- Xilinx Integrated Logic Analyzer
+- Intel Signal Tap
+- MathWorks HDL Verifier (in SoC Blockset)
+
+.. figure:: ad9081_204b_M4L8.svg
+ :align: center
+
+**COS Typical Prototyping System**
+
+.. figure:: intro_typical_system.png
+ :align: center
+
+**COS IP Library**
+
+.. figure:: intro_ip_library.png
+ :align: center
+
+**COS Frameworks - JESD204 Interface Framework**
+
+*JESD204 Layers:*
+
+- Physical – FPGA specific (GTXE2, GTHE3, GTHE4, GTY4, GTY5, Arria 10, Stratix 10)
+- Data Link – GPL 2 and commercial license
+- Transport – ADC/DAC/Transceiver specific
+
+*The Framework includes:*
+
+- Evaluation boards
+- HDL
+- Software
+
+.. figure:: jesd204_chain.svg
+ :align: center
+
+**COS Frameworks - SPI Engine Framework**
+
+========================= ===
+COS HDL projects %
+========================= ===
+JESD PROJECTS 34%
+SPI ENGINE PROJECTS 21%
+CUSTOM INTERFACE PROJECTS 45%
+========================= ===
+
+SPI Engine supports 21.5% of the HLD projects.
+
+.. figure:: intro_spie.svg
+ :align: center
+
+SPI Engine Architecture
+-----------------------
+
+**Serial Peripheral Interface**
+
+A full-duplex serial communication bus design by Motorola in mid 1980s, used
+in short distance chip to chip communication, primarily in embedded systems.
+It becomes a 'de facto' standard, with small variations depending on the use
+case and application.
+
+.. figure:: spi_master_slave.png
+ :align: center
+
+SCLK – Serial Clock from master
+MOSI – Master Output Slave Input
+MISO – Master Input Slave Output
+CSN – Chip Select N (active low)
+
+======== ==== ====
+SPI MODE CPOL CPHA
+======== ==== ====
+0 0 0
+1 0 1
+2 1 0
+3 1 1
+======== ==== ====
+
+.. figure:: spi_modes_2.png
+ :align: center
+
+**Why the MCU SPI controller isn't enough?**
+
+*Physical layer challenges:*
+
+- Almost every ADI chip has a 3-wire SPI (but this is not a big issue)
+- CS can have other functionalities too (e.g., conversion start)
+- Other status or control lines can co-exist (BUSY/CNV)
+- Multiple MOSI line can co-exist
+- SCLK frequency limited to ~50MHz (higher frequency support is rear)
+- Fixed timing relationship of the interface lines
+- No possibility to synchronize the interface with other signals
+- Limited number of MISO lines
+- No DDR support
+
+*All the SPI controllers are fully software driven:*
+
+- Can not support low latency transfers
+- Can not support high throughput periodic transfers (capture or send a stream of data)
+- Non-deterministic (e.g., time between spi_read function call and the actual SPI transfer is undefined)
+
+**SPI transfers timing diagram – AD4020**
+
+.. figure:: spi_transfer_diagram_ad4020.png
+ :align: center
+
+**SPI transfers timing diagram – AD4630**
+
+.. figure:: spi_transfer_diagram_ad4630.png
+ :align: center
+
+**SPI Engine Framework – What it is?**
+
+SPI Engine is a highly flexible and powerful SPI controller open-source
+framework. It consists out of multiple submodules which communicate over
+well-defined interfaces. This allows a high degree of flexibility and
+re-usability while at the same time staying highly customizable and easily
+extensible.
+
+*Some of the SPI Engine Framework features are:*
+
+- HDL IP supporting the two major FPGA vendors (AMD Xilinx and Intel)
+- Software API integrated into the Linux kernel's SPI framework
+- Bare-metal software API
+- Examples with various devices (device drivers that leverage the framework)
+
+**SPI Engine Framework – HDL Architecture**
+
+.. figure:: spie_framework.svg
+ :align: center
+
+*Command Stream Generator (CSG)*
+
+- Software driven (controlled through a register map)
+- Hardware driven (MISO or MOSI data offload)
+- Generate a predefined command sequence periodically or synchronously
+
+*Command Stream Executor (CSE)*
+
+- Parse an incoming command stream and drive the physical pins on the interface
+- Can be a standard parser or a custom parser (e.g. custom SDI latching)
+
+*Command Stream Interconnect (CSI)*
+
+- Arbitrates multiple streams from multiple CSGs to a single CSE
+
+**SPI Engine Framework – AXI SPI Engine IP**
+
+- Memory mapped access to command stream interface
+- Fully software controlled CSG
+
+- Memory mapped access to offload control interface
+- Allow dynamic reconfiguration of offload block
+
+- SPI clock and AXI clock can be asynchronous
+
+.. figure:: spie_axi_spi_engine_ip.png
+ :align: center
+
+**SPI Engine Framework – Data Offload IP**
+
+- Internal RAM/ROM for CMD and SDO stream
+- A trigger launches a command stream
+- Received data is sent to an AXI4-streaming interface
+- It can be connected directly to a DMA
+
+.. figure:: spie_offload_ip.png
+ :align: center
+
+**SPI Engine Framework – Interconnect IP**
+
+- Arbitrates multiple command streams into a single CSE
+- Arbitration is done at an SPI transaction level (a SYNC instruction must be
+ used for end of transaction)
+- Lower slave port always take precedence
+
+.. figure:: spie_interconnect_ip.png
+ :align: center
+
+**SPI Engine Framework – Execution IP**
+
+- Accepts commands on the control interface
+- Generates low-level SPI signals on the SPI interface
+- Active signal indicates if the block is busy processing commands
+
+.. figure:: spie_execution_ip.png
+ :align: center
+
+**SPI Engine Framework – Command Stream Interfaces**
+
+*4 AXI-Stream interfaces*
+
+- CMD: Instructions
+- SDO: SPI write data (MOSI)
+- SDI: SPI read data (MISO)
+- SYNC: Synchronization events
+
+*Each streams follows standard AXI-Stream handshaking*
+
+- Only the main AXI-stream signals are used (ready, valid, data)
+
+**SPI Engine Framework – Software support**
+
+- Introduces the concept of SPI offload
+- Moves certain operations typically performed by the application processor to the SPI controller
+- Interrupt offload capability
+- Data offload capability
+- SPI-Engine is one implementation of SPI offload
+- ADI converter drivers can be used with any offload capable SPI controller
+
+**Build prerequisites – HDL repository**
+
+.. figure:: build_prerequisites_hdl.png
+ :align: center
+
+**Build prerequisites – Linux repository**
+
+.. figure:: build_prerequisites_linux.png
+ :align: center
+
+.. figure:: build_prerequisites_clone.png
+ :align: center
+
+Use Case
+--------
+
+**What is the use case?**
+
+.. figure:: use_case_examples.png
+ :align: center
+
+*Requirements:*
+
+- Highest sampling rate possible with low jitter in sample acquisition
+- Maximum SNR
+- Minimum THD
+- Minimize processor usage for data acquisition and processing
+
+.. figure:: use_case_typical_app.png
+ :align: center
+
+.. figure:: use_case_snr.png
+ :align: center
+
+.. figure:: use_case_jitter.png
+ :align: center
+
+============================ ====================== =====================
+Test conditions Regular SPI controller SPI Engine controller
+============================ ====================== =====================
+Resolution[bits] 16 18
+Sampling rate[KSPS] 15 15 and 1330
+Input signal frequency[kHz] 1 1
+Input signal amplitude[dBFS] -0.5 -0.5
+Supply voltage [V] -2.5 and 5 -2.5 and 5
+============================ ====================== =====================
+
+**Features of the AD7984 converter**
+
+- High performance
+- Throughput: 1.33 MSPS
+- True differential analog input range: ±VREF
+- 0 V to VREF with VREF between 2.9 V to 5 V
+- Zero latency architecture
+- 18-bit resolution with no missing codes
+- Dynamic range: 99.7 dB, VREF = 5 V
+- SNR: 98.5 dB at fIN = 1 kHz, VREF = 5 V
+- THD: −110.5 dB at fIN = 1 kHz, VREF = 5 V
+- SINAD: 97.5 dB at fIN = 1 kHz, VREF = 5 V
+
+**AD7984 SPI transfer Timing Diagram**
+
+.. figure:: use_case_ad7984_transfer_diagram.png
+ :align: center
+
+**Timing parameters needed to configure the framework**
+
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| Device | Resolution | Sample rate | T_SPI_SCLK min | T_CONV max | T_CYC min | T_ACQ min |
+| | [bits] | [KSPS] | [ns] | [ns] | [ns] | [ns] |
++================+==============+================+==================+================+================+================+
+| AD7942 | 14 | 250 | 18 | 2200 | 4000 | 1800 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7946 | 14 | 500 | 15 | 1600 | 2000 | 400 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7988-1 | 16 | 100 | 12 | 9500 | 1000 | 500 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7685 | 16 | 250 | 15 | 2200 | 4000 | 1800 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7687 | 16 | 250 | 10 | 2200 | 4000 | 1800 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7691 | 16 | 250 | 15 | 2200 | 4000 | 1800 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7686 | 16 | 500 | 15 | 1600 | 2000 | 400 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7693 | 16 | 500 | 15 | 1600 | 2000 | 400 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7988-5(B) | 16 | 500 | 12 | 1600 | 2000 | 400 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7988-5(C) | 16 | 500 | 12 | 1200 | 2000 | 800 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7980 | 16 | 1000 | 10 | 710 | 1000 | 290 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7983 | 16 | 1333 | 12 | 500 | 750 | 250 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7982 | 18 | 1000 | 12 | 710 | 1000 | 290 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| AD7982 | 18 | 1000 | 12 | 710 | 1000 | 290 |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+| **AD7984** | **18** | **1333** | **12** | **500** | **750** | **250** |
++----------------+--------------+----------------+------------------+----------------+----------------+----------------+
+
+**HDL design block diagram**
+
+.. figure:: use_case_hdl_bd.svg
+ :align: center
+
+**HDL Framework instantiation**
+
+- TCL Function header:
+
+.. code-block:: tcl
+
+ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {sdi_delay 0} {echo_sclk 0}}
+
+- Instantiation example for PulSAR ADC:
+
+.. code-block:: tcl
+
+ source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl4
+ set data_width32
+ set async_spi_clk1
+ set num_cs1
+ set num_sdi1
+ set sdi_delay1
+ set hier_spi_enginespi_pulsar_adc
+ spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $sdi_delay
+
+
+#. DATA_WIDTH - will set the width of the data bus / data line used by the SPI
+Engine to connect tothe DMA. It will also set the maximum word length for the
+SPI transfer. Since the Pulsar_ADC devices are all single SDI/SDO and some of
+them require 18bit transfers, this value will be rounded to 32bit.
+
+#. ASYNC_SPI_CLK - will chose the reference clock for the SPI Engine. Setting
+this to 0 will configure the hierarchy to use the axi clock (100MHz) as the
+reference clock. Setting it to 1 will allow for an external reference clock
+(SPI_CLK).
+
+#. NUM_CS - selects the number of CS lines.
+
+#. NUM_SDI - selects the number of SDI lines.
+
+#. SDI_DELAY - the latch of the SDI line can be delayed with 1, 2 or 3 SPI core
+clock cycle. Needed for designs with high SCLK rate (>50MHz).
+
+**PulSAR ADC Architecture**
+
+.. figure:: use_case_pulsar_arch.png
+ :align: center
+
+*ADI AXI PWM GENERATOR*
+
+- ad_ip_parameter pulsar_adc_trigger_gen CONFIG.PULSE_0_PERIOD 120
+- ad_ip_parameter pulsar_adc_trigger_gen CONFIG.PULSE_0_WIDTH 1
+- ad_connect spi_clk pulsar_adc_trigger_gen/ext_clk
+- ad_connect pulsar_adc_trigger_gen/pwm_0 $hier_spi_engine/offload/trigger
+
+*AXI CLKGEN*
+
+- ad_ip_instance axi_clkgen spi_clkgen
+- ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
+- ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
+- ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
+- ad_connect $hier_spi_engine/m_spi pulsar_adc_spi
+- ad_connect spi_clk spi_clkgen/clk_0
+- ad_connect spi_clk spi_pulsar_adc/spi_clk
+
+*ADI AXI DMA CONTROLLER*
+
+- ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_TYPE_SRC 1
+- ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_TYPE_DEST 0
+- ad_ip_parameter axi_pulsar_adc_dma CONFIG.CYCLIC 0
+- ad_ip_parameter axi_pulsar_adc_dma CONFIG.SYNC_TRANSFER_START 0
+- ad_ip_parameter axi_pulsar_adc_dma CONFIG.AXI_SLICE_SRC 0
+- ad_ip_parameter axi_pulsar_adc_dma CONFIG.AXI_SLICE_DEST 1
+- ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_2D_TRANSFER 0
+- ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 32
+- ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_DATA_WIDTH _DEST 64
+- ad_connect spi_clk axi_pulsar_adc_dma/s_axis_aclk
+
+**Debug options – ILA**
+
+.. figure:: use_case_debug_options_ila.png
+ :align: center
+
+**Debug options – regular SPI controller transfer capture**
+
+.. figure:: use_case_debug_options_spi.png
+ :align: center
+
+**Debug options –SPI Engine controller transfer capture**
+
+.. figure:: use_case_debug_options_spie.png
+ :align: center
+
+Build System
+------------
+
+.. figure:: system_build_bd.png
+ :align: center
+
+**System Build - ADALM2000**
+
+.. figure:: system_build_m2k.png
+ :align: center
+
+- Two programmable power supplies
+- Two-channel USB digital oscilloscope
+- Two-channel arbitrary function generator
+- 16-channel digital logic analyzer (3.3V CMOS and 1.8V or 5V tolerant, 100MS/s)
+
+**System Build - Scopy**
+
+.. figure:: system_build_scopy.png
+ :align: center
+
+Uses the ADALM2000 to implement virtual instruments:
+
+- Oscilloscope (with Mixed Signal Capability)
+- Signal Generator (Functions and Arbitrary)
+- Spectrum Analyzer
+- Network Analyzer
+- Voltmeter
+- Power Supply
+- Logic Analyzer (with Stack Decoder support)
+- Digital Pattern Generator
+- GPIO
+
+**System Build - Schematic**
+
+.. figure:: system_build_schematic.png
+ :align: center
+
+**System Build - Cora Z7S Configuration**
+
+.. figure:: system_build_cora.png
+ :align: center
+
+**System Build - Power Supply**
+
+.. figure:: system_build_power_supply.png
+ :align: center
+
+**System Build - Input Signal**
+
+.. figure:: system_build_input_signal.png
+ :align: center
+
+**System Build - UART Configuration**
+
+.. figure:: system_build_uart.png
+ :align: center
+
+**System Build – change host IP**
+
+.. figure:: system_build_ip.png
+ :align: center
+
+**System Build - UART and Ethernet Testing**
+
+Step 1 - using Putty
+
+.. shell::
+ :caption: ifconfig
+ :user: root
+
+ $ifconfig
+ eth0: flags=4163 mtu 1500
+ inet 169.254.92.202 netmask 255.255.255.0 broadcast 10.48.65.255
+ inet6 fe80::241:8f:d3d0:e43b prefixlen 64 scopeid 0x20
+ ether 0e:23:90:e3:61:01 txqueuelen 1000 (Ethernet)
+ RX packets 483757 bytes 81480222 (77.7 MiB)
+ RX errors 0 dropped 0 overruns 0 frame 0
+ TX packets 5562 bytes 775511 (757.3 KiB)
+ TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
+ device interrupt 38
+
+ lo: flags=73 mtu 65536
+ inet 127.0.0.1 netmask 255.0.0.0
+ inet6 ::1 prefixlen 128 scopeid 0x10
+ loop txqueuelen 1000 (Local Loopback)
+ RX packets 83 bytes 10176 (9.9 KiB)
+ RX errors 0 dropped 0 overruns 0 frame 0
+ TX packets 83 bytes 10176 (9.9 KiB)
+ TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
+
+Step 2 - using Cygwin
+
+.. shell::
+ :caption: ping 169.254.92.202
+
+ $ping 169.254.92.202
+
+ Pinging 169.254.92.202 with 32 bytes of data:
+ Reply from 169.254.92.202: bytes=32 time=2ms TTL=64
+ Reply from 169.254.92.202: bytes=32 time=1ms TTL=64
+ Reply from 169.254.92.202: bytes=32 time=1ms TTL=64
+ Reply from 169.254.92.202: bytes=32 time=1ms TTL=64
+
+ Ping statistics for 169.254.92.202:
+ Packets: Sent = 4, Received = 4, Lost = 0 (0% loss),
+ Approximate round trip times in milli-seconds:
+ Minimum = 1ms, Maximum = 2ms, Average = 1ms
+
+Evaluate System
+---------------
+
+**System Evaluation – regular SPI trigger configuration**
+
+.. figure:: system_evaluation_spi_trigger_1.png
+ :align: center
+
+.. figure:: system_evaluation_spi_trigger_2.png
+ :align: center
+
+**System Evaluation**
+
+=========================================================== ====================== =====================
+Steps Regular SPI controller SPI Engine controller
+=========================================================== ====================== =====================
+Connect IIO Oscilloscope and visualize the captured signals
+Run the Python script on `Cora Z7S`_ / Cygwin
+Analyze results in VisualAnalog
+Compare the results
+=========================================================== ====================== =====================
+
+**System Evaluation - IIO Oscilloscope**
+
+.. figure:: system_evaluation_iio_osc_1.png
+ :align: center
+
+.. figure:: system_evaluation_iio_osc_2.png
+ :align: center
+
+**System Evaluation - Logic Analyzer**
+
+.. figure:: system_evaluation_m2k_1.png
+ :align: center
+
+.. figure:: system_evaluation_m2k_2.png
+ :align: center
+
+**System Evaluation**
+
+=========================================================== ====================== =====================
+Steps Regular SPI controller SPI Engine controller
+=========================================================== ====================== =====================
+Connect IIO Oscilloscope and visualize the captured signals X
+Run the Python script on `Cora Z7S`_ / Cygwin
+Analyze results in VisualAnalog
+Compare the results
+=========================================================== ====================== =====================
+
+**System Evaluation - Python script**
+
+.. figure:: system_evaluation_spi_python_script.png
+ :align: center
+
+**System Evaluation – Python from the FPGA board**
+
+.. figure:: system_evaluation_spi_python_from_fpga_1.png
+ :align: center
+
+.. figure:: system_evaluation_spi_python_from_fpga_2.png
+ :align: center
+
+**System Evaluation – Python from a remote machine - optional**
+
+.. figure:: system_evaluation_spi_python_from_remote_1.png
+ :align: center
+
+.. figure:: system_evaluation_spi_python_from_remote_2.png
+ :align: center
+
+.. figure:: system_evaluation_spi_python_from_remote_3.png
+ :align: center
+
+**System Evaluation**
+
+=========================================================== ====================== =====================
+Steps Regular SPI controller SPI Engine controller
+=========================================================== ====================== =====================
+Connect IIO Oscilloscope and visualize the captured signals X
+Run the Python script on `Cora Z7S`_ / Cygwin X
+Analyze results in VisualAnalog
+Compare the results
+=========================================================== ====================== =====================
+
+**System Evaluation - IIO Oscilloscope**
+
+.. figure:: system_evaluation_cora_and_iio_osc.png
+ :align: center
+
+**System Evaluation**
+
+=========================================================== ====================== =====================
+Steps Regular SPI controller SPI Engine controller
+=========================================================== ====================== =====================
+Connect IIO Oscilloscope and visualize the captured signals X X
+Run the Python script on `Cora Z7S`_ / Cygwin X
+Analyze results in VisualAnalog
+Compare the results
+=========================================================== ====================== =====================
+
+**System Evaluation – Python from the FPGA board**
+
+.. shell::
+ :caption: cd /boot/
+
+ $cd /cygdrive/c/work/fae_workshop_workspace
+
+.. figure:: system_evaluation_spie_python_from_fpga_1.png
+ :align: center
+
+.. figure:: system_evaluation_spie_python_from_fpga_2.png
+ :align: center
+
+**System Evaluation – Python from a remote machine - optional**
+
+.. figure:: system_evaluation_spie_python_from_remote_1.png
+ :align: center
+
+.. figure:: system_evaluation_spie_python_from_remote_2.png
+ :align: center
+
+.. figure:: system_evaluation_spie_python_from_remote_3.png
+ :align: center
+
+**System Evaluation**
+
+=========================================================== ====================== =====================
+Steps Regular SPI controller SPI Engine controller
+=========================================================== ====================== =====================
+Connect IIO Oscilloscope and visualize the captured signals X X
+Run the Python script on `Cora Z7S`_ / Cygwin X X
+Analyze results in VisualAnalog
+Compare the results
+=========================================================== ====================== =====================
+
+.. shell::
+ :caption: cd /cygdrive/c/work/fae_workshop_workspace
+
+ $cd /cygdrive/c/work/fae_workshop_workspace
+
+.. shell::
+ :caption: scp root@169.254.92.202L/boot/workshop/fae_workshop_visual.vac .
+
+ $scp root@169.254.92.202L/boot/workshop/fae_workshop_visual.vac .
+ root@169.254.92.202's password:analog
+ fae_worksop_visual.vac 100% 17KB 1.7MB/s 00:00
+
+.. figure:: system_evaluation_analyse_results.png
+ :align: center
+
+**System Evaluation–Analyze results (SPI Engine-1.3MSPS)**
+
+.. figure:: system_evaluation_analyse_results_spie_1m3.png
+ :align: center
+
+**System Evaluation–Analyze results (Regular SPI -15KSPS)**
+
+.. figure:: system_evaluation_analyse_results_spi_1k5.png
+ :align: center
+
+**System Evaluation–Analyze results (SPI Engine-15KSPS)**
+
+.. figure:: system_evaluation_analyse_results_spie_1k5.png
+ :align: center
+
+**System Evaluation**
+
+=========================================================== ====================== =====================
+Steps Regular SPI controller SPI Engine controller
+=========================================================== ====================== =====================
+Connect IIO Oscilloscope and visualize the captured signals X X
+Run the Python script on `Cora Z7S`_ / Cygwin X X
+Analyze results in VisualAnalog X X
+Compare the results
+=========================================================== ====================== =====================
+
+**System Evaluation – Results comparison**
+
+=========================================== ========= ================================== ================================== ====================================
+Parameter Datasheet Regular SPI controller SPI Engine controller SPI Engine controller
+ (Fin=1kHz, SR=15KHz, Ain=-0.5dBFS) (Fin=1kHz, SR=15KHz, Ain=-0.5dBFS) (Fin=1kHz, SR=1.33MHz, Ain=-0.5dBFS)
+=========================================== ========= ================================== ================================== ====================================
+Signal-to-Noise SNR [dBFS] 98.5 14.81 78.60 77.70
+Spurious-Free Dynamic Range SFDR [dBFS] 112.5 21.13 92.97 99.15
+Total Harmonic Distortion THD [dBFS] -110.5 -45.65 -99.20 -110
+Signal-to-(Noise + Distortion) SINAD [dBFS] 98 14.30 78 77.20
+=========================================== ========= ================================== ================================== ====================================
+
+**System Evaluation**
+
+=========================================================== ====================== =====================
+Steps Regular SPI controller SPI Engine controller
+=========================================================== ====================== =====================
+Connect IIO Oscilloscope and visualize the captured signals X X
+Run the Python script on `Cora Z7S`_ / Cygwin X X
+Analyze results in VisualAnalog X X
+Compare the results X X
+=========================================================== ====================== =====================
+
+Conclusions
+-----------
+
+#. A classic MCU can be used for converters that have the sampling rate up to
+ 100kSPS.
+#. Maximum performance, in terms of sampling rate, SNR, THD can be only
+ achieved with an FPGA.
+#. SPI Engine is a highly flexible and powerful open-source SPI controller
+ framework which can interface a wide range of precision converters.
+#. We are now familiar with the COS group open-source solution stack.
+
+**Thank You!**
+
+**Related Presentations**
+
+- My customer uses an FPGA in his product. Now what?
+- ADALM2000 in real life applications
+- Just enough Software and HDL for High-Speed designs
+- Hardware and Software Tools for Precision Wideband Instrumentation
+
+**Questions?**
+:ez:`community/university-program`
+
+.. _Cora Z7S: https://digilent.com/shop/cora-z7-zynq-7000-single-core-for-arm-fpga-soc-development
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diff --git a/docs/linux/kernel/index.rst b/docs/linux/kernel/index.rst
index 5c005d66a..4fe9cc901 100644
--- a/docs/linux/kernel/index.rst
+++ b/docs/linux/kernel/index.rst
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.. _linux-kernel:
Kernel and devicetrees
-""""""""""""""""""""""
-
-.. toctree::
- :hidden:
-
- petalinux
+======================
This section provides a concise guide on building the Linux kernel and
devicetrees for different platforms on different hosts.
Jump to your platform and preferred method:
-.. contents::
- :depth: 2
- :local:
-
-Building the Zynq Linux kernel and devicetrees from source
-==========================================================
-
-Using a script
---------------
-
-We provide
-:git-wiki-scripts:`a script `
-that does automates the build for Zynq using the Linaro toolchain.
-
-The script takes up to 3 parameters, but if left blank, it uses defaults:
-
-#. **** - default is **linux-adi** if left blank ; use this,
- if you want to use an already cloned kernel repo
-#. **** - which device tree should be exported/copied from the
- build. Default is ``zynq-zc702-adv7511-ad9361-fmcomms2-3.dtb`` for Zynq
-#. **** - in case you have your own preferred toolchain
- (other than Linaro's or Xilinx's) you can use override it with this 3rd param
-
-The script will:
-
-* Clone the ADI kernel tree
-* Download the Linaro GCC toolchain (if no other is specified)
-* Build the ADI kernel tree
-* Export/copy the Image file and device tree file out of the kernel build folder
-
-Running the script in one line, with defaults:
-
-.. shell::
-
- $wget https://raw.githubusercontent.com/analogdevicesinc/wiki-scripts/main/linux/build_zynq_kernel_image.sh && \
- $chmod +x build_zynq_kernel_image.sh && \
- $./build_zynq_kernel_image.sh
-
-Building with Petalinux
------------------------
-
-Please see here: :ref:`linux-kernel petalinux`.
-
-On the development host
------------------------
-
-Make sure you have ``u-boot-tools`` installed, to have the ``mkimage`` utility
-available. You can install it via your distro's package manager.
-
-Then
-
-.. shell::
-
- $git clone https://github.com/analogdevicesinc/linux.git \
- $ --no-single-branch --depth=10 \
- $ -- linux
-
-or do a git pull in a existing cloned repository.
-
-The ``depth`` and ``no-single-branch`` options are included to speed up the
-cloning by fetching only near the head of each branch/release, you may remove
-them to fetch all history, but bear in mind it will go from around 800MB to
-around 3.4GB and growing.
-
-Checkout the Release branch
-~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-.. tip::
-
- Use the latest release, if not required otherwise!
-
-.. list-table::
- :header-rows: 1
-
- - - Release names and Branches
- - - 2014_R2
- - - 2015_R2
- - - 2016_R1
- - - 2016_R2
- - - 2017_R1
- - - 2018_R1
- - - 2018_R2
- - - 2019_R1
- - - 2019_R2
- - - 2021_R1
-
-.. shell::
-
- $git checkout origin/2021_R1 -b 2021_R1
- Branch 2021_R1 set up to track remote branch 2021_R1 from origin.
- Switched to a new branch '2021_R1'
-
-Setup cross compile environment variables
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-There are a few toolchains that can be used. The Xilinx toolchain is
-recommended, but the Linaro toolchain can also be used.
-
-Other toolchains/compilers for ARM may work as well, but the ones described here
-have been tested and found to work.
-
-Using the Xilinx toolchain
-^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. list-table::
- :header-rows: 1
-
- - - Release names and Branches
- - Required Vivado/Vitis versions
- - - 2014_R2
- - Vivado 2014.2
- - - 2015_R2
- - Vivado 2015.2
- - - 2016_R1
- - Vivado 2015.4.2
- - - 2016_R2
- - Vivado 2016.2
- - - 2017_R1
- - Vivado 2016.4
- - - 2018_R1
- - Vivado 2017.4
- - - 2018_R2
- - Vivado 2018.2
- - - 2019_R1
- - Vivado 2018.3
- - - 2019_R2
- - Vivado 2019.1
- - - 2021_R1
- - Vivado 2021.1
-
-.. shell::
-
- $source $PATH_TO_XILINX/Vitis/$VITIS_VERSION/settings64.sh
- $which which arm-linux-gnueabihf-gcc
- $PATH_TO_XILINX/Vitis/$VITIS_VERSION/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin/arm-linux-gnueabihf-gcc
-
-.. important::
-
- Find the path to the Xilinx installation folder, and then use
- it to replace this string: **$PATH_TO_XILINX** that is written above.
- Same goes for the **$VITIS_VERSION**, where you choose the Vitis version.
-
-.. shell::
-
- $export ARCH=arm
- $export CROSS_COMPILE="arm-linux-gnueabihf-"
-
-Using the Linaro toolchain
-^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Alternatively, the Linaro toolchain/compiler can be used to compile to kernel.
-Linaro compilers (that work with Zynq) can be downloaded from
-`here `__.
-Always use the latest release just in case.
-
-.. shell::
-
- $wget https://releases.linaro.org/components/toolchain/binaries/latest-7/arm-linux-gnueabi/gcc-linaro-7.5.0-2019.12-x86_64_arm-linux-gnueabi.tar.xz
- $tar -xvf gcc-linaro-7.5.0-2019.12-x86_64_arm-linux-gnueabi.tar.xz
-
-.. shell::
-
- $export ARCH=arm
- $export CROSS_COMPILE=$(pwd)/gcc-linaro-7.5.0-2019.12-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-
-
-Configure the kernel
-~~~~~~~~~~~~~~~~~~~~
-
-Inside the repository, generate the configuration file before building the
-kernel tree.
-The command shown below is generic and is not project specific.
-As long as the board is a ZYNQ FPGA, use the configuration below.
-
-.. shell::
-
- $make zynq_xcomm_adv7511_defconfig
- #
- # configuration written to .config
- #
-
-Build the kernel
-~~~~~~~~~~~~~~~~
-
-Build the kernel via 'make'. This is the same for all Xilinx ZYNQ FPGAs.
-
-.. shell::
-
- $make -j5 UIMAGE_LOADADDR=0x8000 uImage
- scripts/kconfig/conf --silentoldconfig Kconfig
- CHK include/config/kernel.release
- CHK include/generated/uapi/linux/version.h
- UPD include/config/kernel.release
- CHK include/generated/utsrelease.h
-
- [ -- snip --]
-
- AS arch/arm/boot/compressed/bswapsdi2.o
- AS arch/arm/boot/compressed/piggy.gzip.o
- LD arch/arm/boot/compressed/vmlinux
- OBJCOPY arch/arm/boot/zImage
- Kernel: arch/arm/boot/zImage is ready
- UIMAGE arch/arm/boot/uImage
- Image Name: Linux-3.17.0-126697-g611e217-dir
- Created: Fri Nov 28 10:20:40 2014
- Image Type: ARM Linux Kernel Image (uncompressed)
- Data Size: 3195872 Bytes = 3120.97 kB = 3.05 MB
- Load Address: 00008000
- Entry Point: 00008000
-
-Build the devicetree FCMOMMS2/3/4/5
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-Build the one that fits your FPGA carrier and FMC card
-
-.. list-table::
- :header-rows: 1
-
- - - device tree
- - board
- - chip
- - - zynq-adrv9361-z7035-bob
- - :adi:`ADRV1CRR-BOB`
- - | :adi:`ADRV9361`
- - - zynq-adrv9361-z7035-bob-cmos
- - :adi:`ADRV1CRR-BOB`
- - | :adi:`ADRV9361`
- - - zynq-adrv9361-z7035-packrf
- - :adi:`ADRV-PACKRF`
- - | :adi:`ADRV9361`
- - - zynq-adrv9361-z7035-fmc
- - :adi:`ADRV1CRR-FMC`
- - | :adi:`ADV7511` (on-board) and the
- | :adi:`ADRV9361`
- - - zynq-adrv9361-z7035-fmc-rfcard-tdd
- - :adi:`ADRV1CRR-FMC`
- - | :adi:`ADV7511` (on-board), the
- | :adi:`ADRV9361` and the
- | :adi:`AD-PZSDR2400TDD-EB`
- - - zynq-adrv9364-z7020-bob
- - :adi:`ADRV1CRR-BOB`
- - | :adi:`ADRV9364`
- - - zynq-adrv9364-z7020-bob-cmos
- - :adi:`ADRV1CRR-BOB`
- - | :adi:`ADRV9364`
- - - zynq-adrv9364-z7020-packrf
- - :adi:`ADRV-PACKRF`
- - | :adi:`ADRV9364`
- - - zynq-coraz7s
- - `Cora Z7`_
- - |
- - - zynq-mini-itx-adv7511
- - `Mini-ITX`_
- - | :adi:`ADV7511` (on-board)
- - - zynq-mini-itx-adv7511-ad9361-fmcomms2-3
- - `Mini-ITX`_
- - | :adi:`ADV7511` (on-board)
- | :dokuwiki:`AD-FMCOMMS2-EBZ `
- | :dokuwiki:`AD-FMCOMMS3-EBZ `
- - - zynq-mini-itx-adv7511-ad9364-fmcomms4
- - `Mini-ITX`_
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCOMMS4-EBZ ` board
- - - zynq-zc702-adv7511
- - :xilinx:`ZC702`
- - | :adi:`ADV7511` (on-board)
- - - zynq-zc702-adv7511-ad9361-fmcomms2-3
- - :xilinx:`ZC702`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCOMMS2-EBZ ` or
- | :dokuwiki:`AD-FMCOMMS3-EBZ ` board
- - - zynq-zc702-adv7511-ad9361-fmcomms5
- - :xilinx:`ZC702`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCOMMS5-EBZ `
- - - zynq-zc702-adv7511-ad9364-fmcomms4
- - :xilinx:`ZC702`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCOMMS4-EBZ ` board
- - - zynq-zc706-adv7511
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board)
- - - zynq-zc706-adv7511-ad6676-fmc
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD6676-FMC-EBZ ` board
- - - zynq-zc706-adv7511-ad9265-fmc-125ebz
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD9265-FMC-125EBZ ` board
- - - zynq-zc706-adv7511-ad9361-fmcomms2-3
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCOMMS2-EBZ ` or
- | :dokuwiki:`AD-FMCOMMS3-EBZ ` board
- - - zynq-zc706-adv7511-ad9361-fmcomms5
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCOMMS5-EBZ ` board
- - - zynq-zc706-adv7511-ad9361-fmcomms5-ext-lo-adf5355
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCOMMS5-EBZ ` board
- - - zynq-zc706-adv7511-ad9364-fmcomms4
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCOMMS4-EBZ ` board
- - - zynq-zc706-adv7511-ad9434-fmc-500ebz
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD9434-FMC-500EBZ ` board
- - - zynq-zc706-adv7511-ad9625-fmcadc2
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCADC2-EBZ ` board
- - - zynq-zc706-adv7511-ad9739a-fmc
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :adi:`EVAL-AD9739A`
- - - zynq-zc706-adv7511-adrv9371
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`ADRV9371 ` board
- - - zynq-zc706-adv7511-adrv9375
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`ADRV9375 ` board
- - - zynq-zc706-adv7511-fmcadc4
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCADC4-EBZ ` board
- - - zynq-zc706-adv7511-fmcdaq2
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCDAQ2-EBZ ` board
- - - zynq-zc706-adv7511-fmcdaq3
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCDAQ3-EBZ ` board
- - - zynq-zc706-adv7511-fmcjesdadc1
- - :xilinx:`ZC706`
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCJESDADC1-EBZ ` board
- - - zynq-zc706-imageon
- - :xilinx:`ZC706`
- - | FMC-IMAGEON
- - - zynq-zed-adv7511
- - `Zed Board `__
- - :adi:`ADV7511` (on-board)
- - - zynq-zed-adv7511-ad9361-fmcomms2-3
- - `Zed Board `__
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCOMMS2-EBZ ` or
- | :dokuwiki:`AD-FMCOMMS3-EBZ ` board
- - - zynq-zed-adv7511-ad9364-fmcomms4
- - `ZedBoard`_
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD-FMCOMMS4-EBZ ` board
- - - zynq-zed-adv7511-ad9467-fmc-250ebz
- - `ZedBoard`_
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`AD9467-FMC-250EBZ ` board
- - - zynq-zed-adv7511-cn0363
- - `ZedBoard`_
- - | :adi:`ADV7511` (on-board) and the
- | :dokuwiki:`EVAL-CN0363-PMDZ ` board
- - - zynq-zed-imageon
- - `ZedBoard`_
- - | FMC-IMAGEON
-
-.. _ZedBoard: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard
-.. _Mini-ITX: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/mini-itx
-.. _Cora Z7: https://digilent.com/reference/programmable-logic/cora-z7/start
-
-Building the device tree uses 'make' by turning the .dts file to a .dtb. The
-command is simply 'make' plus the device tree name with a .dtb file extension.
-
-.. shell::
-
- $make zynq-zc702-adv7511-ad9361.dtb
- DTC arch/arm/boot/dts/zynq-zc702-adv7511-ad9361.dtb
-
-Copy the generated files to your SD Card
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The output files for building the kernel and device tree are **uImage** and
-**.dtb**. Refer to the code below to find their respective
-output directories. Take note that the device tree file needs to be renamed to
-**devicetree.dtb**.
-See :ref:`kuiper sdcard` for more information in configuring the SD card.
-
-.. shell::
-
- $cp arch/arm/boot/uImage /media/BOOT/uImage
- $cp arch/arm/boot/dts/zynq-zc702-adv7511-ad9361.dtb /media/BOOT/devicetree.dtb
-
-On the target platform (devicetrees)
-------------------------------------
-
-To modify devicetrees on the target platform:
-
-#. Make sure the boot partition is mounted. On new images, this can be done by
- right-clicking the boot icon on the desktop and selecting the "Mount Volume"
- option. The partition will then be mounted at */media/analog/boot*.
-
-#. Convert the compiled devicetree related to the target back into an editable
- format.
-
- .. shell::
-
- $cd /media/analog/boot/zynq-zc702-adv7511
- $dtc -I dtb -O dts -o devicetree.dts devicetree.dtb
-
-
-#. Modify the devicetree.dts file as required.
-
-#. Recompile the devicetree file. Note that this will overwrite the original dtb
- file, copy or rename the original file if you want to keep it before running
- this step.
-
- .. shell::
-
- $cd /media/analog/boot/zynq-zc702-adv7511
- $dtc -I dts -O dtb -o devicetree.dtb devicetree.dts
-
-
-Building the ZynqMP / MPSoC Linux kernel and devicetrees from source
-====================================================================
-
-Using a script
---------------
-
-We provide
-:git-wiki-scripts:`a script `
-that does automates the build for Zynq using the Linaro toolchain.
-
-.. attention::
-
- This script differs from the one for Zynq.
-
-The script takes up to 3 parameters, but if left blank, it uses defaults:
-
-#. **** - default is **linux-adi** if left blank ; use this,
- if you want to use an already cloned kernel repo
-#. **** - which device tree should be exported/copied from the
- build. Default is ``xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dtb`` for
- ZynqMP
-#. **** - in case you have your own preferred toolchain
- (other than Linaro's or Xilinx's) you can use override it with this 3rd param
-
-The script will:
-
-* Clone the ADI kernel tree
-* Download the Linaro GCC toolchain (if no other is specified)
-* Build the ADI kernel tree
-* Export/copy the Image file and device tree file out of the kernel build folder
-
-Running the script in one line, with defaults:
-
-.. shell::
-
- $wget https://raw.githubusercontent.com/analogdevicesinc/wiki-scripts/main/linux/build_zynqmp_kernel_image.sh && \
- $ chmod +x build_zynqmp_kernel_image.sh && \
- $ ./build_zynqmp_kernel_image.sh
-
-
-Building with Petalinux
------------------------
-
-Please see here: :ref:`linux-kernel petalinux`.
-
-On the development host
------------------------
-
-Make sure you have ``u-boot-tools`` installed, to have the ``mkimage`` utility
-available. You can install it via your distro's package manager.
-
-Then
-
-.. shell::
-
- $git clone https://github.com/analogdevicesinc/linux.git \
- $ --no-single-branch --depth=10 \
- $ -- linux
-
-or do a git pull in a existing cloned repository.
-
-The ``depth`` and ``no-single-branch`` options are included to speed up the
-cloning by fetching only near the head of each branch/release, you may remove
-them to fetch all history, but bear in mind it will go from around 800MB to
-around 3.4GB and growing.
-
-Checkout the main development
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-.. shell::
-
- $git checkout main
- Already on 'main'
- Your branch is up-to-date with 'origin/main'.
-
-Add aarch64-linux-gnu-gcc to PATH
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-Using the Xilinx toolchain
-^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. shell::
-
- $source $PATH_TO_XILINX/Vitis/$VITIS_VERSION/settings64.sh
- $which aarch64-linux-gnu-gcc
- $PATH_TO_XILINX/Vitis/$VITIS_VERSION/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-gcc
-
-.. important::
-
- Find the path to the Xilinx installation folder, and then use
- it to replace this string: **$PATH_TO_XILINX** that is written above.
- Same goes for the **$VITIS_VERSION**, where you choose the Vitis version.
-
-.. shell::
-
- $export ARCH=arm64
- $export CROSS_COMPILE="aarch64-linux-gnu-"
-
-Using the Linaro toolchain
-^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Alternatively, the Linaro toolchain/compiler can be used to compile to kernel.
-Linaro compilers (that work with ZYNQMP) can be downloaded from
-`here `__.
-Always use the latest release just in case.
-
-.. shell::
-
- $wget https://releases.linaro.org/components/toolchain/binaries/latest-7/aarch64-linux-gnu/gcc-linaro-7.5.0-2019.12-x86_64_aarch64-linux-gnu.tar.xz
- $tar -xvf gcc-linaro-7.5.0-2019.12-x86_64_aarch64-linux-gnu.tar.xz
-
-.. shell::
-
- $export ARCH=arm64
- $export CROSS_COMPILE=$(pwd)/gcc-linaro-7.5.0-2019.12-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
-
-Configure the kernel
-~~~~~~~~~~~~~~~~~~~~
-
-Inside the repository, generate the configuration file before building the
-kernel tree.
-
-.. shell::
-
- $make adi_zynqmp_defconfig
- #
- # configuration written to .config
- #
-
-Build the kernel via 'make'. This is the same for all Xlinx ZYNQMP MPSoC FPGAs.
-
-.. shell::
-
- $make -j5 Image UIMAGE_LOADADDR=0x8000
- CHK include/config/kernel.release
- CHK include/generated/uapi/linux/version.h
- HOSTCC scripts/basic/fixdep
- HOSTCC scripts/basic/bin2c
-
- [ -- snip --]
-
- CC init/version.o
- LD init/built-in.o
- KSYM .tmp_kallsyms1.o
- KSYM .tmp_kallsyms2.o
- LD vmlinux
- SORTEX vmlinux
- SYSMAP System.map
- OBJCOPY arch/arm64/boot/Image
-
-Build the devicetree FCMOMMS2/3
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-Build the one that fits your FPGA carrier and FMC card
-
-.. list-table::
- :header-rows: 1
-
- - - device tree
- - board
- - chip
- - - zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dts
- - :xilinx:`ZCU102` **Rev. 1.0**
- - | :dokuwiki:`AD-FMCOMMS2-EBZ ` or
- | :dokuwiki:`AD-FMCOMMS3-EBZ ` board
- - - zynqmp-zcu102-rev10-ad9364-fmcomms4.dts
- - :xilinx:`ZCU102` **Rev. 1.0**
- - | :dokuwiki:`AD-FMCOMMS4-EBZ ` or
- | :dokuwiki:`AD-FMCOMMS4-EBZ ` board
- - - zynqmp-zcu102-revB-ad9361-fmcomms2-3.dts
- - :xilinx:`ZCU102` Rev.B
- - | :dokuwiki:`AD-FMCOMMS2-EBZ ` or
- | :dokuwiki:`AD-FMCOMMS3-EBZ ` board
- - - zynqmp-zcu102-revB-ad9364-fmcomms4.dts
- - :xilinx:`ZCU102` Rev.B
- - | :dokuwiki:`AD-FMCOMMS4-EBZ ` board
-
-The device tree **zynqmp-zcu102-revA.dts** can also be used for any ZCU102 FPGA
-that uses an SD card for boot up. Building the device tree uses 'make' by
-turning the .dts file to a .dtb. The command is simply 'make' plus the device
-tree name with a .dtb file extension.
-
-.. shell::
-
- $make xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dtb
- DTC arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dtb
-
-Copy the generated files to your SD Card
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The output files for building the kernel and device tree are **uImage** and
-**.dtb**. Refer to the code below to find their respective
-output directories. Take note that the device tree file needs to be renamed to
-**devicetree.dtb**.
-See :ref:`kuiper sdcard` for more information in configuring the SD card.
-
-.. shell::
-
- $cp arch/arm64/boot/Image /media/michael/BOOT/
- $cp arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB-ad9361-fmcomms2-3.dtb /media/michael/BOOT/system.dtb
-
-Common Issues
--------------
-
-This sections goes through common issues related to the Linux Kernel on the
-ZynqMP.
-
-DisplayPort - no picture?
-~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The default configuration for most of the projects is to use the HDMI output,
-and that is what the configuration is set up for.
+.. toctree::
+ :maxdepth: 2
-For DisplayPort projects, you may need to add a custom ``xorg.conf`` file.
+ Build Zynq
+ Build ZynqMP
+ Build MicroBlaze
-.. code:: bash
+The :git-linux:`/` can also be compiled using Petalinux to be used on Xilinx
+SoC FPGA based platforms.
- printf 'Section "Device"
- Identifier "myfb"
- Driver "fbdev"
- Option "fbdev" "/dev/fb0"
- EndSection' > /etc/X11/xorg.conf
+.. toctree::
+ :titlesonly:
-After following that, the board should be rebooted.
+ petalinux
-You can find a list with tested monitors
-:xilinx:`here `.
-Resolution or image problems may appear if there is used a monitor that was not
-tested.
diff --git a/docs/linux/kernel/microblaze.rst b/docs/linux/kernel/microblaze.rst
new file mode 100644
index 000000000..d49b3fc44
--- /dev/null
+++ b/docs/linux/kernel/microblaze.rst
@@ -0,0 +1,207 @@
+.. _linux-kernel microblaze:
+
+Build MicroBlaze Linux kernel
+=============================
+
+On the development host
+-----------------------
+
+This guide provides some step-by-step instructions on how to build a Microblaze
+Linux Kernel image for the FMC board connected to a:
+
+* :xilinx:`KC705`
+* :xilinx:`KCU105`
+* :xilinx:`VC707`
+* :xilinx:`VCU118`
+* :xilinx:`VCU128`
+
+The :git-linux:`/` contains the Linux Kernel flavor from Analog Devices Inc.
+:download:`rootfs.cpio.gz `
+contains the files system to be used.
+As the compiler, the Microblaze GNU Tools are bumbled on both
+:xilinx:`AMD Vivado ` and
+:xilinx:`AMD Vivis `, as well
+as the ``xsdb`` tool for booting.
+
+After ensuring all tools are installed, clone the :git-linux:`/`
+
+.. shell::
+
+ $git clone https://github.com/analogdevicesinc/linux.git \
+ $ --no-single-branch --depth=10 \
+ $ -- linux
+
+The ``depth`` and ``no-single-branch`` options are included to speed up the
+cloning by fetching only near the head of each branch/release, you may remove
+them to fetch all history, but bear in mind it will go from around 800 MB to
+around 3.4GB and growing.
+
+Checkout the Release branch
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. tip::
+
+ Use the latest release, if not required otherwise!
+
+The release branches have the format ``_R[1|2]``, starting from ``2014_R2``.
+
+.. shell::
+
+ $git checkout origin/2021_R1 -b 2021_R1
+ Branch 2021_R1 set up to track remote branch 2021_R1 from origin.
+ Switched to a new branch '2021_R1'
+
+Setup cross compile environment variables
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The Microblaze GNU Toolchain bumbled in AMD Vivado/Xilinx is the recommended
+compiler.
+
+/data/opt/Xilinx/Vitis/$XVERSION/gnu/microblaze/linux_toolchain/lin64_le/bin/
+
+.. shell::
+
+ $XVERSION=2024.2
+ $GCC_MICROBLAZE=$PATH_TO_XILINX/Vits/$VITIS_VERSION/gnu/microblaze/linux_toolchain/lin64_le/bin/
+ $export ARCH=microblaze
+ $export CROSS_COMPILE="$GCC_MICROBLAZE/microblazeel-xilinx-linux-gnu-"
+
+.. important::
+
+ Find the path to the Xilinx installation folder, and then use
+ it to replace this string: **$PATH_TO_XILINX** that is written above.
+ Same goes for the **$VITIS_VERSION**, where you choose the Vitis version.
+ Alternatively, you can replace Vitis with Vivado.
+
+Compile the kernel
+~~~~~~~~~~~~~~~~~~
+
+Prepare the configuration:
+
+.. shell::
+
+ ~/linux
+ $make adi_mb_defconfig
+ #
+ # configuration written to .config
+ #
+
+Download the rootfs:
+
+.. shell::
+
+ ~/linux
+ $wget https://swdownloads.analog.com/cse/microblaze/rootfs/rootfs.cpio.gz
+ Saving to: ‘rootfs.cpio.gz’
+ rootfs.cpio.gz 100%[======================>] 4.74M 6.39MB/s in 0.7s
+ 2025-05-28 11:00:09 (6.39 MB/s) - ‘rootfs.cpio.gz’ saved [4970267/4970267]
+
+
+The result of building the kernel is an elf file in *arch/microblaze/boot* named
+`simpleImage.` based on the dts specified.
+
+The build process for the kernel searches in the *arch/microblaze/boot/dts*
+directory for a specified device tree file and then builds the device tree into
+the kernel image.
+
+The following command shows the general format for the build target name. Note
+that the ** does not include the file extension *.dts*.
+
+.. shell::
+
+ ~/linux
+ $make simpleImage.
+
+To see what device-trees for the different FPGA carrier and FMC module combination exist type:
+
+.. shell::
+
+ ~/linux
+ $ls -l arch/microblaze/boot/dts
+
+So, for example, for *vcu118_quad_ad9081_204c_txmode_23_rxmode_25_onchip_pll_revc_nz1.dts*:
+
+.. shell::
+
+ ~/linux
+ $make simpleImage.vcu118_quad_ad9081_204c_txmode_23_rxmode_25_onchip_pll_revc_nz1
+ SYNC include/config/auto.conf.cmd
+ CC scripts/mod/empty.o
+ CC scripts/mod/devicetable-offsets.s
+ MKELF scripts/mod/elfconfig.h
+ HOSTCC scripts/mod/modpost.o
+ HOSTCC scripts/mod/sumversion.o
+ HOSTCC scripts/mod/file2alias.o
+
+ [ --snip-- ]
+
+ AR init/built-in.a
+ LD vmlinux.o
+ MODPOST vmlinux.symvers
+ MODINFO modules.builtin.modinfo
+ GEN modules.builtin
+ LD .tmp_vmlinux.kallsyms1
+ KSYMS .tmp_vmlinux.kallsyms1.S
+ AS .tmp_vmlinux.kallsyms1.S
+ LD .tmp_vmlinux.kallsyms2
+ KSYMS .tmp_vmlinux.kallsyms2.S
+ AS .tmp_vmlinux.kallsyms2.S
+ LD vmlinux
+ SORTTAB vmlinux
+ SYSMAP System.map
+ OBJCOPY arch/microblaze/boot/simpleImage.vcu118_quad_ad9081_204c_txmode_23_rxmode_25_onchip_pll_revc_nz1
+ SHIPPED arch/microblaze/boot/simpleImage.vcu118_quad_ad9081_204c_txmode_23_rxmode_25_onchip_pll_revc_nz1.unstrip
+ STRIP vmlinux arch/microblaze/boot/simpleImage.vcu118_quad_ad9081_204c_txmode_23_rxmode_25_onchip_pll_revc_nz1.strip
+ UIMAGE arch/microblaze/boot/simpleImage.vcu118_quad_ad9081_204c_txmode_23_rxmode_25_onchip_pll_revc_nz1.ub
+ Image Name: Linux-5.10.0-97916-g513446e488c3
+ Created: Tue Jan 18 12:07:35 2022
+ Image Type: MicroBlaze Linux Kernel Image (uncompressed)
+ Data Size: 18398124 Bytes = 17966.92 KiB = 17.55 MiB
+ Load Address: 80000000
+ Entry Point: 80000000
+ Kernel: arch/microblaze/boot/simpleImage.vcu118_quad_ad9081_204c_txmode_23_rxmode_25_onchip_pll_revc_nz1 is ready (#3678)
+
+The STRIP image (*.strip*) found under *arch/microblaze/boot* is the ELF image
+to load via the debugger.
+
+Boot on FPGA MicroBlaze
+~~~~~~~~~~~~~~~~~~~~~~~
+
+One method to load the kernel onto the already built and running FPGA which has
+the MicroBlaze processor is to use ``xsdb``/``xsct`` or ``xmd`` from the AMD
+Xilinx Vivado/Vitis toolset to download the build *.strip* file.
+
+Go to the folder containing the *.strip* and *system_top.bit* file, to flash the
+bitstream and download the Image.
+
+.. note::
+
+ The **system_top.bit** is obtained from the HDL project.
+ Learn how to :external+hdl:ref:`build_hdl`, but instead of using the generated
+ **\*.sdk/system_top.xsa**, use the **\*.runs/impl_1/system_top.bit**.
+
+With ``xsdb``/``xsct``:
+
+::
+
+ xsdb> connect
+ xsdb> fpga -f system_top.bit
+ xsdb> targets
+ 1 xcku040
+ 2 MicroBlaze Debug Module at USER2
+ 3 MicroBlaze #0 (Running)
+ xsdb> targets 3
+ xsdb> dow simpleImage.kcu105_fmcdaq2
+ xsdb> con
+ xsdb> disconnect
+
+To automate, the same commands can be added to a *.tcl* script and run with ``xsdb run.tcl``.
+
+With ``xmd``:
+
+::
+
+ xmd> fpga -f system_top.bit
+ xmd> connect mb mdm
+ xmd> dow simpleImage.vc707_fmcomms2-3
+ xmd> run
diff --git a/docs/linux/kernel/petalinux.rst b/docs/linux/kernel/petalinux.rst
index a0c8d91ef..491c2f1ca 100644
--- a/docs/linux/kernel/petalinux.rst
+++ b/docs/linux/kernel/petalinux.rst
@@ -1,7 +1,7 @@
.. _linux-kernel petalinux:
-Building with Petalinux
-=======================
+Build with Petalinux
+====================
The ADI Linux kernel can also be compiled using Petalinux to be used on Xilinx
SoC FPGA based platforms (using :git-meta-adi:`ADI Yocto ` repository).
diff --git a/docs/linux/kernel/zynq.rst b/docs/linux/kernel/zynq.rst
new file mode 100644
index 000000000..c343f8188
--- /dev/null
+++ b/docs/linux/kernel/zynq.rst
@@ -0,0 +1,409 @@
+.. _linux-kernel zynq:
+
+Build Zynq Linux kernel and devicetree
+======================================
+
+Using a script
+--------------
+
+We provide
+:git-wiki-scripts:`a script `
+that does automates the build for Zynq using the Linaro toolchain.
+
+The script takes up to 3 parameters, but if left blank, it uses defaults:
+
+#. **** - default is **linux-adi** if left blank ; use this,
+ if you want to use an already cloned kernel repo
+#. **** - which device tree should be exported/copied from the
+ build. Default is ``zynq-zc702-adv7511-ad9361-fmcomms2-3.dtb`` for Zynq
+#. **** - in case you have your own preferred toolchain
+ (other than Linaro's or Xilinx's) you can use override it with this 3rd param
+
+The script will:
+
+* Clone the ADI kernel tree
+* Download the Linaro GCC toolchain (if no other is specified)
+* Build the ADI kernel tree
+* Export/copy the Image file and device tree file out of the kernel build folder
+
+Running the script in one line, with defaults:
+
+.. shell::
+
+ $wget https://raw.githubusercontent.com/analogdevicesinc/wiki-scripts/main/linux/build_zynq_kernel_image.sh && \
+ $chmod +x build_zynq_kernel_image.sh && \
+ $./build_zynq_kernel_image.sh
+
+Building with Petalinux
+-----------------------
+
+Please see here: :ref:`linux-kernel petalinux`.
+
+On the development host
+-----------------------
+
+Make sure you have ``u-boot-tools`` installed, to have the ``mkimage`` utility
+available. You can install it via your distro's package manager.
+
+Then
+
+.. shell::
+
+ $git clone https://github.com/analogdevicesinc/linux.git \
+ $ --no-single-branch --depth=10 \
+ $ -- linux
+
+or do a git pull in a existing cloned repository.
+
+The ``depth`` and ``no-single-branch`` options are included to speed up the
+cloning by fetching only near the head of each branch/release, you may remove
+them to fetch all history, but bear in mind it will go from around 800MB to
+around 3.4GB and growing.
+
+Checkout the Release branch
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. tip::
+
+ Use the latest release, if not required otherwise!
+
+The release branches have the format ``_R[1|2]``, starting from ``2014_R2``.
+
+.. shell::
+
+ $git checkout origin/2021_R1 -b 2021_R1
+ Branch 2021_R1 set up to track remote branch 2021_R1 from origin.
+ Switched to a new branch '2021_R1'
+
+Setup cross compile environment variables
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+There are a few toolchains that can be used. The AMD Xilinx toolchain is
+recommended, but the Linaro toolchain can also be used.
+
+Other toolchains/compilers for ARM may work as well, but the ones described here
+have been tested and found to work.
+
+Using the AMD Xilinx toolchain
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. list-table::
+ :header-rows: 1
+
+ - - Release names and Branches
+ - Required Vivado/Vitis versions
+ - - 2014_R2
+ - Vivado 2014.2
+ - - 2015_R2
+ - Vivado 2015.2
+ - - 2016_R1
+ - Vivado 2015.4.2
+ - - 2016_R2
+ - Vivado 2016.2
+ - - 2017_R1
+ - Vivado 2016.4
+ - - 2018_R1
+ - Vivado 2017.4
+ - - 2018_R2
+ - Vivado 2018.2
+ - - 2019_R1
+ - Vivado 2018.3
+ - - 2019_R2
+ - Vivado 2019.1
+ - - 2021_R1
+ - Vivado 2021.1
+
+.. shell::
+
+ $source $PATH_TO_XILINX/Vitis/$VITIS_VERSION/settings64.sh
+ $which which arm-linux-gnueabihf-gcc
+ $PATH_TO_XILINX/Vitis/$VITIS_VERSION/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin/arm-linux-gnueabihf-gcc
+
+.. important::
+
+ Find the path to the Xilinx installation folder, and then use
+ it to replace this string: **$PATH_TO_XILINX** that is written above.
+ Same goes for the **$VITIS_VERSION**, where you choose the Vitis version.
+
+.. shell::
+
+ $export ARCH=arm
+ $export CROSS_COMPILE="arm-linux-gnueabihf-"
+
+Using the Linaro toolchain
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Alternatively, the Linaro toolchain/compiler can be used to compile to kernel.
+Linaro compilers (that work with Zynq) can be downloaded from
+`here `__.
+Always use the latest release just in case.
+
+.. shell::
+
+ $wget https://releases.linaro.org/components/toolchain/binaries/latest-7/arm-linux-gnueabi/gcc-linaro-7.5.0-2019.12-x86_64_arm-linux-gnueabi.tar.xz
+ $tar -xvf gcc-linaro-7.5.0-2019.12-x86_64_arm-linux-gnueabi.tar.xz
+
+.. shell::
+
+ $export ARCH=arm
+ $export CROSS_COMPILE=$(pwd)/gcc-linaro-7.5.0-2019.12-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-
+
+Configure the kernel
+~~~~~~~~~~~~~~~~~~~~
+
+Inside the repository, generate the configuration file before building the
+kernel tree.
+The command shown below is generic and is not project specific.
+As long as the board is a ZYNQ FPGA, use the configuration below.
+
+.. shell::
+
+ $make zynq_xcomm_adv7511_defconfig
+ #
+ # configuration written to .config
+ #
+
+Build the kernel
+~~~~~~~~~~~~~~~~
+
+Build the kernel via 'make'. This is the same for all AMD Xilinx ZYNQ FPGAs.
+
+.. shell::
+
+ $make -j5 UIMAGE_LOADADDR=0x8000 uImage
+ scripts/kconfig/conf --silentoldconfig Kconfig
+ CHK include/config/kernel.release
+ CHK include/generated/uapi/linux/version.h
+ UPD include/config/kernel.release
+ CHK include/generated/utsrelease.h
+
+ [ -- snip --]
+
+ AS arch/arm/boot/compressed/bswapsdi2.o
+ AS arch/arm/boot/compressed/piggy.gzip.o
+ LD arch/arm/boot/compressed/vmlinux
+ OBJCOPY arch/arm/boot/zImage
+ Kernel: arch/arm/boot/zImage is ready
+ UIMAGE arch/arm/boot/uImage
+ Image Name: Linux-3.17.0-126697-g611e217-dir
+ Created: Fri Nov 28 10:20:40 2014
+ Image Type: ARM Linux Kernel Image (uncompressed)
+ Data Size: 3195872 Bytes = 3120.97 kB = 3.05 MB
+ Load Address: 00008000
+ Entry Point: 00008000
+
+Build the devicetree FCMOMMS2/3/4/5
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Build the one that fits your FPGA carrier and FMC card
+
+.. list-table::
+ :header-rows: 1
+
+ - - device tree
+ - board
+ - chip
+ - - zynq-adrv9361-z7035-bob
+ - :adi:`ADRV1CRR-BOB`
+ - | :adi:`ADRV9361`
+ - - zynq-adrv9361-z7035-bob-cmos
+ - :adi:`ADRV1CRR-BOB`
+ - | :adi:`ADRV9361`
+ - - zynq-adrv9361-z7035-packrf
+ - :adi:`ADRV-PACKRF`
+ - | :adi:`ADRV9361`
+ - - zynq-adrv9361-z7035-fmc
+ - :adi:`ADRV1CRR-FMC`
+ - | :adi:`ADV7511` (on-board) and the
+ | :adi:`ADRV9361`
+ - - zynq-adrv9361-z7035-fmc-rfcard-tdd
+ - :adi:`ADRV1CRR-FMC`
+ - | :adi:`ADV7511` (on-board), the
+ | :adi:`ADRV9361` and the
+ | :adi:`AD-PZSDR2400TDD-EB`
+ - - zynq-adrv9364-z7020-bob
+ - :adi:`ADRV1CRR-BOB`
+ - | :adi:`ADRV9364`
+ - - zynq-adrv9364-z7020-bob-cmos
+ - :adi:`ADRV1CRR-BOB`
+ - | :adi:`ADRV9364`
+ - - zynq-adrv9364-z7020-packrf
+ - :adi:`ADRV-PACKRF`
+ - | :adi:`ADRV9364`
+ - - zynq-coraz7s
+ - `Cora Z7`_
+ - |
+ - - zynq-mini-itx-adv7511
+ - `Mini-ITX`_
+ - | :adi:`ADV7511` (on-board)
+ - - zynq-mini-itx-adv7511-ad9361-fmcomms2-3
+ - `Mini-ITX`_
+ - | :adi:`ADV7511` (on-board)
+ | :dokuwiki:`AD-FMCOMMS2-EBZ `
+ | :dokuwiki:`AD-FMCOMMS3-EBZ `
+ - - zynq-mini-itx-adv7511-ad9364-fmcomms4
+ - `Mini-ITX`_
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCOMMS4-EBZ ` board
+ - - zynq-zc702-adv7511
+ - :xilinx:`ZC702`
+ - | :adi:`ADV7511` (on-board)
+ - - zynq-zc702-adv7511-ad9361-fmcomms2-3
+ - :xilinx:`ZC702`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCOMMS2-EBZ ` or
+ | :dokuwiki:`AD-FMCOMMS3-EBZ ` board
+ - - zynq-zc702-adv7511-ad9361-fmcomms5
+ - :xilinx:`ZC702`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCOMMS5-EBZ `
+ - - zynq-zc702-adv7511-ad9364-fmcomms4
+ - :xilinx:`ZC702`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCOMMS4-EBZ ` board
+ - - zynq-zc706-adv7511
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board)
+ - - zynq-zc706-adv7511-ad6676-fmc
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD6676-FMC-EBZ ` board
+ - - zynq-zc706-adv7511-ad9265-fmc-125ebz
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD9265-FMC-125EBZ ` board
+ - - zynq-zc706-adv7511-ad9361-fmcomms2-3
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCOMMS2-EBZ ` or
+ | :dokuwiki:`AD-FMCOMMS3-EBZ ` board
+ - - zynq-zc706-adv7511-ad9361-fmcomms5
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCOMMS5-EBZ ` board
+ - - zynq-zc706-adv7511-ad9361-fmcomms5-ext-lo-adf5355
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCOMMS5-EBZ ` board
+ - - zynq-zc706-adv7511-ad9364-fmcomms4
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCOMMS4-EBZ ` board
+ - - zynq-zc706-adv7511-ad9434-fmc-500ebz
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD9434-FMC-500EBZ ` board
+ - - zynq-zc706-adv7511-ad9625-fmcadc2
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCADC2-EBZ ` board
+ - - zynq-zc706-adv7511-ad9739a-fmc
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :adi:`EVAL-AD9739A`
+ - - zynq-zc706-adv7511-adrv9371
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`ADRV9371 ` board
+ - - zynq-zc706-adv7511-adrv9375
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`ADRV9375 ` board
+ - - zynq-zc706-adv7511-fmcadc4
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCADC4-EBZ ` board
+ - - zynq-zc706-adv7511-fmcdaq2
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCDAQ2-EBZ ` board
+ - - zynq-zc706-adv7511-fmcdaq3
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCDAQ3-EBZ ` board
+ - - zynq-zc706-adv7511-fmcjesdadc1
+ - :xilinx:`ZC706`
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCJESDADC1-EBZ ` board
+ - - zynq-zc706-imageon
+ - :xilinx:`ZC706`
+ - | FMC-IMAGEON
+ - - zynq-zed-adv7511
+ - `Zed Board `__
+ - :adi:`ADV7511` (on-board)
+ - - zynq-zed-adv7511-ad9361-fmcomms2-3
+ - `Zed Board `__
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCOMMS2-EBZ ` or
+ | :dokuwiki:`AD-FMCOMMS3-EBZ ` board
+ - - zynq-zed-adv7511-ad9364-fmcomms4
+ - `ZedBoard`_
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD-FMCOMMS4-EBZ ` board
+ - - zynq-zed-adv7511-ad9467-fmc-250ebz
+ - `ZedBoard`_
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`AD9467-FMC-250EBZ ` board
+ - - zynq-zed-adv7511-cn0363
+ - `ZedBoard`_
+ - | :adi:`ADV7511` (on-board) and the
+ | :dokuwiki:`EVAL-CN0363-PMDZ ` board
+ - - zynq-zed-imageon
+ - `ZedBoard`_
+ - | FMC-IMAGEON
+
+.. _ZedBoard: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard
+.. _Mini-ITX: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/mini-itx
+.. _Cora Z7: https://digilent.com/reference/programmable-logic/cora-z7/start
+
+Building the device tree uses 'make' by turning the .dts file to a .dtb. The
+command is simply 'make' plus the device tree name with a .dtb file extension.
+
+.. shell::
+
+ $make zynq-zc702-adv7511-ad9361.dtb
+ DTC arch/arm/boot/dts/zynq-zc702-adv7511-ad9361.dtb
+
+Copy the generated files to your SD Card
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The output files for building the kernel and device tree are **uImage** and
+**.dtb**. Refer to the code below to find their respective
+output directories. Take note that the device tree file needs to be renamed to
+**devicetree.dtb**.
+See :ref:`kuiper sdcard` for more information in configuring the SD card.
+
+.. shell::
+
+ $cp arch/arm/boot/uImage /media/BOOT/uImage
+ $cp arch/arm/boot/dts/zynq-zc702-adv7511-ad9361.dtb /media/BOOT/devicetree.dtb
+
+On the target platform (devicetrees)
+------------------------------------
+
+To modify devicetrees on the target platform:
+
+#. Make sure the boot partition is mounted. On new images, this can be done by
+ right-clicking the boot icon on the desktop and selecting the "Mount Volume"
+ option. The partition will then be mounted at */media/analog/boot*.
+
+#. Convert the compiled devicetree related to the target back into an editable
+ format.
+
+ .. shell::
+
+ $cd /media/analog/boot/zynq-zc702-adv7511
+ $dtc -I dtb -O dts -o devicetree.dts devicetree.dtb
+
+
+#. Modify the devicetree.dts file as required.
+
+#. Recompile the devicetree file. Note that this will overwrite the original dtb
+ file, copy or rename the original file if you want to keep it before running
+ this step.
+
+ .. shell::
+
+ $cd /media/analog/boot/zynq-zc702-adv7511
+ $dtc -I dts -O dtb -o devicetree.dtb devicetree.dts
+
diff --git a/docs/linux/kernel/zynqmp.rst b/docs/linux/kernel/zynqmp.rst
new file mode 100644
index 000000000..9c5844742
--- /dev/null
+++ b/docs/linux/kernel/zynqmp.rst
@@ -0,0 +1,239 @@
+.. _linux-kernel zynqmp:
+
+Build ZynqMP / MPSoC Linux kernel and devicetree
+================================================
+
+Using a script
+--------------
+
+We provide
+:git-wiki-scripts:`a script `
+that does automates the build for Zynq using the Linaro toolchain.
+
+.. attention::
+
+ This script differs from the one for Zynq.
+
+The script takes up to 3 parameters, but if left blank, it uses defaults:
+
+#. **** - default is **linux-adi** if left blank ; use this,
+ if you want to use an already cloned kernel repo
+#. **** - which device tree should be exported/copied from the
+ build. Default is ``xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dtb`` for
+ ZynqMP
+#. **** - in case you have your own preferred toolchain
+ (other than Linaro's or AMD Xilinx's) you can use override it with this 3rd paramameter
+
+The script will:
+
+* Clone the ADI kernel tree
+* Download the Linaro GCC toolchain (if no other is specified)
+* Build the ADI kernel tree
+* Export/copy the Image file and device tree file out of the kernel build folder
+
+Running the script in one line, with defaults:
+
+.. shell::
+
+ $wget https://raw.githubusercontent.com/analogdevicesinc/wiki-scripts/main/linux/build_zynqmp_kernel_image.sh && \
+ $ chmod +x build_zynqmp_kernel_image.sh && \
+ $ ./build_zynqmp_kernel_image.sh
+
+
+Building with Petalinux
+-----------------------
+
+Please see here: :ref:`linux-kernel petalinux`.
+
+On the development host
+-----------------------
+
+Make sure you have ``u-boot-tools`` installed, to have the ``mkimage`` utility
+available. You can install it via your distro's package manager.
+
+Then
+
+.. shell::
+
+ $git clone https://github.com/analogdevicesinc/linux.git \
+ $ --no-single-branch --depth=10 \
+ $ -- linux
+
+or do a git pull in a existing cloned repository.
+
+The ``depth`` and ``no-single-branch`` options are included to speed up the
+cloning by fetching only near the head of each branch/release, you may remove
+them to fetch all history, but bear in mind it will go from around 800MB to
+around 3.4GB and growing.
+
+Checkout the Release branch
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. tip::
+
+ Use the latest release, if not required otherwise!
+
+The release branches have the format ``_R[1|2]``, starting from ``2014_R2``.
+
+.. shell::
+
+ $git checkout origin/2021_R1 -b 2021_R1
+ Branch 2021_R1 set up to track remote branch 2021_R1 from origin.
+ Switched to a new branch '2021_R1'
+
+Add aarch64-linux-gnu-gcc to PATH
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Using the Xilinx toolchain
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. shell::
+
+ $source $PATH_TO_XILINX/Vitis/$VITIS_VERSION/settings64.sh
+ $which aarch64-linux-gnu-gcc
+ $PATH_TO_XILINX/Vitis/$VITIS_VERSION/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-gcc
+
+.. important::
+
+ Find the path to the Xilinx installation folder, and then use
+ it to replace this string: **$PATH_TO_XILINX** that is written above.
+ Same goes for the **$VITIS_VERSION**, where you choose the Vitis version.
+
+.. shell::
+
+ $export ARCH=arm64
+ $export CROSS_COMPILE="aarch64-linux-gnu-"
+
+Using the Linaro toolchain
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Alternatively, the Linaro toolchain/compiler can be used to compile to kernel.
+Linaro compilers (that work with ZYNQMP) can be downloaded from
+`here `__.
+Always use the latest release just in case.
+
+.. shell::
+
+ $wget https://releases.linaro.org/components/toolchain/binaries/latest-7/aarch64-linux-gnu/gcc-linaro-7.5.0-2019.12-x86_64_aarch64-linux-gnu.tar.xz
+ $tar -xvf gcc-linaro-7.5.0-2019.12-x86_64_aarch64-linux-gnu.tar.xz
+
+.. shell::
+
+ $export ARCH=arm64
+ $export CROSS_COMPILE=$(pwd)/gcc-linaro-7.5.0-2019.12-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
+
+Configure the kernel
+~~~~~~~~~~~~~~~~~~~~
+
+Inside the repository, generate the configuration file before building the
+kernel tree.
+
+.. shell::
+
+ $make adi_zynqmp_defconfig
+ #
+ # configuration written to .config
+ #
+
+Build the kernel via 'make'. This is the same for all Xlinx ZYNQMP MPSoC FPGAs.
+
+.. shell::
+
+ $make -j5 Image UIMAGE_LOADADDR=0x8000
+ CHK include/config/kernel.release
+ CHK include/generated/uapi/linux/version.h
+ HOSTCC scripts/basic/fixdep
+ HOSTCC scripts/basic/bin2c
+
+ [ -- snip --]
+
+ CC init/version.o
+ LD init/built-in.o
+ KSYM .tmp_kallsyms1.o
+ KSYM .tmp_kallsyms2.o
+ LD vmlinux
+ SORTEX vmlinux
+ SYSMAP System.map
+ OBJCOPY arch/arm64/boot/Image
+
+Build the devicetree FCMOMMS2/3
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Build the one that fits your FPGA carrier and FMC card
+
+.. list-table::
+ :header-rows: 1
+
+ - - device tree
+ - board
+ - chip
+ - - zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dts
+ - :xilinx:`ZCU102` **Rev. 1.0**
+ - | :dokuwiki:`AD-FMCOMMS2-EBZ ` or
+ | :dokuwiki:`AD-FMCOMMS3-EBZ ` board
+ - - zynqmp-zcu102-rev10-ad9364-fmcomms4.dts
+ - :xilinx:`ZCU102` **Rev. 1.0**
+ - | :dokuwiki:`AD-FMCOMMS4-EBZ ` or
+ | :dokuwiki:`AD-FMCOMMS4-EBZ ` board
+ - - zynqmp-zcu102-revB-ad9361-fmcomms2-3.dts
+ - :xilinx:`ZCU102` Rev.B
+ - | :dokuwiki:`AD-FMCOMMS2-EBZ ` or
+ | :dokuwiki:`AD-FMCOMMS3-EBZ ` board
+ - - zynqmp-zcu102-revB-ad9364-fmcomms4.dts
+ - :xilinx:`ZCU102` Rev.B
+ - | :dokuwiki:`AD-FMCOMMS4-EBZ ` board
+
+The device tree **zynqmp-zcu102-revA.dts** can also be used for any ZCU102 FPGA
+that uses an SD card for boot up. Building the device tree uses 'make' by
+turning the .dts file to a .dtb. The command is simply 'make' plus the device
+tree name with a .dtb file extension.
+
+.. shell::
+
+ $make xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dtb
+ DTC arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dtb
+
+Copy the generated files to your SD Card
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The output files for building the kernel and device tree are **uImage** and
+**.dtb**. Refer to the code below to find their respective
+output directories. Take note that the device tree file needs to be renamed to
+**devicetree.dtb**.
+See :ref:`kuiper sdcard` for more information in configuring the SD card.
+
+.. shell::
+
+ $cp arch/arm64/boot/Image /media/michael/BOOT/
+ $cp arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB-ad9361-fmcomms2-3.dtb /media/michael/BOOT/system.dtb
+
+Common Issues
+-------------
+
+This sections goes through common issues related to the Linux Kernel on the
+ZynqMP.
+
+DisplayPort - no picture?
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The default configuration for most of the projects is to use the HDMI output,
+and that is what the configuration is set up for.
+
+For DisplayPort projects, you may need to add a custom ``xorg.conf`` file.
+
+.. code:: bash
+
+ printf 'Section "Device"
+ Identifier "myfb"
+ Driver "fbdev"
+ Option "fbdev" "/dev/fb0"
+ EndSection' > /etc/X11/xorg.conf
+
+After following that, the board should be rebooted.
+
+You can find a list with tested monitors
+:xilinx:`here `.
+Resolution or image problems may appear if there is used a monitor that was not
+tested.
+
+