From bba183a7f0d17ac86eb2c839728294889e0f2254 Mon Sep 17 00:00:00 2001 From: Joyce Velasco Date: Wed, 11 Jun 2025 16:40:01 +0800 Subject: [PATCH 1/3] solutions: reference designs: Added CN0584 pages Signed-off-by: Joyce Velasco --- docs/conf.py | 2 +- .../reference-designs/eval-cn0584-ebz/001.svg | 2971 +++++++++++++ .../eval-cn0584-ebz/CN0584-DesignSupport.zip | 3 + .../HDL-project/cn0585_hdl_diagram.svg | 3867 +++++++++++++++++ .../eval-cn0584-ebz/HDL-project/index.rst | 100 + .../captured_loopback_signal_cn0585.jpg | 3 + .../eval-cn0584-ebz/cn0584.png | 3 + .../cn0584_loopback_connection.png | 3 + .../eval-cn0584-ebz/cn0585_remote_login.jpg | 3 + .../dac_data_management_cn0585.jpg | 3 + .../eval-cn0584-ebz/digital-template/boot.zip | 3 + .../cn0584_loopback_connection.png | 3 + ...igital_template_python_example_scripts.zip | 3 + .../digital_template_simulink_models.zip | 3 + .../digital-template/dt_build_1-2.png | 3 + .../digital-template/dt_build_4-1.png | 3 + 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.../matlab-configuration/figure12.png | 3 + .../matlab-configuration/figure13.png | 3 + .../matlab-configuration/figure14.png | 3 + .../matlab-configuration/figure15.png | 3 + .../matlab-configuration/figure16.png | 3 + .../matlab-configuration/figure17.png | 3 + .../matlab-configuration/figure18.png | 3 + .../matlab-configuration/figure19.png | 3 + .../matlab-configuration/figure20.png | 3 + .../matlab-configuration/figure3.png | 3 + .../matlab-configuration/figure4.png | 3 + .../matlab-configuration/figure5.png | 3 + .../matlab-configuration/figure6.png | 3 + .../matlab-configuration/figure7.png | 3 + .../matlab-configuration/figure8.png | 3 + .../matlab-configuration/figure9.png | 3 + .../matlab-configuration/index.rst | 337 ++ .../sd_card_config_files_revb.zip | 3 + .../matlab-configuration/socblocksetaddon.png | 3 + .../socblocksetsupportpackage.png | 3 + .../matlab-configuration/table1.png | 3 + .../matlab-configuration/table2.png | 3 + .../matlab-configuration/table3.png | 3 + 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docs/solutions/reference-designs/eval-cn0584-ebz/zed_jumpers.jpg diff --git a/docs/conf.py b/docs/conf.py index ae02fc016..170330021 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -6,7 +6,7 @@ repository = 'documentation' project = 'System Level Documentation' -copyright = '2024, Analog Devices, Inc.' +copyright = '2025, Analog Devices, Inc.' author = 'Analog Devices, Inc.' # -- General configuration --------------------------------------------------- diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/001.svg b/docs/solutions/reference-designs/eval-cn0584-ebz/001.svg new file mode 100644 index 000000000..fb891bad3 --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/001.svg @@ -0,0 +1,2971 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/docs/solutions/reference-designs/eval-cn0584-ebz/HDL-project/cn0585_hdl_diagram.svg @@ -0,0 +1,3867 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + + MEMORY INTERCONNECT + Zed + + + FMC CONNECTOR + + + + + DAC_DMA + ADC_CPACK + ADC_DMA + (15/60MHz) + + + + + ARM (Zynq) + Zynq SoC + + + + + AD3552R CORE + CS + 4xSDIO + SCLK + + + + + + + + + AD3552R_IF + AXI REGMAP + + + + + + + + + AXI PWMGEN + AXI CLKGEN + 100MHz + 120MHz + + + + LVDS INTERFACE + + + DAC core frame + + + DAC core frame + + + DAC core frame + + + DAC core frame + + LTC2387 CORE + + + + DA + + + + + DCO + + + + + DB + + CLK_GATE + CNV + LTC_CLK + RX_CLK_P + RX_CLK_N + pwm_0 + pwm_1 + pwm_2 + pwm_3 + + + + + + PNMONITORING + + + + + + + + + + + + 100MHz + 120MHz + + + + + + + + + + + + + + ADC + RAMP + DDS + DMA + + + + + + + Transmit path + Recive path + PN MONITORING + + AXI CLKGEN + 100MHz + 120MHz + 120Mhz + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 32b + 32b + 64b + 64b + 16b + 16b + 16b + 16b + 32b + 32b + + + + + + + diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/HDL-project/index.rst b/docs/solutions/reference-designs/eval-cn0584-ebz/HDL-project/index.rst new file mode 100644 index 000000000..b37c739bb --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/HDL-project/index.rst @@ -0,0 +1,100 @@ +HDL Project +============ + +Introduction +------------ + +This page describes the HDL project for +:ref:`CN0584 Precision Low Latency Development Kit ` +and :ref:`CN0585 Quad Channel, Low Latency, Data Acquisition and Signal Generation Module `. + +Functional Overview +------------------- + +The HDL reference design is an embedded system built around a processor core +either ARM, NIOS-II, or Microblaze. A functional block diagram of the system +is shown below. The device digital interface is handled by specific device +cores :git-repo:`axi_ad35552r ` +for the DAC path and :git-repo:`axi_ltc2387 ` +for the ADC path. The cores are programmable through an AXI-lite interface. + +.. figure:: cn0585_hdl_diagram.svg + +Digital Interface +----------------- + +The digital interface consists of a Quad SPI port running at 15/60MHz depending +on the FSM state (control/stream) for the DAC path and 3 LVDS serial pairs for +the ADC path. The clock signals are generated by the AXI_PWM_GEN and AXI_CLKGEN +IP cores. + +DAC Interface +------------- + +The DAC data may be sourced from an internal data generator (DDS or pattern), +from the external DDR via DMA or from the ADC. The source control selection can +be made by updating the `REG_CHAN_CNTRL_7 (DAC Channel) ` +register. + +ADC Interface +------------- + +The ADC data is sent to DDR via DMA. The ADC PACK IP (util_cpack) allows the use +of a single DMA IP core for all four analog-to-digital converters. + +Control and SPI +--------------- + +The SPI signals of the ADC are controlled by the SPI port of the ARM processor. + +The DAC’s control is performed by the :git-repo:`axi_ad35552r ` +IP core. + +Download +-------- + +.. admonition:: Download + + The HDL repository, list of supported carriers, and the list of required IP + cores can be found here: + + - Hardware: :adi:`EVAL-CN0585-FMCZ ` + - HDL Project: `hdl_cn0585 `_ + - Carriers: `zed `_ + - Library Cores: + + - `axi_clkgen `_ + - `axi_dmac `_ + - `axi_hdmi_tx `_ + - `axi_i2s_adi `_ + - `axi_ltc2387 `_ + - `axi_ad3552r `_ + - `axi_pwm_gen `_ + - `axi_spdif_tx `_ + - `axi_sysid `_ + - `sysid_rom `_ + +Reference Demos & Software +-------------------------- + +- :adi:`CN0584 Precision Low Latency Development Kit ` +- :adi:`CN0585 Quad Channel, Low Latency, Data Acquisition and Signal Generation Module ` +- :git-hdl:`AXI_AD3552R IP core ` +- :git-hdl:`AXI_LTC2387 IP core ` +- :dokuwiki:`AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Linux device driver ` +- :dokuwiki:`LTC2387 SAR ADC IIO Linux Driver ` + +Help & Support +---------------- + +The :dokuwiki:`carriers (abbreviations can be found here) ` +are commonly available FPGA evaluation boards. + +The :git-hdl:`HDL user guide ` contains all the documentation, build instructions and register map tables. + +The following quick links allows you to browse the github repository for a list of current `branches `_, +`library components `_, and `projects `_. + +Questions? We can help with `FPGA questions `_, +`Linux driver questions `_, or +`No-OS Drivers questions `_. diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/captured_loopback_signal_cn0585.jpg b/docs/solutions/reference-designs/eval-cn0584-ebz/captured_loopback_signal_cn0585.jpg new file mode 100644 index 000000000..035d572f7 --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/captured_loopback_signal_cn0585.jpg @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9b2e8872236001f92cbbb0c7e56b6e38147886dccd7a18ac3020e2db9c258144 +size 87952 diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/cn0584.png b/docs/solutions/reference-designs/eval-cn0584-ebz/cn0584.png new file mode 100644 index 000000000..cba6b41ac --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/cn0584.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:0f253ce66c0a37aae62ca7b8a853b207f52a34aca90f8cc765dafbbaff5c471f +size 46016 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There are four +subsystems within this model: a DDS, a mixer, a FIR filter, and a PID +controller. + +Python scripts are provided that showcase each subsystem. These scripts are +designed to run with the ADCs and DACs connected in loopback mode, as described +in the example :ref:`Setting Up the Hardware Section `, +and shown in the following image. + +.. figure:: cn0584_loopback_connection.png + + EVAL-CN0585-FMCZ with loopback connection + +The additional packages required to run these scripts are: scipy.fft, +scipy.signal. + +External signals can be used as inputs to the ADCs if desired, needed changes +are explained in each section. + +The ad3552r_0.output_range should be updated in each script to match the +configuration of the board being used, but is default set to +10V/-10V. Each +script produces a set of Python plots and terminal outputs. The terminal outputs +display the configurations that were set, followed by additional measurements +calculated specific to each model. + +The parameters for each subsystem are controlled by AXI registers. The AXI +register are 32-bits, but can be used for a variety of datatypes including int16 +and fixed point decimals. Each parameter is described in the following sections +with its datatype and possible range of values for the user to modify as +desired. + +.. note:: + + All ADC and DAC numbers are 0-indexed. For example, the 4 DACs + are labeled DAC0, DAC1, DAC2 and DAC3. Same applies to ADCs. + +Files +~~~~~ + +The simulink model files can be downloaded from this zip file +:download:`Simulink models` and placed in the +HighSpeedConverterToolbox/test folder. The PID and DDS are submodels within the +top level testModel_template_top.slx file, and the path pointing to the +submodels should be updated to reflect the new correct path on the user’s +machine. See the Build section at the bottom of this page for instructions on +implementing the model. Additionally, the bootfile is provided here :download:`Boot file` +and can be copied directly into the boot directory of the SD card. + +The Python example scripts can be downloaded from this zip file +:download:`Python Examples`, and placed in the +pyadi-iio/examples folder while in the cn0585_v1 branch. + +The following sections describe the model and scripts in more detail. + +DDS +~~~ + +One subsystem in the model is a Direct Digital Synthesizer (DDS) that outputs a +sine wave. This signal outputs on DAC3. + +.. figure:: dt_dds_bd.png + + DDS subsystem diagram + +Run +^^^ + +To see the DDS in action, run the provided python script +**cn0585_fmcz_example_dds.py** the same way the generic cn0585_fmcz_example.py +script is run. + +The following lines should be observed in the terminal after completion: + +.. code-block:: console + + $ python examples/cn0585_fmcz_example_dds.py ip:169.254.92.202 + uri: ip:169.254.92.202 + ############################################# + GPIO4_VIO state is: 0 + GPIO5_VIO state is: 0 + Voltage monitor values: + Temperature: 41.25 C + Channel 0: 2274.1699200119997 millivolts + Channel 1: 643.310546348 millivolts + Channel 2: 2017.822263972 millivolts + Channel 3: 763.5498040619999 millivolts + Channel 4: 2082.519529544 millivolts + Channel 5: 2090.4540998499997 millivolts + Channel 6: 2259.521482524 millivolts + Channel 7: 1806.030271958 millivolts + Buffer size is 1048576 + Sampling rate is: 15000000 + input_source:dac0: adc_input + input_source:dac1: adc_input + ############################################# + DDS frequency set to 10000 Hz + DDS amplitude set to 9.99969482421875 V + DDS phase shift set to 0 degrees + +The last printed section displays what the parameter values were set to in the +AXI registers. These can be compared to the Python plot for accuracy. + +In addition, the following window will pop up. This displays the voltage data +captured at ADC3 in the top plot, and the corresponding spectrum done by FFT +(Fast Fourier Transform) of the data in the bottom plot. + +.. figure:: dt_dds_plot.png + + DDS output captured on ADC3 and FFT + +Parameters +^^^^^^^^^^ + +The parameters for the DDS can be found on lines 14-18 as so: + +.. code-block:: python + + # user inputs + freq = 10000 + amp = 2**15-1 + phase_shift = 0 + external_signals = 0 + +The *freq* variable controls the output frequency of the DDS, this can range +from 0 to 1000000 in steps of 1, the units are Hertz. The *amp* variable +controls the amplitude of the sine wave, in units of DAC codes, with a maximum +value of 32767, or 2^15-1, in steps of 1. The conversion between DAC codes and +voltage can be found on the :adi:`AD3552R` datasheet. The *phase_shift* offsets +the sine wave phase, from -360 to 360 in steps of 1, in units of degrees. +The *external_signals* variable should be set to 0 when the +ADCs and DACs are connected in loopback mode, and set to 1 when the signals are +being driven and measured with external devices. See following section for more +details on hardware connections. + +External Inputs and Outputs +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +There are no external inputs on this system. The output of the DDS can be seen +by connecting DAC3 to the desired system. + +Mixer +~~~~~ + +The mixer takes one input from ADC0 and multiplies it with the output of the +DDS. In loopback mode, the signal into ADC0 is generated from the DMA of DAC0. +The output of the mixer goes to DAC2. + +.. figure:: dt_mixer_bd.png + + Mixer subsystem diagram + +Run +^^^ + +The script **cn0585_fmcz_example_dds_mixer.py** is an example of how to see the +mixer output. Run this the same way as the other example scripts. After running, +the following output should be seen in the terminal. + +.. code-block:: console + + $ python examples/cn0585_fmcz_example_dds_mixer.py ip:169.254.92.202 + uri: ip:169.254.92.202 + ############################################# + GPIO4_VIO state is: 0 + GPIO5_VIO state is: 0 + Voltage monitor values: + Temperature: 47.75 C + Channel 0: 2274.780271574 millivolts + Channel 1: 644.5312494719999 millivolts + Channel 2: 2012.329099914 millivolts + Channel 3: 763.5498040619999 millivolts + Channel 4: 2079.467771734 millivolts + Channel 5: 2084.960935792 millivolts + Channel 6: 2257.690427838 millivolts + Channel 7: 1806.030271958 millivolts + Buffer size is 150000 + Sampling rate is: 15000000 + input_source:dac0: dma_input + input_source:dac1: adc_input + ############################################# + DDS frequency set to 2000 Hz + DDS amplitude set to 0.3125 V + DDS phase shift set to 0 degrees + DMA frequency set to 3000 Hz + DMA amplitude set to 0.0390625 V + The mixer output's largest frequency component is at 5.0 kHz, with estimated signal power 13.82 dB + +The last section of the terminal output displays the settings of the two input +waves, as well as the largest frequency component of the mixer output. + +The below window will pop up. The first plot shows the DDS output captured on +ADC3, and the second plot shows the input on ADC0. The final two plots show the +mixer output looped back and captured from ADC2, and its FFT transformation. + +.. figure:: dt_mixer_plot.png + + Mixer inputs from DDS and ADC0 (top 2 graphs), Mixer out and its FFT + (bottom 2 graphs) + +Parameters +^^^^^^^^^^ + +The parameters used are similar to those for the DDS example, and can be found +on lines 13-18. + +.. code-block:: python + + # user inputs + dds_freq = 2000 + dma_freq = 3000 + dds_amp = 2**10 + dma_amp = 2**7 + dds_phase_shift = 0 + external_signals = 0 + +The units are as described in the DDS section, but here are labeled with whether +they control the output of the DDS- or DMA-generated sine wave. Note the +DMA-generated wave does not have a phase shift option. The *external_signals* +variable should be set to 0 when the ADCs and DACs are connected in loopback +mode, and set to 1 when the signals are being driven and measured with external +devices. See following section for more details on hardware connections. + +External Inputs and Outputs +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To use external inputs or outputs, connect an analog input signal to ADC0. The +output of the mixer on DAC2 can then be connected to a desired measurement +device or system. + +FIR Filter +~~~~~~~~~~ + +The FIR filter is implemented as a moving average filter with 32 taps. The +cutoff frequency of the filter is at 200kHz. The simulated frequency response of +the filter is shown below. + +.. figure:: dt_fir_bode.png + + FIR filter bode plot + +In loopback mode, a noisy test signal is generated from the DMA of DAC3 then fed +to ADC3. The filter takes the input from ADC3, and outputs the filtered signal +on DAC0. + +.. figure:: dt_fir_bd.png + + FIR filter subsystem diagram + +Run +^^^ + +Run the **cn0585_fmcz_example_fir_filter.py** script the same way as the other +scripts. The signal into the FIR filter is generated as a 10kHz signal, +superimposed with 800kHz and random noise, the latter two of which should be +reduced after being filtered. + +The terminal output should resemble the following. + +.. code-block:: console + + $ python examples/cn0585_fmcz_example_fir_filter.py ip:169.254.92.202 + uri: ip:169.254.92.202 + ############################################# + GPIO4_VIO state is: 0 + GPIO5_VIO state is: 0 + Voltage monitor values: + Temperature: 47.75 C + Channel 0: 2274.780271574 millivolts + Channel 1: 643.92089791 millivolts + Channel 2: 2000.7324202359998 millivolts + Channel 3: 764.1601556239999 millivolts + Channel 4: 2072.7539045519998 millivolts + Channel 5: 2075.805662362 millivolts + Channel 6: 2257.080076276 millivolts + Channel 7: 1806.030271958 millivolts + Buffer size is 4096 + Sampling rate is: 15000000 + input_source:dac0: adc_input + input_source:dac1: dma_input + ############################################# + SNR of unfiltered signal: 10.699287492673212 dB + SNR of filtered signal: 24.032664229257037 dB + The signal at 800039 Hz was attenuated by 17.553201089520595 dB + +The last section shows the calculated signal to noise ratio of the signal pre- +and post-filter. The filtered signal should have a better SNR. The attenuation +of the 800kHz is also shown, a frequency which is in the cutoff region and +should be substantially attenuated. + +And the window with the below plots should pop up. The input to the FIR filter +and its FFT are displayed in the first and third plots, while the filter output +and its FFT are in the second and fourth. + +.. figure:: dt_fir_plot.png + + FIR filter output in plots 2 and 4, from the input captures in plots 1 and 3 + +Parameters +^^^^^^^^^^ + +The only parameter in this model is the external_signals variable on line 14 of +the script. + +The external_signals variable should be set to 0 when the ADCs and DACs are +connected in loopback mode, and set to 1 when the signals are being driven and +measured with external devices. See following section for more details on +hardware connections. + +External Inputs and Outputs +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +An input analog signal can be connected to ADC3 to go into the filter, and the +filter output can be taken from DAC0. + +PID +~~~ + +The PID controller has the set point and feedback inputs on ADC2 and ADC1 +respectively, with the output on DAC1. Figure 8 shows the isolated system in the +board. Figure 9 shows a closed loop example using a voltage divider as a plant. + +.. figure:: dt_pid_bd.png + + PID subsystem diagram + +External Inputs and Outputs +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This design is intended to be used with an external plant, and as such is +expected to always use external signals. ADC2 should be driven by the desired +set point. To add a plant to the PID controller, connected the PID output on +DAC1 to the input of the plant. Then the output of the plant must be connected +to the feedback point on ADC1. + +Figure 10 shows an example of using voltage divider as plant. It is composed of +two 3k-Ohm resistors in series, connecting PID output at DAC1 to ground. The +connection point between the resistors the connects to the feedback point at +ADC1. The set point is driven by a +/-4V square wave. + +.. figure:: dt_pid_close_loop.png + + PID subsystem diagram with resistor divider connected as plant + forming a closed loop system + +Run +^^^ + +Run the **cn0585_fmcz_example_pid.py** script as the other scripts. Cite above +closed loop system as example, the signal into setpoint is a square wave +generated from external function generator. + +The terminal output should resemble the following. + +.. code-block:: console + + $ python examples/cn0585_fmcz_example_pid.py ip:169.254.92.202 + ############################################# + GPIO4_VIO state is: 0 + GPIO5_VIO state is: 0 + Voltage monitor values: + Temperature: 48.0 C + Channel 0: 2269.2871075159997 millivolts + Channel 1: 649.4140619679999 millivolts + Channel 2: 2052.001951444 millivolts + Channel 3: 764.1601556239999 millivolts + Channel 4: 2086.181638916 millivolts + Channel 5: 2081.909177982 millivolts + Channel 6: 2252.19726378 millivolts + Channel 7: 1798.706053214 millivolts + Buffer size is 20000 + Sampling rate is: 15000000 + input_source:dac0: adc_input + input_source:dac1: dma_input + ############################################# + PID controller Kp given as: 1 + PID controller Ki given as: 0.2 + PID controller Kd given as: 0.01 + Register value for kp: 1024 decimal value: 1.0 + Register value for ki: 204 decimal value: 0.19921875 + Register value for kd: 10 decimal value: 0.009765625 + +And the window with the below plots should pop up. The input to the set point is +displayed on top graph, it’s a 500Hz square wave with -/+4V amplitude. The +bottom graph is the feedback which resembles the set point with some overshoot +feature and small latency. + +.. figure:: dt_pid_plot.png + + Setpoint of PID in top plot, feedback in bottom plot + +The following figure shows the two signals on an oscilloscope with clear PID +features shown. + +.. figure:: dt_pid_scope.png + + Example PID controller test result. Channel 1 (yellow) is setpoint, + Channel 3 (blue) is feedback after going through voltage divider plant + +Parameters +^^^^^^^^^^ + +The parameters can be found on lines 15-17 as shown below. *Kp*, *Ki*, and *Kd* are +respectively the proportional, integral, and derivative coefficients. All three +coefficients are unsigned fixed point numbers with 6 bits of integers and 10 +decimal bits. + +.. code-block:: python + + # user inputs + Kp = 1 + Ki = 0.2 + Kd = 0.01 + +Build +----- + +After the HighSpeedConvertToolbox repo is set up on the machine as described in +the Matlab Configuration Guide page of the wiki and the digital template models +have been put in the correct folder, the Simulink model can be opened and built. +This mostly follows the step on `this page `_, +but a few changes are required. + +Before starting the build process, go to Configuration Parameters -> HDL Code +Generation -> Global Settings and set the Reset Type to Synchronous. + +Open the HDL Workflow Advisor and start the build process as described in the +Matlab Configuration Guide. + +In step 1.2, the reference design should be selected as TX. + +.. figure:: dt_build_1-2.png + + Build step 1.2 Reference design TX + +In step 1.3, ensure the connections are configured to match the screenshots +below. + +.. figure:: dt_ports1.png + + Build step 1.3 Port connections + +.. figure:: dt_ports2.png + + Build step 1.3 Port connections + +In step 4.1, set the synthesis objective to Speed Optimized. + +.. figure:: dt_build_4-1.png + + Build step 4.1 Synthesis objective speed optimized + +The bootfile generated from this model does have some remaining timing +violations within a MATLAB IP block. They do not significantly impact the +performance of the system, however if they are desired to be removed, a custom +set of blocks could be designed to replace the IP block. diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/eval-cn0585-fmcz_angle-web.jpg b/docs/solutions/reference-designs/eval-cn0584-ebz/eval-cn0585-fmcz_angle-web.jpg new file mode 100644 index 000000000..4dc10cdfa --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/eval-cn0585-fmcz_angle-web.jpg @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:dda865f488d42611cd8192c5a945052a5274d588f3a7bf7ec2a312147a2ad8e5 +size 71690 diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/eval-cn0585-fmcz_kit_angle.jpg b/docs/solutions/reference-designs/eval-cn0584-ebz/eval-cn0585-fmcz_kit_angle.jpg new file mode 100644 index 000000000..23752f7be --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/eval-cn0585-fmcz_kit_angle.jpg @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8707d7aa93b31f1f6562d29167e94123618a20f7927bebcb01e7f16f98132dbd +size 61677 diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/eval-cn0585-fmcz_kit_top.jpg b/docs/solutions/reference-designs/eval-cn0584-ebz/eval-cn0585-fmcz_kit_top.jpg new file mode 100644 index 000000000..544837ff3 --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/eval-cn0585-fmcz_kit_top.jpg @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:0758ed83c97c4842b9cbbca79c550d36b9198259fce410628d7d91a860db7c5a +size 111557 diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/figure15_adc_cap_data_python_plot.png b/docs/solutions/reference-designs/eval-cn0584-ebz/figure15_adc_cap_data_python_plot.png new file mode 100644 index 000000000..c849a24fa --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/figure15_adc_cap_data_python_plot.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ab8f7004c1f58455e9955526589fc13be1546c6de2564cfb0aac3bc7934b1472 +size 159686 diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/hil_cn0584_personalityboard_top-web.jpg b/docs/solutions/reference-designs/eval-cn0584-ebz/hil_cn0584_personalityboard_top-web.jpg new file mode 100644 index 000000000..86783a4b3 --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/hil_cn0584_personalityboard_top-web.jpg @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b541e79f9aac6553cabbede36dd5cb30cf321ff7dbc41ef9a2ef22c1957c1c72 +size 135810 diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/index.rst b/docs/solutions/reference-designs/eval-cn0584-ebz/index.rst new file mode 100644 index 000000000..a490bc7fe --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/index.rst @@ -0,0 +1,853 @@ +.. _eval-cn0584-ebz: + +EVAL-CN0584-EBZ +=============== + +Precision Low Latency Development Kit +"""""""""""""""""""""""""""""""""""""" + +Overview +-------- + +.. figure:: eval-cn0585-fmcz_kit_angle.jpg + :width: 1000 px + :align: left + + CN0584 Low Latency Development Kit + +The :adi:`CN0584` Low Latency Development Kit is a development platform consisting of two +boards the :adi:`EVAL-CN0585-FMCZ ` and the :adi:`EVAL-CN0584-EBZ `. + +:adi:`EVAL-CN0585-FMCZ ` consists of 4 x 16-bit ADC channels and +4 x 16-bit DAC channels that are interfaced with an FPGA through the +FMC Low Pin Count (LPC) Connector. Current revision of :adi:`EVAL-CN0585-FMCZ ` +is Rev B. :adi:`EVAL-CN0584-EBZ ` is the application specific analog front end (AFE) board. +CN0584 is connected to a Zedboard to build a development system setup. + +The Low Latency Development Kit (LLDK) provides a complete data acquisition and +signal generation platform with on-board power rails, voltage monitoring, logic +level translation, general purpose I/O, I2C, SPI, and a personality interface +connector. + +The key performance benefit of the LLDK system is the ability to perform a +complete capture and conversion of precision analog input data in <70ns with the +ADC module and generate a settled full-scale analog output in <200ns from +initial data written to the DAC. + +Connections and Configurations +------------------------------ + +.. figure:: hil_cn0584_personalityboard_top-web.jpg + + EVAL-CN0584-EBZ Board + +.. figure:: 001.svg + :width: 800 px + + Simplified Block Diagram of LLDK + +ADC Inputs +~~~~~~~~~~ + +There are four channels of differential input signals on :adi:`EVAL-CN0584-EBZ `. + +.. table:: ADC Input Signal Connectors + + ========= ===================== ===================== + Channel Positive Input Signal Negative Input Signal + ========= ===================== ===================== + Channel 0 J1 J2 + Channel 1 J3 J4 + Channel 2 J5 J6 + Channel 3 J7 J8 + ========= ===================== ===================== + +ADC Input Range Configuration +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This LLDK has configurable input voltage ranges of ±10V (Default), ±5V, ±4.096V, +±2.5V, and ±1.5V. The input range can be changed by modifying resistor +placements on :adi:`EVAL-CN0584-EBZ ` as described in Table 2. + +.. table:: ADC Input Voltage Range Selection by Resistor Connections + + +-----------+---------------------+-------------------------------------------+ + | Channel | Input Voltage Range | AFE Board Modification | + +===========+=====================+===========================================+ + | Channel 0 | ±10 V (default) | Include R19A, R21A, R22A, R24A; DNI R18A, | + | | | R20A, R23A, R25A | + +-----------+---------------------+-------------------------------------------+ + | | ±5 V | Include R18A, R20A, R23A, R25A; DNI R19A, | + | | | R21A, R22A, R24A | + +-----------+---------------------+-------------------------------------------+ + | | ±4.096 V | Include R19A, R21A; DNI R18A, R20A, R22A, | + | | | R23A, R24A, R25A | + +-----------+---------------------+-------------------------------------------+ + | | ±2.5 V | Include R18A, R20A; DNI R19A, R21A, R22A, | + | | | R23A, R24A, R25A | + +-----------+---------------------+-------------------------------------------+ + | | ±1.5 V | Include R18A, R19A, R20A, R21A; DNI R22A, | + | | | R23A, R24A, R25A | + +-----------+---------------------+-------------------------------------------+ + | Channel 1 | ±10 V (default) | Include R19B, R21B, R22B, R24B; DNI R18B, | + | | | R20B, R23B, R25B | + +-----------+---------------------+-------------------------------------------+ + | | ±5 V | Include R18B, R20B, R23B, R25B; DNI R19B, | + | | | R21B, R22B, R24B | + +-----------+---------------------+-------------------------------------------+ + | | ±4.096 V | Include R19B, R21B; DNI R18B, R20B, R22B, | + | | | R23B, R24B, R25B | + +-----------+---------------------+-------------------------------------------+ + | | ±2.5 V | Include R18B, R20B; DNI R19B, R21B, R22B, | + | | | R23B, R24B, R25B | + +-----------+---------------------+-------------------------------------------+ + | | ±1.5 V | Include R18B, R19B, R20B, R21B; DNI R22B, | + | | | R23B, R24B, R25B | + +-----------+---------------------+-------------------------------------------+ + | Channel 2 | ±10 V (default) | Include R19C, R21C, R22C, R24C; DNI R18C, | + | | | R20C, R23C, R25C | + +-----------+---------------------+-------------------------------------------+ + | | ±5 V | Include R18C, R20C, R23C, R25C; DNI R19C, | + | | | R21C, R22C, R24C | + +-----------+---------------------+-------------------------------------------+ + | | ±4.096 V | Include R19C, R21C; DNI R18C, R20C, R22C, | + | | | R23C, R24C, R25C | + +-----------+---------------------+-------------------------------------------+ + | | ±2.5 V | Include R18C, R20C; DNI R19C, R21C, R22C, | + | | | R23C, R24C, R25C | + +-----------+---------------------+-------------------------------------------+ + | | ±1.5 V | Include R18C, R19C, R20C, R21C; DNI R22C, | + | | | R23C, R24C, R25C | + +-----------+---------------------+-------------------------------------------+ + | Channel 3 | ±10 V (default) | Include R19D, R21D, R22D, R24D; DNI R18D, | + | | | R20D, R23D, R25D | + +-----------+---------------------+-------------------------------------------+ + | | ±5 V | Include R18D, R20D, R23D, R25D; DNI R19D, | + | | | R21D, R22D, R24D | + +-----------+---------------------+-------------------------------------------+ + | | ±4.096 V | Include R19D, R21D; DNI R18D, R20D, R22D, | + | | | R23D, R24D, R25D | + +-----------+---------------------+-------------------------------------------+ + | | ±2.5 V | Include R18D, R20D; DNI R19D, R21D, R22D, | + | | | R23D, R24D, R25D | + +-----------+---------------------+-------------------------------------------+ + | | ±1.5 V | Include R18D, R19D, R20D, R21D; DNI R22D, | + | | | R23D, R24D, R25D | + +-----------+---------------------+-------------------------------------------+ + +DAC Outputs +~~~~~~~~~~~ + +LLDK can support multiple output voltage ranges which can be configured, such as +0V to 2.5V, 0V to 5V, −5V to +5V, and −10V to +10V, and custom +intermediate ranges with full 16-bit resolution. In order to change the output +range, resistor placements on the AFE board must be modified and register +settings must be applied to :adi:`AD3552R` on :adi:`EVAL-CN0585-FMCZ ` +as described in Table 4. + +.. table:: DAC Output Signal Connectors + + ======= ============================================= + Channel Output Signal + ======= ============================================= + A J9 + B J10 + C J11 + D J12 + ======= ============================================= + +.. table:: DAC Output Voltage Range Selection by Resistor Connections and Register Settings + + +---------+---------------+---------+---------+---------------+---------------+ + | Channel | Output Span | VZS (V) | VFS (V) | AFE Board | Register | + | | | | | Modification | Setting | + +=========+===============+=========+=========+===============+===============+ + | CH0 | +/- 10V | -10.382 | 10.380 | Include R9; | CH0_CH1 | + | | (Default) | | | DNI R10, R11 | _OUTPUT_RANGE | + | | | | | | = 0x100 | + +---------+---------------+---------+---------+---------------+---------------+ + | | +/- 5V | -5.165 | 5.166 | Include R11; | CH0_CH1 | + | | | | | DNI R9, R10 | _OUTPUT_RANGE | + | | | | | | = 0x011 | + +---------+---------------+---------+---------+---------------+---------------+ + | | 10V | -0.165 | 10.163 | Include R11; | CH0_CH1 | + | | | | | DNI R9, R10 | _OUTPUT_RANGE | + | | | | | | = 0x010 | + +---------+---------------+---------+---------+---------------+---------------+ + | | 5V | -0.078 | 5.077 | Include R10; | CH0_CH1 | + | | | | | DNI R9, R11 | _OUTPUT_RANGE | + | | | | | | = 0x001 | + +---------+---------------+---------+---------+---------------+---------------+ + | | 2.5V | -0.198 | 2.701 | Include R10; | CH0_CH1 | + | | | | | DNI R9, R11 | _OUTPUT_RANGE | + | | | | | | = 0x000 | + +---------+---------------+---------+---------+---------------+---------------+ + | CH1 | +/- 10V | -10.382 | 10.380 | Include R12; | CH0_CH1 | + | | (Default) | | | DNI R13, R14 | _OUTPUT_RANGE | + | | | | | | = 0x100 | + +---------+---------------+---------+---------+---------------+---------------+ + | | +/- 5V | -5.165 | 5.166 | Include R13; | CH0_CH1 | + | | | | | DNI R12, R14 | _OUTPUT_RANGE | + | | | | | | = 0x011 | + +---------+---------------+---------+---------+---------------+---------------+ + | | 10V | -0.165 | 10.163 | Include R13; | CH0_CH1 | + | | | | | DNI R12, R14 | _OUTPUT_RANGE | + | | | | | | = 0x010 | + +---------+---------------+---------+---------+---------------+---------------+ + | | 5V | -0.078 | 5.077 | Include R14; | CH0_CH1 | + | | | | | DNI R12, R13 | _OUTPUT_RANGE | + | | | | | | = 0x001 | + +---------+---------------+---------+---------+---------------+---------------+ + | | 2.5V | -0.198 | 2.701 | Include R14; | CH0_CH1 | + | | | | | DNI R12, R13 | _OUTPUT_RANGE | + | | | | | | = 0x000 | + +---------+---------------+---------+---------+---------------+---------------+ + | CH2 | +/- 10V | -10.382 | 10.380 | Include R15; | CH2_CH3 | + | | (Default) | | | DNI R16, R17 | _OUTPUT_RANGE | + | | | | | | = 0x100 | + +---------+---------------+---------+---------+---------------+---------------+ + | | +/- 5V | -5.165 | 5.166 | Include R16; | CH2_CH3 | + | | | | | DNI R15, R17 | _OUTPUT_RANGE | + | | | | | | = 0x011 | + +---------+---------------+---------+---------+---------------+---------------+ + | | 10V | -0.165 | 10.163 | Include R16; | CH2_CH3 | + | | | | | DNI R15, R17 | _OUTPUT_RANGE | + | | | | | | = 0x010 | + +---------+---------------+---------+---------+---------------+---------------+ + | | 5V | -0.078 | 5.077 | Include R17; | CH2_CH3 | + | | | | | DNI R15, R16 | _OUTPUT_RANGE | + | | | | | | = 0x001 | + +---------+---------------+---------+---------+---------------+---------------+ + | | 2.5V | -0.198 | 2.701 | Include R17; | CH2_CH3 | + | | | | | DNI R15, R16 | _OUTPUT_RANGE | + | | | | | | = 0x000 | + +---------+---------------+---------+---------+---------------+---------------+ + | CH3 | +/- 10V | -10.382 | 10.380 | Include R18; | CH2_CH3 | + | | (Default) | | | DNI R19, R20 | _OUTPUT_RANGE | + | | | | | | = 0x100 | + +---------+---------------+---------+---------+---------------+---------------+ + | | +/- 5V | -5.165 | 5.166 | Include R19; | CH2_CH3 | + | | | | | DNI R18, R20 | _OUTPUT_RANGE | + | | | | | | = 0x011 | + +---------+---------------+---------+---------+---------------+---------------+ + | | 10V | -0.165 | 10.163 | Include R19; | CH2_CH3 | + | | | | | DNI R18, R20 | _OUTPUT_RANGE | + | | | | | | = 0x010 | + +---------+---------------+---------+---------+---------------+---------------+ + | | 5V | -0.078 | 5.077 | Include R20; | CH2_CH3 | + | | | | | DNI R18, R19 | _OUTPUT_RANGE | + | | | | | | = 0x001 | + +---------+---------------+---------+---------+---------------+---------------+ + | | 2.5V | -0.198 | 2.701 | Include R20; | CH2_CH3 | + | | | | | DNI R18, R19 | _OUTPUT_RANGE | + | | | | | | = 0x000 | + +---------+---------------+---------+---------+---------------+---------------+ + +Voltage Reference +~~~~~~~~~~~~~~~~~ + +The default ADC reference configuration uses the internal 2.048V, ±0.1% +accurate, 20ppm/°C max voltage reference. For more stringent use cases where +the accuracy and temperature drift is an issue, an external :adi:`LTC6655` +2.048V, ±0.025% accurate, 2ppm/°C max voltage reference can be used. + +The default DAC reference configuration uses the internal 2.5V, ±0.3% accurate, +10ppm/°C max voltage reference. For more stringent use cases where the accuracy +and temperature drift is an issue, an external :adi:`ADR4525` 2.5V, +±0.02% accurate, 2ppm/°C max voltage reference can be used. + +.. table:: VREF Configuration + + +------------------+-------------------------+ + | VREF | Jumper Settings | + +==================+=========================+ + | ADC_VREF | Short P5 | + +------------------+-------------------------+ + | DAC_VREF | Short P4 | + +------------------+-------------------------+ + +Power Supply Considerations and Configuration +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +All power for CN0584 is provided by :adi:`EVAL-CN0585-FMCZ ` through +the analog front end (AFE) connector. CN0584 uses the +15V and -15V rails to provide the positive +and negative supply voltages for the :adi:`ADG5421F` input protection switches. The +12V and -12V rails +provide the positive and negative supply voltages for the :adi:`ADA4898-1` ADC buffer amplifiers. +The +3.3V rail powers the EEPROM circuit. + +Power tree information can be found in :adi:`EVAL-CN0585-FMCZ `. +Table 6 provides more details on LLDK power rails: + +.. table:: Power Rail Descriptions + + ========== ============================================================ + Power Rail Description + ========== ============================================================ + +12 V LT3045-1 provides the 12V rail supplying up 280mA + -12 V LT3094 provides the -12V rail supplying up to -280mA + +15 V LTM8049 provides the +15V rail at 80% efficiency + -15 V LTM8049 provides the -15V rail at 80% efficiency + +3.3 V Fed through from the FPGA FMC connector to the AFE connector + ========== ============================================================ + +System Setup Using a ZedBoard +----------------------------- + +CN0584 is fully supported using a ZedBoard. + +.. figure:: eval-cn0585-fmcz_kit_top.jpg + + EVAL-CN0585-FMCZ revB connected to EVAL-CN0584-EBZ + +.. figure:: eval-cn0585-fmcz_angle-web.jpg + + EVAL-CN0585-FMCZ revB + +The following is a list of items needed for system setup: + +- **Hardware** + + - :adi:`EVAL-CN0585-FMCZ(RevB) ` + (Note: Figure 4 features EVAL-CN0585-FMCZ RevA board. Current LLDK system has RevB board shown in + Figure 5, same connectors and functionalities, only different in USB-C power supply.) + - :adi:`EVAL-CN0584-EBZ ` + - `ZedBoard `__ + Rev D or later board + - 12Vdc, 3A power supply + - 16GB (or larger) Class 10 (or faster) micro-SD card (included in the box) + - USB-C power source (included in the EVAL-CN0585-FMCZ RevB box) + - Micro-USB to Type-A cable + - Ethernet cable + - User interface setup (choose one): + - HDMI monitor, keyboard, and mouse plugged directly into the ZedBoard + - Host Windows/Linux/Mac computer on the same network as the ZedBoard + +- **Software** + + - Host PC (Windows or Linux) + - A UART terminal if need to access Linux system on the ZedBoard + (Putty/TeraTerm/Minicom, etc.), Baud rate 115200 (8N1) + - :ref:`IIO Oscilloscope ` + - `Kuiper Linux `__ + +Loading Image on SD Card +~~~~~~~~~~~~~~~~~~~~~~~~ + +The box includes a pre-programmed SD card. You can skip the steps in this +section and go to the :ref:`Setting Up the Hardware Section ` +if using the provided card. + +To boot the ZedBoard and control the :adi:`EVAL-CN0585-FMCZ `, you will +need to install ADI Kuiper Linux on an SD card. Complete instructions, including +where to download the SD card image, how to write it to the SD card, and how to +configure the system are provided on the `Kuiper Linux page `__. + +Configuring the SD Card +~~~~~~~~~~~~~~~~~~~~~~~ + +Follow the configuration procedure under **Configuring the SD Card for FPGA Projects** +on the `Kuiper Linux page `__ page. + +Copy the following files onto the boot directory to configure the SD card: + +.. admonition:: Download + + for :download:`EVAL-CN0585-FMCZ RevB` + + for :download:`EVAL-CN0585-FMCZ` + +- **uImage** file for Zynq +- **BOOT.BIN** specific to your :adi:`EVAL-CN0585-FMCZ ` + ZedBoard +- **setup_adc.sh** file for setting up ADC +- **devicetree.dtb** devicetree for Zynq specific to your :adi:`EVAL-CN0585-FMCZ ` + ZedBoard. + + The device tree describes the following devices: + + #. ``one-bit-adc-dac`` – controls the MAX7301 + #. ``axi_pwm_gen`` – generates the CNV signal for analog-to-digital converters + #. ``ref_clk`` – generates the sample clock for ADAQ23876 devices and the + reference clock for AD3552R devices + #. ``rx_dma`` – controls the DMA for RX path + #. ``Ltc2387`` – controls ADAQ23876 devices + #. ``qspi0`` – controls the SPI devices that are connected to the PL SPI IP + #. ``dac0_tx_dma`` - controls the DMA for the first AD3552R device + #. ``dac1_tx_dma`` - controls the DMA for the second AD3552R device + #. ``axi_ad3552r_0`` – controls the first AD3552R device + #. ``axi_ad3552r_1`` – controls the second AD3552R device + #. ``I2C`` – controls devices that are connected to PL I2C IP (eeprom, eeprom2, ad7291_1) + +.. _setting_up_the_hardware: + +Setting up the Hardware +~~~~~~~~~~~~~~~~~~~~~~~~ + +#. Prepare the `ZedBoard `__. +#. Insert the SD card into the SD Card Interface Connector (J12). +#. Connect the :adi:`EVAL-CN0585-FMCZ ` board into the ZedBoard FMC connector. +#. Connect the :adi:`EVAL-CN0584-EBZ ` board into the :adi:`EVAL-CN0585-FMCZ `. +#. Connect micro USB to UART port (J14), and the other end to the host PC. +#. Connect the ethernet cable to RJ45 ethernet connector (J11), and the other + end to the host PC. +#. Plug the Power Supply into the 12V Power ZedBoard input connector (J20). + **DO NOT turn the device on**. +#. Plug USB-C power supply to :adi:`EVAL-CN0585-FMCZ ` (revB only). +#. Set the jumpers as seen in figure below. + + .. figure:: zed_jumpers.jpg + + ZedBoard Jumper Settings + +#. Connect the DAC output connectors to the negative ADC input connectors as + shown in Figure 7 using coax cables (e.g., DAC0 to ADC0-neg, DAC1 to ADC1-neg, + etc.). Terminate the positive ADC connectors with 50ohms SMA terminators. + + .. figure:: cn0584_loopback_connection.png + + EVAL-CN0584-EBZ Loopback Connection on AFE + +#. Turn the ZedBoard on. + + - Wait ~30 seconds for the “DONE” LED to turn blue. This is near the DISP1. + The hardware set up is now complete. + + .. figure:: setup_cn0585_diagram.png + + Example System Setup + +.. esd-warning:: + +Application Software (both locally and remotely on the FPGA) +------------------------------------------------------------ + +The CN0584 can be interfaced with using IIO Oscilloscope, Python, or MATLAB to +enable device configuration, capture of incoming samples from the ADCs, and +generation of waveforms to be transmitted by the DACs. + +Hardware Connection +~~~~~~~~~~~~~~~~~~~ + +Libiio is a library used for interfacing with IIO devices and must be installed +on your computer to interface with the hardware. + +Download and install the latest :git-libiio:`Libiio package ` on your +machine. + +To connect to your device, the IIO Osciloscope software must be able to create a +context. The context creation in the software depends on the backend used to +connect to the device as well as the platform where the :adi:`EVAL-CN0585-FMCZ ` is attached. +The ZedBoard running ADI Kuiper Linux is currently the only platform supported for the CN0585. + +The user needs to supply a **Uniform Resource Identifier (URI)** which will be +used in the context creation. To get the URI, use the command iio_info in the +terminal. The `iio_info `__ +command is a part of the libIIO package that reports all IIO attributes. Upon +installation, simply enter the command on the terminal command line to access it. + +For FPGA (ZedBoard) Direct Local Access +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. code-block:: python + + iio_info + +For Windows machine connected to an FPGA (ZedBoard) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. code-block:: python + + iio_info -u ip: + +Example: + +.. code-block:: python + + * If your ZedBoard has the IP address 169.254.92.202, you have to use //iio_info -u ip::169.254.92.202// as your URI + +.. note:: + Do note that the Windows machine and the FPGA board should be connected + to the same network for the machine to detect the device. + +IIO Oscilloscope +~~~~~~~~~~~~~~~~ + +:ref:`IIO Oscilloscope ` +is a cross platform GUI application which can interface with different +evaluation boards from within a Linux system. + +.. important:: + Make sure to download/update to the latest version of + :git-iio-oscilloscope:`IIO Oscilloscope `. + +#. Once done with the installation or an update of the latest IIO Oscilloscope, + open the application. The user needs to supply a URI which will be used in the + context creation of the IIO Oscilloscope. If there’s only one platform is + connected, the IIO Oscilloscope will find URI automatically; if more than one + platforms are connected, the user needs to supply the specific URI. The + instructions to obtain the URI can be found in the previous section. + + **Note: the “Serial Context” connection method is not enabled.** + +#. Press ``Refresh`` to display available IIO Devices and press ``Connect``. + + .. figure:: cn0585_remote_login.jpg + + IIO Oscilloscope Connection + +#. After the board is connected, select the **one-bit-adc-dac-device**, which is + the controller for the MAX7301ATL+ I/O Expander. Then, configure pins values of + output voltages 0 through 9, by setting the **raw value to 1**. + + Press **Write** to confirm. + + .. figure:: max7301atl_output_channels_configuration.png + + MAX7301ATL Output Channels Configuration + + .. table:: Voltage Configuration for GPIO Pins + + +----------------------------------+---------------------------------+ + | one-bit-adc-dac device channel | Schematic Pin | + +==================================+=================================+ + | Voltage0 | GPIO0_VIO | + +----------------------------------+---------------------------------+ + | Voltage1 | GPIO1_VIO | + +----------------------------------+---------------------------------+ + | Voltage2 | GPIO2_VIO | + +----------------------------------+---------------------------------+ + | Voltage3 | GPIO3_VIO | + +----------------------------------+---------------------------------+ + | Voltage4 | GPIO6_VIO | + +----------------------------------+---------------------------------+ + | Voltage5 | GPIO7_VIO | + +----------------------------------+---------------------------------+ + | Voltage6 | PAD_ADC0 | + +----------------------------------+---------------------------------+ + | Voltage7 | PAD_ADC1 | + +----------------------------------+---------------------------------+ + | Voltage8 | PAD_ADC2 | + +----------------------------------+---------------------------------+ + | Voltage9 | PAD_ADC3 | + +----------------------------------+---------------------------------+ + +#. Input sources for AD3552R devices axi-ad3552r-0 and axi-ad3552r-1 can be + configured as dma_input, ramp_input, or adc_input. + + - **dma_input:** DAC input is driven by signals generated by Matlab stored in DMA. + - **ramp_input:** DAC input is driven by ramp signal generated by Matlab stored in DMA. + - **adc_input:** For passthrough models, DAC input is driven by ADC output. + For models with integrated HDL_DUT, DAC input is driven by HDL_DUT outputs. + + Select the desired input source for both AD3552R devices axi-ad3552r-0 and + axi-ad3552r-1 as dma_input. + + .. figure:: input_source_dac0_cn0585.png + + AD3552R Input Source Selection in IIO Oscilloscope + + .. important:: + Even if the input source is set to adc_input or ramp_input the steps regarding the DAC Data + Manager tab have to be followed. + +#. Select the desired output range for both AD3552R devices. + + .. figure:: output_range_cn0585.png + + AD3552R Output Range Selection in IIO Oscilloscope + + .. warning:: + Make sure you don’t try to read/write the output_range attribute + when the stream_status is in start_stream or start_stream_synced. + + .. important:: + After changing the output range, the board should be power cycled + to ensure the DACs operate properly. + +#. From the DAC Data Manager Window select the output channels of the DAC and + enable the cyclic buffer for each DAC. + +#. Load an example file (.mat, .txt, etc) from the IIO Oscilloscope installation + directory, under **Program Files/IIO Oscilloscope/lib/osc/waveforms** folder. + + .. important:: + If the source is set as dma_input and the data from all 4 channels needs + to be synchronized, make sure that you press the load button for + the axi-ad3552r-1 device first then for axi-ad3552r-0. + + .. figure:: dac_data_management_cn0585.jpg + + DAC Data Manager with Example Waves on 4 Channels + +#. Click on the ``Load`` button. + +#. From the Debug window, select the stream_status IIO Attribute and start the + stream (start_stream_synced means that all 4 channels are updated at the same + time and the data streaming process waits for both DACs to be started). + + .. figure:: stream_status_iio.jpg + + DAC Stream Status Selection + +#. After the stream_status has been written and 4 channels are enabled, hit + play button. Then data capture window can be seen like in Figure 15. + + .. figure:: captured_loopback_signal_cn0585.jpg + + Captured Loopback Signal + + .. important:: + Note that there is a phase delay between voltage0/voltage2 and + voltage1/voltage3 because the DAC device channels are updated consecutively. + See the DAC UPDATE MODES section of the :adi:`AD3552R Data Sheet `. + + .. warning:: + If you intend to stop the stream transmission and start it again + synchronized, set the stream_status IIO Attribute to stop_stream for + axi-ad3552r-1 device first then for the axi-ad3552r-0 device. + +PyADI-IIO +~~~~~~~~~ + +The CN0584 can be interfaced to Python using the +:ref:`PyADI-IIO `. +PyADI-IIO is a Python abstraction module to simplify interaction with IIO drivers +on ADI hardware. This module provides device-specific APIs built on top of the +current libIIO Python bindings. These interfaces try to match the driver +naming as much as possible without the need to understand the complexities of +libIIO and IIO. + +Follow the step-by-step procedure on how to install, configure, and set up +PyADI-IIO and install the necessary packages/modules needed by referring to +:ref:`PyADI-IIO `. + +Running the example +^^^^^^^^^^^^^^^^^^^ + +.. admonition:: Download + + Github link for the Python sample script: + :git-pyadi-iio:`CN0585 Python Example ` + +#. Download or git clone :git-pyadi-iio::`pyadi-iio repository ` to your local drive. + + - If direct downloading ZIP folder, make sure to download from cn0585_v1 branch. + - If cloning the repository using `Git `__, type + ``git checkout cn0585_v1`` to switch to the correct branch. + +#. Install additional packages. + + .. code-block:: python + + pip install tk pytest paramiko matplotlib + + Do above in the command prompt window. In general, use pip install "package name" to install any missing package. + +#. After installing and configuring PYADI-IIO on your machine, you are now ready + to run Python script examples. To follow this example, navigate to pyadi-iio + folder (For example, “D:\\pyadi-iio” is where pyadi-iio folder is located). Then + run the **cn0585_fmcz_example.py** found in the examples folder. + + .. code-block:: python + + D:\pyadi-iio>set PYTHONPATH=D:/pyadi-iio/ + D:\pyadi-iio>python examples/cn0585_fmcz_example.py ip:your_board_ip + + Press enter and lines below will be observed: + + :: + + $ python examples/cn0585_fmcz_example.py + uri: ip:your_board_ip + ############# EEPROM INFORMATION ############ + read 256 bytes from /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-1/1-0050/eeprom + Date of Man : Fri Jan 20 08:11:00 2023 + Manufacturer : Analog Devices + Product Name : LLDK-LTC2387-AD3552R + Serial Number : 56864654 + Part Number : 1234 + FRU File ID : 12131321 + PCB Rev : VB + PCB ID : HIL + BOM Rev : VC + Uses LVDS : Y + + ############################################# + GPIO4_VIO state is: 0 + GPIO5_VIO state is: 0 + Voltage monitor values: + Temperature: 49.25 C + Channel 0: 2267.45605283 millivolts + Channel 1: 627.4414057359999 millivolts + Channel 2: 2061.157224874 millivolts + Channel 3: 753.1738275079999 millivolts + Channel 4: 2092.285154536 millivolts + Channel 5: 2084.960935792 millivolts + Channel 6: 2253.4179669039998 millivolts + Channel 7: 1809.69238133 millivolts + AXI4-Lite 0x108 register value: 0x2 + AXI4-Lite 0x10c register value: 0xB + Sampling rate is: 15000000 + input_source:dac0: dma_input + input_source:dac1: dma_input + +The DAC outputs should be looped back into the ADCs as shown in figure 7 in the +System Setup Using a ZedBoard section. After running the script with the board +in this configuration, the following window will pop up: + +.. figure:: figure15_adc_cap_data_python_plot.png + + ADC Captured Data Python Plot + +.. important:: + If you plan to transmit multiple cycles of synchronous stream, + make sure the script starts/stops axi-ad3552r-1 first, then axi-ad3552r-0. + +MATLAB and Simulink +~~~~~~~~~~~~~~~~~~~ + +.. admonition:: Download + + Required MATLAB Add-Ons: + + - :mw:`Communications Toolbox Support Package for Analog Devices ADALM-Pluto Radio ` + - :mw:`HDL Coder ` + - :mw:`SoC Blockset Support Package for Xilinx devices ` + - :mw:`SoC Blockset ` + +.. admonition:: Download + + Github link for the Matlab sample script: :git-repo:`CN0585StreamingTest.m ` + +The steps described in the `Analog Devices Transceiver Toolbox For MATLAB and Simulink `__ +page have to be followed to configure the Matlab/Simulink project using the +:mw:`MathWorks HDL Workflow Advisor `. + +Device Control and Data Streaming +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Remote data streaming to and from hardware is made available through system +object interfaces, which are unique for each component or platform. The hardware +interfacing system objects provide a class to both configure a given platform +and move data back and forth from the device. To run the +:git-repo:`CN0585StreamingTest.m ` +example, the following steps must be completed first. + +#. Ensure MATLAB package “Communications Toolbox Support Package for Analog + Devices ADALM-Pluto Radio” is installed from Matlab Add-Ons. + +#. Execute the following commands on the computer terminal (Cygwin is + recommended for Windows) to set up a local git repository. + + .. code-block:: bash + + git clone https://github.com/analogdevicesinc/HighSpeedConverterToolbox.git + cd HighSpeedConverterToolbox + git submodule update --init --recursive + git checkout cn0585_v1 + +#. Open Matlab from the HighSpeedConverterToolbox directory. + +#. Open CN0585StreamingTest.m from the test subdirectory, update the board_ip + variable to match the Zedboard IP address, and finally run the script. + +The DAC outputs should be looped back into the ADCs as shown in figure 6 in the +System Setup Using a ZedBoard section. After running the script with the board +in this configuration, the window in Figure 17 will pop up. + +.. figure:: matlab_plot.jpg + + ADC Captured Data Matlab Plot + +Note the y-axis is plotted in units of ADC codes, and can be converted to +voltage by referencing the transfer function on the :adi:`ADAQ23876` data sheet. + +.. important:: + If you plan to transmit multiple cycles of synchronous stream, + make sure to start/stop axi-ad3552r-1 first, then axi-ad3552r-0. + +Configuring Custom HDL Models Using Simulink +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The ZedBoard that drives CN0585 is configured with a HDL reference design which +is an embedded system built around a processor core either ARM, NIOS-II, or +Microblaze. + +.. figure:: rx.png + + HDL Block Design with Simulink HDL_DUT in Rx Configuration + +.. figure:: tx.png + + HDL Block Design with Simulink HDL_DUT in Tx Configuration + +.. figure:: rxtx.png + + HDL Block Design with Simulink HDL_DUT in Rx-Tx Configuration + +The device digital interface is handled by specific device cores axi_ad35552r +for the DAC path and axi_ltc2387 for the ADC path. The cores are programmable +through an AXI-lite interface. Details of reference design can be found in +:ref:`Reference Design `. + +HighSpeedConverterToolbox repository supports IP Core generation flow from +MathWorks which allows for automated integration of HDL_DUT into HDL reference +designs from Analog Devices. The workflow for generating HDL_DUT codes takes +Simulink subsystems, runs HDL-Coder to generate source Verilog, and then +integrates that into a larger reference design. HDL_DUT can be integrated inside +HDL reference design in three different configurations which are Rx,Tx and +Rx-TX. Figure 19 and Figure 20 demonstrates how HDL_DUT is placed between Tx and +Rx path for these three configuration types. HDL_DUT Code Generation Workflow is +described in :ref:`Configuring Matlab guide `. + +Digital Template +---------------- + +For an example with a model that utilizes a wider sample of MATLAB Simulink +blocks in the design, the :ref:`Digital Template guide ` +includes a Simulink model and instructions on how to use it. + +Schematic, PCB Layout, Bill of Materials +---------------------------------------- + +.. admonition:: Download + + :download:`EVAL-CN0584-EBZ Design & Integration Files` + + - Schematics + - PCB Layout + - Bill of Materials + - Allegro Project + +Additional Information and Useful Links +--------------------------------------- + +- :adi:`CN0584 Circuit Note Page ` +- :adi:`ADAQ23876 Product Page ` +- :adi:`AD3552R Product Page ` +- :adi:`LTC6655 Product Page ` +- :adi:`ADR4525 Product Page ` +- :adi:`AD7291 Product Page ` +- :adi:`ADG5421F Product Page ` + +Reference Demos & Software +-------------------------- + +- `High Speed Converter Toolbox for MATLAB and Simulink `__ +- :git-repo:`pyadi-iio` +- :ref:`PyADI-IIO Installation Guide ` +- :ref:`IIO Oscilloscope Installation Guide ` +- :ref:`Kuiper Linux `__ + +Help and Support +---------------- + +For questions and more information, please visit the :ez:`/`. + +Software Reference Design +-------------------------- + +.. toctree:: + :titlesonly: + :maxdepth: 2 + :glob: + + */index \ No newline at end of file diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/input_source_dac0_cn0585.png b/docs/solutions/reference-designs/eval-cn0584-ebz/input_source_dac0_cn0585.png new file mode 100644 index 000000000..8fe97601b --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/input_source_dac0_cn0585.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:781dc67204260dbb7cadd938d709f6a45b87a72d20fcb43e2c9cd2116f3c57db +size 128032 diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/matlab-configuration/figure10.png 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b/docs/solutions/reference-designs/eval-cn0584-ebz/matlab-configuration/index.rst new file mode 100644 index 000000000..4a45f5baf --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/matlab-configuration/index.rst @@ -0,0 +1,337 @@ +.. _matlab-configuration: + +MATLAB Configuration +===================== + +Configuring Custom HDL Models using Simulink +-------------------------------------------- + +Prerequisites +~~~~~~~~~~~~~~ + +- Recommended versions: Vivado 2021.1 – Matlab 2022B_U2 +- Recommended terminal for Windows: Cygwin (https://cygwin.com) +- Make sure that the Vitis 2021.1 is installed. +- The latest branch: `https://github.com/analogdevicesinc/HighSpeedConverterToolbox/tree/cn0585_v1`_ + +Make sure that the “SoC Blockset” and “SoC Blockset Support Package for Xilinx +Devices” Add-ons are installed. + +.. figure:: socblocksetaddon.png + + SoC Blockset Add-On + +.. figure:: socblocksetsupportpackage.png + + SoC Blockset Support Package for Xilinx Devices Add-On + +Instructions to build the toolbox from terminal +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +**1.1** Make a clone of the HDL repo and checkout the desired branch + +.. code-block:: bash + + >git clone https://github.com/analogdevicesinc/HighSpeedConverterToolbox.git + > cd HighSpeedConverterToolbox + ../HighSpeedConverterToolbox> git submodule update --init --recursive + ../HighSpeedConverterToolbox > git checkout cn0585_v1 + +To avoid tool mismatches, before opening MATLAB set this variable in the +terminal: + +.. code-block:: bash + + ../HighSpeedConverterToolbox> export ADI_IGNORE_VERSION_CHECK=TRUE + +Build according to the branch + +.. code-block:: bash + + ../HighSpeedConverterToolbox > cd CI/scripts + ../HighSpeedConverterToolbox/CI/scripts > make build HDLBRANCH=cn0585_v1 + +**1.2** In Matlab current folder list, navigate to the folder where +the files had been copied from previous step. Launch MATLAB in the root of the +HighSpeedConverterToolbox folder: + +.. code-block:: bash + + ../HighSpeedConverterToolbox/CI/scripts > cd ../../ + ../HighSpeedConverterToolbox > matlab . + +Creating BOOT.BIN from Simulink Model +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. figure:: figure3.png + + HighSpeedConverterToolbox Sources + +**2.1** Right click on test -> Add to Path -> Selected folders and subfolders. +Right click on hdl -> Add to Path -> Selected folders and subfolders. + +**2.2** In the Matlab command window set the path to Vivado installation folder. The tool +path should be replaced with the user’s Vivado path. + +For example: + +.. code-block:: matlab + + hdlsetuptoolpath(‘ToolName’, ‘Xilinx Vivado’, ’ToolPath’, + ‘’) + +**2.3** Expand the test folder and double click on the desired Simulink test +model, as shown in Figure 4. + +.. figure:: figure4.png + + Simulink Test Model + +**2.4** After opening the Simulink model, right click on the ``HDL_DUT`` and launch +the HDL Workflow Advisor as shown in Figure 5, and Figure 6. + +.. figure:: figure6.png + + Simulink Device Under Test + +.. figure:: figure5.png + + HDL Workflow Advisor Launching + +**2.5** Close this expected warning that will appear, as shown in Figure 7. + +.. figure:: figure7.png + + Expected HDL Workflow Advisor Warning + +**2.6** Select IP Core Generation, choose the desired project and carrier from +the dropdown list and check the Allow unsupported version box. Change the +project folder name if desired. Finally press the ``Run this Task`` button. + +.. figure:: figure8.png + + Set Target Device and Synthesis Tool + +**2.7** Choose the RX, RX-TX or TX configuration, then run the task. + +.. figure:: figure9.png + + Set Target Reference Design + +**2.8** Assign the data ports as described in Figure 10 and Figure 11, add as +many Input/Output registers as you need. Figure 9 and Figure 10 shows data ports +for TX configuration address. + +.. figure:: figure10.png + + Set Input Target Interface + +.. figure:: figure11.png + + Set Output Target Interface + +For RX and RX-TX port assignment is done similarly according to Table 2 and Table 3. +Table 1 shows port descriptions for HDL DUT Tx Reference Design. + +AXI registers are defined in the Simulink model as input or +output ports (AXI-lite option is selected in “Target Platform Interfaces” +column. Register addresses are set in “Interface Mapping” column and written +like x”<100, or another 9-bit hex address>”.) AXI registers that are input ports +are write-only, and AXI registers that are output ports are read-only. If you +connect those two together in the model, you now have a read-only register +connected to the write-only register so it is readable, but at a different address. + +.. figure:: table1.png + + HDL DUT Ports for Transmit Reference Design (Tx) + +.. figure:: table2.png + + HDL DUT Ports for Receive Reference Design (Rx) + +.. figure:: table3.png + + HDL DUT Ports for Receive-Transmit Reference Design (Rx-Tx) + +- The CN0585 ADC DATA IN is the data in offset binary format captured by the + ADC interface IP. IP sends the data at a variable sample rate (default is + 15MHz but can be changed using the IIO Oscilloscope/ Python) along with the + validIn signal which has the logic value 1 for a clock period (8.33ns) when + the data has changed. + +- IP DATA OUT is the data in offset binary format sent to the DAC interface IP. + Data must be sent at 15MSPS when both channels are enabled or at 30MSPS + when only one channel is enabled. The validOut signal should have the same + behavior as validIn. If you make changes to the data captured by the adc + (delay for 1 clock period) and want to send it to the dac output, make sure + you delay the validOut signal at the same time. If the feedback resistors are + placed in the default position, which is +/-10V, a 0000h code will represent + -10.382V and a ffffh code will represent 10.380V as described in Table 4. + +.. figure:: table4.png + + AD3552R DAC Output Span Configuration + +**2.9** Run the task, as shown in Figure 12. + +.. figure:: figure12.png + + Check Model Settings + +**2.10** Select Verilog for the HDL Code Generation Settings, then run task as +shown in Figure 13. + +.. figure:: figure13.png + + Set HDL Options + +**2.11** Check the Enable readback on AXI4 slave write registers as described in +Figure 14. Then run task. + +.. figure:: figure14.png + + Generate RTL code and IP Core + +**2.12** Run the task (this will create the Vivado block design in the +hdl_prj/vivado_ip_prj folder, or the project folder name that was chosen in +1.6), as shown in Figure 15. + +.. figure:: figure15.png + + Create Project + +**2.13** Run the task in Figure 16. + +.. figure:: figure16.png + + Generate Software Interface + +**2.14** Choose the “Custom” option for the Tcl file synthesis build, then +Browse for the adi_build.tcl file located under HighSpeedConverterToolbox/CI/scripts, +as shown in Figure 17. A bash prompt will open, and you can see the entire build process log file, +as shown in Figure 17 and Figure 18. This step usually takes about an hour or more. + +.. figure:: figure17.png + + Build FPGA Bitstream + +.. figure:: figure18.png + + Build FPGA Bitstream Task Complete Message + +In the end you will get this message, and the generated BOOT.BIN file will be +located in: + + :: + + /HighSpeedConverterToolbox/hdl_prj/vivado_ip_prj/boot + +**2.15** Program target device + +Tab 4.4 in the HDL Workflow Advisor is incompatible with The ADI SD card flow. +Instead, choose one of the following methods to update the BOOT.BIN file on the +SD card (BOOT.BIN with register access found in :download:`SD Card Configuration Files`). +After the BOOT.BIN file is generated, you have 2 options: + + #. Copy the BOOT.BIN file on the SD Card directly. + + #. Send it via network using a terminal (CMD for Windows machine). + + #. Go to the folder where the BOOT.BIN file is: + + :: + + HighSpeedConverterToolbox/hdl_prj/vivado_ip_prj/boot + + #. Run this command: + + :: + + scp BOOT.BIN root@:/boot + + #. Finally, reboot the board. + +Register Access Options +~~~~~~~~~~~~~~~~~~~~~~~ + +AXI-Lite registers in HDL_DUT can be accessed using one of the below three +options: + +PyADI-IIO +^^^^^^^^^ + +Get the PyADI-IIO repo, and switch to the compatible branch. + +.. code-block:: bash + + git clone https://github.com/analogdevicesinc/pyadi-iio.git + cd pyadi-iio  + git checkout cn0585_v1     + +Setup Python and run the example file. The path in the first line should be +replaced with the location where you cloned the pyadi-iio repository. + +.. code-block:: python + + export PYTHONPATH=C:/work/python_LLDK/documentation_clone/pyadi-iio/  + > ../pyadi-iio > pip install .  + > ../pyadi-iio > pip install -r requirements.txt  + > ../pyadi-iio > pip install -r requirements_dev.txt  + > ../pyadi-iio> python examples/cn0585_fmcz_example.py ip: + +The console output will contain these 2 new lines: + +:: + + AXI4-Lite 0x108 register value: 0x2 + AXI4-Lite 0x10c register value: 0xB + +These are the functions that were added to be able to access the HDL_DUT IP +registers trough AXI4-Lite: + +:: + + if hdl_dut_write_channel.check_matlab_ip() : + hdl_dut_write_channel.axi4_lite_register_write(0x100, 0x2) + hdl_dut_write_channel.axi4_lite_register_write(0x104, 0xB) + + if hdl_dut_write_channel.check_matlab_ip() : + reg_value = hdl_dut_read_channel.axi4_lite_register_read(0x108) + reg_value1 = hdl_dut_read_channel.axi4_lite_register_read(0x10C) + print("AXI4-Lite 0x108 register value:", reg_value) + print("AXI4-Lite 0x10c register value:", reg_value1) + +MATLAB +^^^^^^ + +- Open the CN0585StreamingTest.m file in Matlab +- Update the board_ip variable with your board IP. +- Run the CN0585StreamingTest.m example. + The output shown in Figure 19 can be observed in the Command Window. + + .. figure:: figure19.png + + MATLAB Command Window Output + + These are the functions that were added to be able to access the HDL DUT IP + registers trough AXI4-Lite: + + .. code-block:: matlab + + write_reg = soc.libiio.aximm.WriteHost(devName='mwipcore0:mmwrchannel0',IPAddress=board_ip); + read_reg = soc.libiio.aximm.WriteHost(devName='mwipcore0:mmrdchannel1',IPAddress=board_ip); + write_reg.writeReg(hex2dec('100'),85) + write_reg.writeReg(hex2dec('104'),22) + +Simulink +^^^^^^^^ + +- From the HighSpeedConverterToolbox/test folder open the + cn0585_host_axi4_lite_read_write_example.slx file. +- Update the IP address for all the blocks existing in the host diagram. +- Modify the value in the constant block to write to the register. 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/dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/tx.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3becbd5f1c3bd393d303a5eee819fba226da5794b7d70b2632723adef6032994 +size 128996 diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/zed_jumpers.jpg b/docs/solutions/reference-designs/eval-cn0584-ebz/zed_jumpers.jpg new file mode 100644 index 000000000..1fbc92301 --- /dev/null +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/zed_jumpers.jpg @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8bf0303dc3973a1c20043f8da94967aa0aba3973a40393e5974efd93be84724a +size 136812 From 3af8e01606bfbab75265d69a7d82b1a62c766193 Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Mon, 4 Aug 2025 18:42:11 +0200 Subject: [PATCH 2/3] review: solutions: reference designs: Added CN0584 pages Fix references, ensure they are unique, use shell, whitespace, remove duplicated hdl page Signed-off-by: Jorge Marques --- docs/software/matlab/hsx-toolbox/index.rst | 2 + .../matlab/transceiver-toolbox/index.rst | 2 + .../HDL-project/cn0585_hdl_diagram.svg | 3867 ----------------- .../eval-cn0584-ebz/HDL-project/index.rst | 100 - .../digital-template/index.rst | 28 +- .../eval-cn0584-ebz/index.rst | 192 +- .../matlab-configuration/index.rst | 84 +- 7 files changed, 158 insertions(+), 4117 deletions(-) delete mode 100644 docs/solutions/reference-designs/eval-cn0584-ebz/HDL-project/cn0585_hdl_diagram.svg delete mode 100644 docs/solutions/reference-designs/eval-cn0584-ebz/HDL-project/index.rst diff --git a/docs/software/matlab/hsx-toolbox/index.rst b/docs/software/matlab/hsx-toolbox/index.rst index abc276d2a..2a9f0848f 100644 --- a/docs/software/matlab/hsx-toolbox/index.rst +++ b/docs/software/matlab/hsx-toolbox/index.rst @@ -1,3 +1,5 @@ +.. _hsx-toolbox: + High Speed Converter Toolbox ============================ diff --git a/docs/software/matlab/transceiver-toolbox/index.rst b/docs/software/matlab/transceiver-toolbox/index.rst index d8545d4aa..02cfeb915 100644 --- a/docs/software/matlab/transceiver-toolbox/index.rst +++ b/docs/software/matlab/transceiver-toolbox/index.rst @@ -1,3 +1,5 @@ +.. _matlab transceiver-toolbox: + Transceiver Toolbox =================== diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/HDL-project/cn0585_hdl_diagram.svg b/docs/solutions/reference-designs/eval-cn0584-ebz/HDL-project/cn0585_hdl_diagram.svg deleted file mode 100644 index 36d333d3b..000000000 --- a/docs/solutions/reference-designs/eval-cn0584-ebz/HDL-project/cn0585_hdl_diagram.svg +++ /dev/null @@ -1,3867 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Ethernet - UART - DDRx - SPI - I2C - Interrupts - - Timer - - - MEMORY INTERCONNECT - Zed - - - FMC CONNECTOR - - - - - DAC_DMA - ADC_CPACK - ADC_DMA - (15/60MHz) - - - - - ARM (Zynq) - Zynq SoC - - - - - AD3552R CORE - CS - 4xSDIO - SCLK - - - - - - - - - AD3552R_IF - AXI REGMAP - - - - - - - - - AXI PWMGEN - AXI CLKGEN - 100MHz - 120MHz - - - - LVDS INTERFACE - - - DAC core frame - - - DAC core frame - - - DAC core frame - - - DAC core frame - - LTC2387 CORE - - - - DA - - - - - DCO - - - - - DB - - CLK_GATE - CNV - LTC_CLK - RX_CLK_P - RX_CLK_N - pwm_0 - pwm_1 - pwm_2 - pwm_3 - - - - - - PNMONITORING - - - - - - - - - - - - 100MHz - 120MHz - - - - - - - - - - - - - - ADC - RAMP - DDS - DMA - - - - - - - Transmit path - Recive path - PN MONITORING - - AXI CLKGEN - 100MHz - 120MHz - 120Mhz - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 32b - 32b - 64b - 64b - 16b - 16b - 16b - 16b - 32b - 32b - - - - - - - diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/HDL-project/index.rst b/docs/solutions/reference-designs/eval-cn0584-ebz/HDL-project/index.rst deleted file mode 100644 index b37c739bb..000000000 --- a/docs/solutions/reference-designs/eval-cn0584-ebz/HDL-project/index.rst +++ /dev/null @@ -1,100 +0,0 @@ -HDL Project -============ - -Introduction ------------- - -This page describes the HDL project for -:ref:`CN0584 Precision Low Latency Development Kit ` -and :ref:`CN0585 Quad Channel, Low Latency, Data Acquisition and Signal Generation Module `. - -Functional Overview -------------------- - -The HDL reference design is an embedded system built around a processor core -either ARM, NIOS-II, or Microblaze. A functional block diagram of the system -is shown below. The device digital interface is handled by specific device -cores :git-repo:`axi_ad35552r ` -for the DAC path and :git-repo:`axi_ltc2387 ` -for the ADC path. The cores are programmable through an AXI-lite interface. - -.. figure:: cn0585_hdl_diagram.svg - -Digital Interface ------------------ - -The digital interface consists of a Quad SPI port running at 15/60MHz depending -on the FSM state (control/stream) for the DAC path and 3 LVDS serial pairs for -the ADC path. The clock signals are generated by the AXI_PWM_GEN and AXI_CLKGEN -IP cores. - -DAC Interface -------------- - -The DAC data may be sourced from an internal data generator (DDS or pattern), -from the external DDR via DMA or from the ADC. The source control selection can -be made by updating the `REG_CHAN_CNTRL_7 (DAC Channel) ` -register. - -ADC Interface -------------- - -The ADC data is sent to DDR via DMA. The ADC PACK IP (util_cpack) allows the use -of a single DMA IP core for all four analog-to-digital converters. - -Control and SPI ---------------- - -The SPI signals of the ADC are controlled by the SPI port of the ARM processor. - -The DAC’s control is performed by the :git-repo:`axi_ad35552r ` -IP core. - -Download --------- - -.. admonition:: Download - - The HDL repository, list of supported carriers, and the list of required IP - cores can be found here: - - - Hardware: :adi:`EVAL-CN0585-FMCZ ` - - HDL Project: `hdl_cn0585 `_ - - Carriers: `zed `_ - - Library Cores: - - - `axi_clkgen `_ - - `axi_dmac `_ - - `axi_hdmi_tx `_ - - `axi_i2s_adi `_ - - `axi_ltc2387 `_ - - `axi_ad3552r `_ - - `axi_pwm_gen `_ - - `axi_spdif_tx `_ - - `axi_sysid `_ - - `sysid_rom `_ - -Reference Demos & Software --------------------------- - -- :adi:`CN0584 Precision Low Latency Development Kit ` -- :adi:`CN0585 Quad Channel, Low Latency, Data Acquisition and Signal Generation Module ` -- :git-hdl:`AXI_AD3552R IP core ` -- :git-hdl:`AXI_LTC2387 IP core ` -- :dokuwiki:`AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Linux device driver ` -- :dokuwiki:`LTC2387 SAR ADC IIO Linux Driver ` - -Help & Support ----------------- - -The :dokuwiki:`carriers (abbreviations can be found here) ` -are commonly available FPGA evaluation boards. - -The :git-hdl:`HDL user guide ` contains all the documentation, build instructions and register map tables. - -The following quick links allows you to browse the github repository for a list of current `branches `_, -`library components `_, and `projects `_. - -Questions? We can help with `FPGA questions `_, -`Linux driver questions `_, or -`No-OS Drivers questions `_. diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/digital-template/index.rst b/docs/solutions/reference-designs/eval-cn0584-ebz/digital-template/index.rst index f2e436544..ed0dcc042 100644 --- a/docs/solutions/reference-designs/eval-cn0584-ebz/digital-template/index.rst +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/digital-template/index.rst @@ -1,6 +1,6 @@ -.. _digital-template: +.. _eval-cn0584-ebz digital-template: -Digital Template Model +Digital Template Model ======================= A digital template is provided as a starting point for designs. There are four @@ -9,12 +9,12 @@ controller. Python scripts are provided that showcase each subsystem. These scripts are designed to run with the ADCs and DACs connected in loopback mode, as described -in the example :ref:`Setting Up the Hardware Section `, +in the example :ref:`Setting Up the Hardware Section `, and shown in the following image. .. figure:: cn0584_loopback_connection.png - EVAL-CN0585-FMCZ with loopback connection + EVAL-CN0585-FMCZ with loopback connection The additional packages required to run these scripts are: scipy.fft, scipy.signal. @@ -43,16 +43,16 @@ Files ~~~~~ The simulink model files can be downloaded from this zip file -:download:`Simulink models` and placed in the +:download:`Simulink models ` and placed in the HighSpeedConverterToolbox/test folder. The PID and DDS are submodels within the top level testModel_template_top.slx file, and the path pointing to the -submodels should be updated to reflect the new correct path on the user’s -machine. See the Build section at the bottom of this page for instructions on +submodels should be updated to reflect the new correct path on the user's +machine. See the Build section at the bottom of tutorial for instructions on implementing the model. Additionally, the bootfile is provided here :download:`Boot file` and can be copied directly into the boot directory of the SD card. The Python example scripts can be downloaded from this zip file -:download:`Python Examples`, and placed in the +:download:`Python Examples `, and placed in the pyadi-iio/examples folder while in the cn0585_v1 branch. The following sections describe the model and scripts in more detail. @@ -131,7 +131,7 @@ from 0 to 1000000 in steps of 1, the units are Hertz. The *amp* variable controls the amplitude of the sine wave, in units of DAC codes, with a maximum value of 32767, or 2^15-1, in steps of 1. The conversion between DAC codes and voltage can be found on the :adi:`AD3552R` datasheet. The *phase_shift* offsets -the sine wave phase, from -360 to 360 in steps of 1, in units of degrees. +the sine wave phase, from -360 to 360 in steps of 1, in units of degrees. The *external_signals* variable should be set to 0 when the ADCs and DACs are connected in loopback mode, and set to 1 when the signals are being driven and measured with external devices. See following section for more @@ -197,7 +197,7 @@ The below window will pop up. The first plot shows the DDS output captured on ADC3, and the second plot shows the input on ADC0. The final two plots show the mixer output looped back and captured from ADC2, and its FFT transformation. -.. figure:: dt_mixer_plot.png +.. figure:: dt_mixer_plot.png Mixer inputs from DDS and ADC0 (top 2 graphs), Mixer out and its FFT (bottom 2 graphs) @@ -385,7 +385,7 @@ The terminal output should resemble the following. Register value for kd: 10 decimal value: 0.009765625 And the window with the below plots should pop up. The input to the set point is -displayed on top graph, it’s a 500Hz square wave with -/+4V amplitude. The +displayed on top graph, it's a 500Hz square wave with -/+4V amplitude. The bottom graph is the feedback which resembles the set point with some overshoot feature and small latency. @@ -414,7 +414,7 @@ decimal bits. # user inputs Kp = 1 Ki = 0.2 - Kd = 0.01 + Kd = 0.01 Build ----- @@ -422,8 +422,8 @@ Build After the HighSpeedConvertToolbox repo is set up on the machine as described in the Matlab Configuration Guide page of the wiki and the digital template models have been put in the correct folder, the Simulink model can be opened and built. -This mostly follows the step on `this page `_, -but a few changes are required. +This mostly follows the step on :ref:`matlab-configuration`, but a few changes +are required. Before starting the build process, go to Configuration Parameters -> HDL Code Generation -> Global Settings and set the Reset Type to Synchronous. diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/index.rst b/docs/solutions/reference-designs/eval-cn0584-ebz/index.rst index a490bc7fe..6494f7386 100644 --- a/docs/solutions/reference-designs/eval-cn0584-ebz/index.rst +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/index.rst @@ -16,11 +16,11 @@ Overview CN0584 Low Latency Development Kit The :adi:`CN0584` Low Latency Development Kit is a development platform consisting of two -boards the :adi:`EVAL-CN0585-FMCZ ` and the :adi:`EVAL-CN0584-EBZ `. +boards the :adi:`EVAL-CN0585-FMCZ ` and the :adi:`EVAL-CN0584-EBZ `. -:adi:`EVAL-CN0585-FMCZ ` consists of 4 x 16-bit ADC channels and -4 x 16-bit DAC channels that are interfaced with an FPGA through the -FMC Low Pin Count (LPC) Connector. Current revision of :adi:`EVAL-CN0585-FMCZ ` +:adi:`EVAL-CN0585-FMCZ ` consists of 4 x 16-bit ADC channels and +4 x 16-bit DAC channels that are interfaced with an FPGA through the +FMC Low Pin Count (LPC) Connector. Current revision of :adi:`EVAL-CN0585-FMCZ ` is Rev B. :adi:`EVAL-CN0584-EBZ ` is the application specific analog front end (AFE) board. CN0584 is connected to a Zedboard to build a development system setup. @@ -38,7 +38,7 @@ Connections and Configurations ------------------------------ .. figure:: hil_cn0584_personalityboard_top-web.jpg - + EVAL-CN0584-EBZ Board .. figure:: 001.svg @@ -142,7 +142,7 @@ LLDK can support multiple output voltage ranges which can be configured, such as 0V to 2.5V, 0V to 5V, −5V to +5V, and −10V to +10V, and custom intermediate ranges with full 16-bit resolution. In order to change the output range, resistor placements on the AFE board must be modified and register -settings must be applied to :adi:`AD3552R` on :adi:`EVAL-CN0585-FMCZ ` +settings must be applied to :adi:`AD3552R` on :adi:`EVAL-CN0585-FMCZ ` as described in Table 4. .. table:: DAC Output Signal Connectors @@ -271,11 +271,11 @@ Power Supply Considerations and Configuration All power for CN0584 is provided by :adi:`EVAL-CN0585-FMCZ ` through the analog front end (AFE) connector. CN0584 uses the +15V and -15V rails to provide the positive -and negative supply voltages for the :adi:`ADG5421F` input protection switches. The +12V and -12V rails -provide the positive and negative supply voltages for the :adi:`ADA4898-1` ADC buffer amplifiers. -The +3.3V rail powers the EEPROM circuit. +and negative supply voltages for the :adi:`ADG5421F` input protection switches. The +12V and -12V rails +provide the positive and negative supply voltages for the :adi:`ADA4898-1` ADC buffer amplifiers. +The +3.3V rail powers the EEPROM circuit. -Power tree information can be found in :adi:`EVAL-CN0585-FMCZ `. +Power tree information can be found in :adi:`EVAL-CN0585-FMCZ `. Table 6 provides more details on LLDK power rails: .. table:: Power Rail Descriptions @@ -296,18 +296,18 @@ System Setup Using a ZedBoard CN0584 is fully supported using a ZedBoard. .. figure:: eval-cn0585-fmcz_kit_top.jpg - + EVAL-CN0585-FMCZ revB connected to EVAL-CN0584-EBZ .. figure:: eval-cn0585-fmcz_angle-web.jpg - + EVAL-CN0585-FMCZ revB The following is a list of items needed for system setup: - **Hardware** - - :adi:`EVAL-CN0585-FMCZ(RevB) ` + - :adi:`EVAL-CN0585-FMCZ(RevB) ` (Note: Figure 4 features EVAL-CN0585-FMCZ RevA board. Current LLDK system has RevB board shown in Figure 5, same connectors and functionalities, only different in USB-C power supply.) - :adi:`EVAL-CN0584-EBZ ` @@ -325,32 +325,32 @@ The following is a list of items needed for system setup: - **Software** - Host PC (Windows or Linux) - - A UART terminal if need to access Linux system on the ZedBoard + - A UART terminal if need to access Linux system on the ZedBoard (Putty/TeraTerm/Minicom, etc.), Baud rate 115200 (8N1) - - :ref:`IIO Oscilloscope ` - - `Kuiper Linux `__ + - :ref:`iio-oscilloscope` + - :ref:`kuiper` Loading Image on SD Card ~~~~~~~~~~~~~~~~~~~~~~~~ The box includes a pre-programmed SD card. You can skip the steps in this -section and go to the :ref:`Setting Up the Hardware Section ` -if using the provided card. +section and go to the :ref:`eval-cn0584-ebz setting-up-the-hardware` if using +the provided card. To boot the ZedBoard and control the :adi:`EVAL-CN0585-FMCZ `, you will need to install ADI Kuiper Linux on an SD card. Complete instructions, including where to download the SD card image, how to write it to the SD card, and how to -configure the system are provided on the `Kuiper Linux page `__. +configure the system are provided on the :ref:`kuiper`. Configuring the SD Card ~~~~~~~~~~~~~~~~~~~~~~~ -Follow the configuration procedure under **Configuring the SD Card for FPGA Projects** -on the `Kuiper Linux page `__ page. +Follow the configuration procedure under **Configuring the SD Card for FPGA Projects** +on :ref:`kuiper`. Copy the following files onto the boot directory to configure the SD card: -.. admonition:: Download +.. admonition:: Download for :download:`EVAL-CN0585-FMCZ RevB` @@ -359,8 +359,8 @@ Copy the following files onto the boot directory to configure the SD card: - **uImage** file for Zynq - **BOOT.BIN** specific to your :adi:`EVAL-CN0585-FMCZ ` + ZedBoard - **setup_adc.sh** file for setting up ADC -- **devicetree.dtb** devicetree for Zynq specific to your :adi:`EVAL-CN0585-FMCZ ` + ZedBoard. - +- **devicetree.dtb** devicetree for Zynq specific to your :adi:`EVAL-CN0585-FMCZ ` + ZedBoard. + The device tree describes the following devices: #. ``one-bit-adc-dac`` – controls the MAX7301 @@ -376,7 +376,7 @@ Copy the following files onto the boot directory to configure the SD card: #. ``axi_ad3552r_1`` – controls the second AD3552R device #. ``I2C`` – controls devices that are connected to PL I2C IP (eeprom, eeprom2, ad7291_1) -.. _setting_up_the_hardware: +.. _eval-cn0584-ebz setting-up-the-hardware: Setting up the Hardware ~~~~~~~~~~~~~~~~~~~~~~~~ @@ -388,13 +388,13 @@ Setting up the Hardware #. Connect micro USB to UART port (J14), and the other end to the host PC. #. Connect the ethernet cable to RJ45 ethernet connector (J11), and the other end to the host PC. -#. Plug the Power Supply into the 12V Power ZedBoard input connector (J20). +#. Plug the Power Supply into the 12V Power ZedBoard input connector (J20). **DO NOT turn the device on**. #. Plug USB-C power supply to :adi:`EVAL-CN0585-FMCZ ` (revB only). #. Set the jumpers as seen in figure below. - - .. figure:: zed_jumpers.jpg - + + .. figure:: zed_jumpers.jpg + ZedBoard Jumper Settings #. Connect the DAC output connectors to the negative ADC input connectors as @@ -402,16 +402,16 @@ Setting up the Hardware etc.). Terminate the positive ADC connectors with 50ohms SMA terminators. .. figure:: cn0584_loopback_connection.png - + EVAL-CN0584-EBZ Loopback Connection on AFE - -#. Turn the ZedBoard on. - + +#. Turn the ZedBoard on. + - Wait ~30 seconds for the “DONE” LED to turn blue. This is near the DISP1. The hardware set up is now complete. - + .. figure:: setup_cn0585_diagram.png - + Example System Setup .. esd-warning:: @@ -434,14 +434,14 @@ machine. To connect to your device, the IIO Osciloscope software must be able to create a context. The context creation in the software depends on the backend used to -connect to the device as well as the platform where the :adi:`EVAL-CN0585-FMCZ ` is attached. +connect to the device as well as the platform where the :adi:`EVAL-CN0585-FMCZ ` is attached. The ZedBoard running ADI Kuiper Linux is currently the only platform supported for the CN0585. The user needs to supply a **Uniform Resource Identifier (URI)** which will be used in the context creation. To get the URI, use the command iio_info in the -terminal. The `iio_info `__ -command is a part of the libIIO package that reports all IIO attributes. Upon -installation, simply enter the command on the terminal command line to access it. +terminal. The :ref:`libiio iio_info` command is a part of the libIIO package +that reports all IIO attributes. Upon installation, simply enter the command on +the terminal command line to access it. For FPGA (ZedBoard) Direct Local Access ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -463,7 +463,7 @@ Example: * If your ZedBoard has the IP address 169.254.92.202, you have to use //iio_info -u ip::169.254.92.202// as your URI -.. note:: +.. note:: Do note that the Windows machine and the FPGA board should be connected to the same network for the machine to detect the device. @@ -474,8 +474,8 @@ IIO Oscilloscope is a cross platform GUI application which can interface with different evaluation boards from within a Linux system. -.. important:: - Make sure to download/update to the latest version of +.. important:: + Make sure to download/update to the latest version of :git-iio-oscilloscope:`IIO Oscilloscope `. #. Once done with the installation or an update of the latest IIO Oscilloscope, @@ -483,8 +483,8 @@ evaluation boards from within a Linux system. context creation of the IIO Oscilloscope. If there’s only one platform is connected, the IIO Oscilloscope will find URI automatically; if more than one platforms are connected, the user needs to supply the specific URI. The - instructions to obtain the URI can be found in the previous section. - + instructions to obtain the URI can be found in the previous section. + **Note: the “Serial Context” connection method is not enabled.** #. Press ``Refresh`` to display available IIO Devices and press ``Connect``. @@ -495,12 +495,12 @@ evaluation boards from within a Linux system. #. After the board is connected, select the **one-bit-adc-dac-device**, which is the controller for the MAX7301ATL+ I/O Expander. Then, configure pins values of - output voltages 0 through 9, by setting the **raw value to 1**. - + output voltages 0 through 9, by setting the **raw value to 1**. + Press **Write** to confirm. .. figure:: max7301atl_output_channels_configuration.png - + MAX7301ATL Output Channels Configuration .. table:: Voltage Configuration for GPIO Pins @@ -525,41 +525,41 @@ evaluation boards from within a Linux system. | Voltage7 | PAD_ADC1 | +----------------------------------+---------------------------------+ | Voltage8 | PAD_ADC2 | - +----------------------------------+---------------------------------+ + +----------------------------------+---------------------------------+ | Voltage9 | PAD_ADC3 | +----------------------------------+---------------------------------+ - + #. Input sources for AD3552R devices axi-ad3552r-0 and axi-ad3552r-1 can be configured as dma_input, ramp_input, or adc_input. - **dma_input:** DAC input is driven by signals generated by Matlab stored in DMA. - **ramp_input:** DAC input is driven by ramp signal generated by Matlab stored in DMA. - - **adc_input:** For passthrough models, DAC input is driven by ADC output. + - **adc_input:** For passthrough models, DAC input is driven by ADC output. For models with integrated HDL_DUT, DAC input is driven by HDL_DUT outputs. Select the desired input source for both AD3552R devices axi-ad3552r-0 and - axi-ad3552r-1 as dma_input. - + axi-ad3552r-1 as dma_input. + .. figure:: input_source_dac0_cn0585.png - + AD3552R Input Source Selection in IIO Oscilloscope - .. important:: + .. important:: Even if the input source is set to adc_input or ramp_input the steps regarding the DAC Data Manager tab have to be followed. #. Select the desired output range for both AD3552R devices. .. figure:: output_range_cn0585.png - + AD3552R Output Range Selection in IIO Oscilloscope - - .. warning:: - Make sure you don’t try to read/write the output_range attribute - when the stream_status is in start_stream or start_stream_synced. - - .. important:: - After changing the output range, the board should be power cycled + + .. warning:: + Make sure you don’t try to read/write the output_range attribute + when the stream_status is in start_stream or start_stream_synced. + + .. important:: + After changing the output range, the board should be power cycled to ensure the DACs operate properly. #. From the DAC Data Manager Window select the output channels of the DAC and @@ -568,30 +568,30 @@ evaluation boards from within a Linux system. #. Load an example file (.mat, .txt, etc) from the IIO Oscilloscope installation directory, under **Program Files/IIO Oscilloscope/lib/osc/waveforms** folder. - .. important:: - If the source is set as dma_input and the data from all 4 channels needs + .. important:: + If the source is set as dma_input and the data from all 4 channels needs to be synchronized, make sure that you press the load button for the axi-ad3552r-1 device first then for axi-ad3552r-0. - .. figure:: dac_data_management_cn0585.jpg - + .. figure:: dac_data_management_cn0585.jpg + DAC Data Manager with Example Waves on 4 Channels -#. Click on the ``Load`` button. +#. Click on the ``Load`` button. #. From the Debug window, select the stream_status IIO Attribute and start the stream (start_stream_synced means that all 4 channels are updated at the same time and the data streaming process waits for both DACs to be started). .. figure:: stream_status_iio.jpg - - DAC Stream Status Selection - + + DAC Stream Status Selection + #. After the stream_status has been written and 4 channels are enabled, hit play button. Then data capture window can be seen like in Figure 15. .. figure:: captured_loopback_signal_cn0585.jpg - + Captured Loopback Signal .. important:: @@ -599,7 +599,7 @@ evaluation boards from within a Linux system. voltage1/voltage3 because the DAC device channels are updated consecutively. See the DAC UPDATE MODES section of the :adi:`AD3552R Data Sheet `. - .. warning:: + .. warning:: If you intend to stop the stream transmission and start it again synchronized, set the stream_status IIO Attribute to stop_stream for axi-ad3552r-1 device first then for the axi-ad3552r-0 device. @@ -608,8 +608,8 @@ PyADI-IIO ~~~~~~~~~ The CN0584 can be interfaced to Python using the -:ref:`PyADI-IIO `. -PyADI-IIO is a Python abstraction module to simplify interaction with IIO drivers +:ref:`PyADI-IIO `. +PyADI-IIO is a Python abstraction module to simplify interaction with IIO drivers on ADI hardware. This module provides device-specific APIs built on top of the current libIIO Python bindings. These interfaces try to match the driver naming as much as possible without the need to understand the complexities of @@ -624,10 +624,10 @@ Running the example .. admonition:: Download - Github link for the Python sample script: - :git-pyadi-iio:`CN0585 Python Example ` + Github link for the Python sample script: + :git-pyadi-iio:`CN0585 Python Example ` -#. Download or git clone :git-pyadi-iio::`pyadi-iio repository ` to your local drive. +#. Download or git clone :git-pyadi-iio:`pyadi-iio repository ` to your local drive. - If direct downloading ZIP folder, make sure to download from cn0585_v1 branch. - If cloning the repository using `Git `__, type @@ -648,12 +648,12 @@ Running the example .. code-block:: python - D:\pyadi-iio>set PYTHONPATH=D:/pyadi-iio/ + D:\pyadi-iio>set PYTHONPATH=D:/pyadi-iio/ D:\pyadi-iio>python examples/cn0585_fmcz_example.py ip:your_board_ip Press enter and lines below will be observed: - :: + :: $ python examples/cn0585_fmcz_example.py uri: ip:your_board_ip @@ -697,7 +697,7 @@ in this configuration, the following window will pop up: ADC Captured Data Python Plot -.. important:: +.. important:: If you plan to transmit multiple cycles of synchronous stream, make sure the script starts/stops axi-ad3552r-1 first, then axi-ad3552r-0. @@ -714,11 +714,11 @@ MATLAB and Simulink - :mw:`SoC Blockset ` .. admonition:: Download - + Github link for the Matlab sample script: :git-repo:`CN0585StreamingTest.m ` -The steps described in the `Analog Devices Transceiver Toolbox For MATLAB and Simulink `__ -page have to be followed to configure the Matlab/Simulink project using the +The steps described in the `matlab tranceiver-toolbox` section have to be +followed to configure the Matlab/Simulink project using the :mw:`MathWorks HDL Workflow Advisor `. Device Control and Data Streaming @@ -737,12 +737,12 @@ example, the following steps must be completed first. #. Execute the following commands on the computer terminal (Cygwin is recommended for Windows) to set up a local git repository. - .. code-block:: bash + .. shell:: - git clone https://github.com/analogdevicesinc/HighSpeedConverterToolbox.git - cd HighSpeedConverterToolbox - git submodule update --init --recursive - git checkout cn0585_v1 + $git clone https://github.com/analogdevicesinc/HighSpeedConverterToolbox.git + $cd HighSpeedConverterToolbox + $git submodule update --init --recursive + $git checkout cn0585_v1 #. Open Matlab from the HighSpeedConverterToolbox directory. @@ -751,7 +751,7 @@ example, the following steps must be completed first. The DAC outputs should be looped back into the ADCs as shown in figure 6 in the System Setup Using a ZedBoard section. After running the script with the board -in this configuration, the window in Figure 17 will pop up. +in this configuration, the window in Figure 17 will pop up. .. figure:: matlab_plot.jpg @@ -785,8 +785,8 @@ Microblaze. The device digital interface is handled by specific device cores axi_ad35552r for the DAC path and axi_ltc2387 for the ADC path. The cores are programmable -through an AXI-lite interface. Details of reference design can be found in -:ref:`Reference Design `. +through an AXI-lite interface. Details of reference design can be found in the +:external+hdl:ref:`HDL Reference Design `. HighSpeedConverterToolbox repository supports IP Core generation flow from MathWorks which allows for automated integration of HDL_DUT into HDL reference @@ -802,7 +802,7 @@ Digital Template ---------------- For an example with a model that utilizes a wider sample of MATLAB Simulink -blocks in the design, the :ref:`Digital Template guide ` +blocks in the design, the :ref:`eval-cn0584-ebz digital-template` includes a Simulink model and instructions on how to use it. Schematic, PCB Layout, Bill of Materials @@ -831,11 +831,11 @@ Additional Information and Useful Links Reference Demos & Software -------------------------- -- `High Speed Converter Toolbox for MATLAB and Simulink `__ +- :ref:`hsx-toolbox` - :git-repo:`pyadi-iio` -- :ref:`PyADI-IIO Installation Guide ` -- :ref:`IIO Oscilloscope Installation Guide ` -- :ref:`Kuiper Linux `__ +- :ref:`pyadi-iio` +- :ref:`iio-oscilloscope` +- :ref:`kuiper` Help and Support ---------------- diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/matlab-configuration/index.rst b/docs/solutions/reference-designs/eval-cn0584-ebz/matlab-configuration/index.rst index 4a45f5baf..57c2ddfe9 100644 --- a/docs/solutions/reference-designs/eval-cn0584-ebz/matlab-configuration/index.rst +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/matlab-configuration/index.rst @@ -1,6 +1,6 @@ .. _matlab-configuration: -MATLAB Configuration +MATLAB Configuration ===================== Configuring Custom HDL Models using Simulink @@ -12,10 +12,10 @@ Prerequisites - Recommended versions: Vivado 2021.1 – Matlab 2022B_U2 - Recommended terminal for Windows: Cygwin (https://cygwin.com) - Make sure that the Vitis 2021.1 is installed. -- The latest branch: `https://github.com/analogdevicesinc/HighSpeedConverterToolbox/tree/cn0585_v1`_ +- The latest branch: :git-HighSpeedConverterToolbox:`cn0585_v1:` Make sure that the “SoC Blockset” and “SoC Blockset Support Package for Xilinx -Devices” Add-ons are installed. +Devices” Add-ons are installed. .. figure:: socblocksetaddon.png @@ -30,35 +30,38 @@ Instructions to build the toolbox from terminal **1.1** Make a clone of the HDL repo and checkout the desired branch -.. code-block:: bash +.. shell:: - >git clone https://github.com/analogdevicesinc/HighSpeedConverterToolbox.git - > cd HighSpeedConverterToolbox - ../HighSpeedConverterToolbox> git submodule update --init --recursive - ../HighSpeedConverterToolbox > git checkout cn0585_v1 + $git clone https://github.com/analogdevicesinc/HighSpeedConverterToolbox.git + $cd HighSpeedConverterToolbox + $git submodule update --init --recursive + $git checkout cn0585_v1 To avoid tool mismatches, before opening MATLAB set this variable in the terminal: -.. code-block:: bash +.. shell:: - ../HighSpeedConverterToolbox> export ADI_IGNORE_VERSION_CHECK=TRUE + ~/HighSpeedConverterToolbox + $export ADI_IGNORE_VERSION_CHECK=TRUE Build according to the branch -.. code-block:: bash +.. shell:: - ../HighSpeedConverterToolbox > cd CI/scripts - ../HighSpeedConverterToolbox/CI/scripts > make build HDLBRANCH=cn0585_v1 + ~/HighSpeedConverterToolbox + $cd CI/scripts + $make build HDLBRANCH=cn0585_v1 **1.2** In Matlab current folder list, navigate to the folder where the files had been copied from previous step. Launch MATLAB in the root of the HighSpeedConverterToolbox folder: -.. code-block:: bash +.. shell:: - ../HighSpeedConverterToolbox/CI/scripts > cd ../../ - ../HighSpeedConverterToolbox > matlab . + ~/HighSpeedConverterToolbox/CI/scripts + $cd ../../ + $matlab . Creating BOOT.BIN from Simulink Model ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -68,7 +71,7 @@ Creating BOOT.BIN from Simulink Model HighSpeedConverterToolbox Sources **2.1** Right click on test -> Add to Path -> Selected folders and subfolders. -Right click on hdl -> Add to Path -> Selected folders and subfolders. +Right click on hdl -> Add to Path -> Selected folders and subfolders. **2.2** In the Matlab command window set the path to Vivado installation folder. The tool path should be replaced with the user’s Vivado path. @@ -78,10 +81,10 @@ For example: .. code-block:: matlab hdlsetuptoolpath(‘ToolName’, ‘Xilinx Vivado’, ’ToolPath’, - ‘’) + ‘’) **2.3** Expand the test folder and double click on the desired Simulink test -model, as shown in Figure 4. +model, as shown in Figure 4. .. figure:: figure4.png @@ -130,8 +133,8 @@ for TX configuration address. Set Output Target Interface -For RX and RX-TX port assignment is done similarly according to Table 2 and Table 3. -Table 1 shows port descriptions for HDL DUT Tx Reference Design. +For RX and RX-TX port assignment is done similarly according to Table 2 and Table 3. +Table 1 shows port descriptions for HDL DUT Tx Reference Design. AXI registers are defined in the Simulink model as input or output ports (AXI-lite option is selected in “Target Platform Interfaces” @@ -207,8 +210,8 @@ hdl_prj/vivado_ip_prj folder, or the project folder name that was chosen in Generate Software Interface **2.14** Choose the “Custom” option for the Tcl file synthesis build, then -Browse for the adi_build.tcl file located under HighSpeedConverterToolbox/CI/scripts, -as shown in Figure 17. A bash prompt will open, and you can see the entire build process log file, +Browse for the adi_build.tcl file located under HighSpeedConverterToolbox/CI/scripts, +as shown in Figure 17. A bash prompt will open, and you can see the entire build process log file, as shown in Figure 17 and Figure 18. This step usually takes about an hour or more. .. figure:: figure17.png @@ -230,7 +233,7 @@ located in: Tab 4.4 in the HDL Workflow Advisor is incompatible with The ADI SD card flow. Instead, choose one of the following methods to update the BOOT.BIN file on the -SD card (BOOT.BIN with register access found in :download:`SD Card Configuration Files`). +SD card (BOOT.BIN with register access found in :download:`SD Card Configuration Files`). After the BOOT.BIN file is generated, you have 2 options: #. Copy the BOOT.BIN file on the SD Card directly. @@ -247,7 +250,7 @@ After the BOOT.BIN file is generated, you have 2 options: :: - scp BOOT.BIN root@:/boot + scp BOOT.BIN root@:/boot #. Finally, reboot the board. @@ -262,29 +265,30 @@ PyADI-IIO Get the PyADI-IIO repo, and switch to the compatible branch. -.. code-block:: bash +.. shell:: - git clone https://github.com/analogdevicesinc/pyadi-iio.git - cd pyadi-iio  - git checkout cn0585_v1     + $git clone https://github.com/analogdevicesinc/pyadi-iio.git + $cd pyadi-iio  + $git checkout cn0585_v1     Setup Python and run the example file. The path in the first line should be replaced with the location where you cloned the pyadi-iio repository. -.. code-block:: python +.. shell:: ps1 - export PYTHONPATH=C:/work/python_LLDK/documentation_clone/pyadi-iio/  - > ../pyadi-iio > pip install .  - > ../pyadi-iio > pip install -r requirements.txt  - > ../pyadi-iio > pip install -r requirements_dev.txt  - > ../pyadi-iio> python examples/cn0585_fmcz_example.py ip: + ~/pyadi-iio + export PYTHONPATH=C:\work\python_LLDK\documentation_clone\pyadi-iio + $pip install .  + $pip install -r requirements.txt  + $pip install -r requirements_dev.txt  + $python examples/cn0585_fmcz_example.py ip: The console output will contain these 2 new lines: :: - AXI4-Lite 0x108 register value: 0x2 - AXI4-Lite 0x10c register value: 0xB + AXI4-Lite 0x108 register value: 0x2 + AXI4-Lite 0x10c register value: 0xB These are the functions that were added to be able to access the HDL_DUT IP registers trough AXI4-Lite: @@ -318,9 +322,9 @@ MATLAB .. code-block:: matlab - write_reg = soc.libiio.aximm.WriteHost(devName='mwipcore0:mmwrchannel0',IPAddress=board_ip); - read_reg = soc.libiio.aximm.WriteHost(devName='mwipcore0:mmrdchannel1',IPAddress=board_ip); - write_reg.writeReg(hex2dec('100'),85) + write_reg = soc.libiio.aximm.WriteHost(devName='mwipcore0:mmwrchannel0',IPAddress=board_ip); + read_reg = soc.libiio.aximm.WriteHost(devName='mwipcore0:mmrdchannel1',IPAddress=board_ip); + write_reg.writeReg(hex2dec('100'),85) write_reg.writeReg(hex2dec('104'),22) Simulink From e8c116f9c756d2423257eae0d3c0fefccde7d07c Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Mon, 4 Aug 2025 19:01:41 +0200 Subject: [PATCH 3/3] review: solutions: reference designs: Added CN0584 pages Make matlab-configuration ref unique. Signed-off-by: Jorge Marques --- .../eval-cn0584-ebz/digital-template/index.rst | 4 ++-- docs/solutions/reference-designs/eval-cn0584-ebz/index.rst | 2 +- .../eval-cn0584-ebz/matlab-configuration/index.rst | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/digital-template/index.rst b/docs/solutions/reference-designs/eval-cn0584-ebz/digital-template/index.rst index ed0dcc042..8cfd86080 100644 --- a/docs/solutions/reference-designs/eval-cn0584-ebz/digital-template/index.rst +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/digital-template/index.rst @@ -422,8 +422,8 @@ Build After the HighSpeedConvertToolbox repo is set up on the machine as described in the Matlab Configuration Guide page of the wiki and the digital template models have been put in the correct folder, the Simulink model can be opened and built. -This mostly follows the step on :ref:`matlab-configuration`, but a few changes -are required. +This mostly follows the step on :ref:`eval-cn0584-ebz matlab-configuration`, +but a few changes are required. Before starting the build process, go to Configuration Parameters -> HDL Code Generation -> Global Settings and set the Reset Type to Synchronous. diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/index.rst b/docs/solutions/reference-designs/eval-cn0584-ebz/index.rst index 6494f7386..6c7cdc5f8 100644 --- a/docs/solutions/reference-designs/eval-cn0584-ebz/index.rst +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/index.rst @@ -796,7 +796,7 @@ integrates that into a larger reference design. HDL_DUT can be integrated inside HDL reference design in three different configurations which are Rx,Tx and Rx-TX. Figure 19 and Figure 20 demonstrates how HDL_DUT is placed between Tx and Rx path for these three configuration types. HDL_DUT Code Generation Workflow is -described in :ref:`Configuring Matlab guide `. +described in :ref:`Configuring Matlab guide `. Digital Template ---------------- diff --git a/docs/solutions/reference-designs/eval-cn0584-ebz/matlab-configuration/index.rst b/docs/solutions/reference-designs/eval-cn0584-ebz/matlab-configuration/index.rst index 57c2ddfe9..3ab825ece 100644 --- a/docs/solutions/reference-designs/eval-cn0584-ebz/matlab-configuration/index.rst +++ b/docs/solutions/reference-designs/eval-cn0584-ebz/matlab-configuration/index.rst @@ -1,4 +1,4 @@ -.. _matlab-configuration: +.. _eval-cn0584-ebz matlab-configuration: MATLAB Configuration =====================