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index 904b349bc4..eb6e6b2d66 100644
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diff --git a/docs/projects/adrv9026/index.rst b/docs/projects/adrv9026/index.rst
index 4679dd6c88..ff8a6ddc55 100644
--- a/docs/projects/adrv9026/index.rst
+++ b/docs/projects/adrv9026/index.rst
@@ -330,6 +330,14 @@ The Tx links (DAC Path) operate with the following parameters:
 - JESD204C Lane Rate: 16.22 Gbps
 - QPLL0
 
+.. caution::
+
+   ONLY for the ZCU102 design:
+     - Cache coherency is available and enabled.
+     - The DMA is connected to the Memory via HPC interface which is limited
+       to 128 bits.
+     - SYS_DMA_CLK = 333 MHz
+
 Configuration modes
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
diff --git a/projects/adrv9026/common/adrv9026_bd.tcl b/projects/adrv9026/common/adrv9026_bd.tcl
index 1ca9778379..8e664b18ed 100644
--- a/projects/adrv9026/common/adrv9026_bd.tcl
+++ b/projects/adrv9026/common/adrv9026_bd.tcl
@@ -355,6 +355,7 @@ ad_connect  util_adrv9026_tx_upack/s_axis $dac_offload_name/m_axis
 ad_connect  $sys_dma_clk $dac_offload_name/s_axis_aclk
 ad_connect  $sys_dma_resetn $dac_offload_name/s_axis_aresetn
 ad_connect  $sys_dma_clk axi_adrv9026_tx_dma/m_axis_aclk
+ad_connect  $sys_dma_resetn axi_adrv9026_tx_dma/m_src_axi_aresetn
 ad_connect  $dac_offload_name/s_axis axi_adrv9026_tx_dma/m_axis
 ad_connect  $dac_offload_name/init_req axi_adrv9026_tx_dma/m_axis_xfer_req
 ad_connect  tx_adrv9026_tpl_core/dac_dunf util_adrv9026_tx_upack/fifo_rd_underflow
diff --git a/projects/adrv9026/zcu102/system_bd.tcl b/projects/adrv9026/zcu102/system_bd.tcl
index 5095459df4..ce13019d2a 100644
--- a/projects/adrv9026/zcu102/system_bd.tcl
+++ b/projects/adrv9026/zcu102/system_bd.tcl
@@ -38,4 +38,33 @@ LINKS=$ad_project_params(RX_OS_NUM_LINKS)"
 
 sysid_gen_sys_init_file $sys_cstring;
 
+ad_ip_instance clk_wiz dma_clk_wiz
+ad_ip_parameter dma_clk_wiz CONFIG.PRIMITIVE MMCM
+ad_ip_parameter dma_clk_wiz CONFIG.RESET_TYPE ACTIVE_LOW
+ad_ip_parameter dma_clk_wiz CONFIG.USE_LOCKED false
+ad_ip_parameter dma_clk_wiz CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 333
+ad_ip_parameter dma_clk_wiz CONFIG.PRIM_SOURCE No_buffer
+
+ad_ip_instance proc_sys_reset sys_dma_rstgen
+ad_ip_parameter sys_dma_rstgen CONFIG.C_EXT_RST_WIDTH 1
+
+ad_connect sys_dma_clk dma_clk_wiz/clk_out1
+ad_connect sys_dma_reset sys_dma_rstgen/peripheral_reset
+ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
+
+set sys_dma_clk           [get_bd_nets sys_dma_clk]
+set sys_dma_reset         [get_bd_nets sys_dma_reset]
+set sys_dma_resetn        [get_bd_nets sys_dma_resetn]
+
+ad_connect $sys_cpu_clk dma_clk_wiz/clk_in1
+ad_connect $sys_cpu_resetn dma_clk_wiz/resetn
+ad_connect $sys_cpu_reset sys_dma_rstgen/ext_reset_in
+ad_connect $sys_dma_clk sys_dma_rstgen/slowest_sync_clk
+
 source ../common/adrv9026_bd.tcl
+
+ad_ip_parameter axi_adrv9026_tx_dma    CONFIG.FIFO_SIZE 16
+ad_ip_parameter axi_adrv9026_rx_dma    CONFIG.FIFO_SIZE 16
+if {$ORX_ENABLE} {
+  ad_ip_parameter axi_adrv9026_rx_os_dma CONFIG.FIFO_SIZE 16
+}