From 3570efbe2016b0a87a1eeb46685e51ec9113e921 Mon Sep 17 00:00:00 2001 From: caosjr Date: Wed, 5 Nov 2025 23:22:38 -0300 Subject: [PATCH 1/3] projects/ad4630_fmc: Refactor ad463x Separates the 1CH (AD4030) HDL support from the 2CH (AD4630) support. Previously, whenever 1CH was used it was necessary to throw away half of the data because the project was always expecting 2 channels for the ADC. Updated the XDC files for each supported mode considering how the amount of channels the ADC. Also updated the tcl script variables, now there is a NUM_OF_CHANNEL, updated the NUM_OF_SDI to LANES_PER_CHANNEL, and inserted INTERLEAVE_MODE variable. NO_REORDER became an internal compilation variable that is enabled according to the combination NUM_OF_CHANNEL, LANES_PER_CHANNEL and INTERLEAVE_MODE. Setting INTERLEAVE_MODE to 1 with unsupported configuration throws an error. Inserts a GPIO to drive CNV pin in parallel with the PWM. The CNV pin is an "or" function of the GPIO[36] and PWM. Updated examples in the README FILE. Signed-off-by: Carlos Souza --- projects/ad4630_fmc/common/ad463x_bd.tcl | 86 ++++++---- projects/ad4630_fmc/zed/Makefile | 11 +- projects/ad4630_fmc/zed/README.md | 159 +++++++++++++----- projects/ad4630_fmc/zed/system_bd.tcl | 5 +- ...tr_1sdi.xdc => system_constr_1sdi_1ch.xdc} | 6 +- .../ad4630_fmc/zed/system_constr_1sdi_2ch.xdc | 20 +++ .../zed/system_constr_1sdi_2ch_interleave.xdc | 17 ++ ...tr_2sdi.xdc => system_constr_2sdi_1ch.xdc} | 9 +- ...tr_4sdi.xdc => system_constr_2sdi_2ch.xdc} | 13 +- .../ad4630_fmc/zed/system_constr_4sdi_1ch.xdc | 25 +++ ...tr_8sdi.xdc => system_constr_4sdi_2ch.xdc} | 13 +- projects/ad4630_fmc/zed/system_project.tcl | 89 ++++++---- projects/ad4630_fmc/zed/system_top.v | 7 +- 13 files changed, 333 insertions(+), 127 deletions(-) rename projects/ad4630_fmc/zed/{system_constr_1sdi.xdc => system_constr_1sdi_1ch.xdc} (81%) create mode 100644 projects/ad4630_fmc/zed/system_constr_1sdi_2ch.xdc create mode 100644 projects/ad4630_fmc/zed/system_constr_1sdi_2ch_interleave.xdc rename projects/ad4630_fmc/zed/{system_constr_2sdi.xdc => system_constr_2sdi_1ch.xdc} (76%) rename projects/ad4630_fmc/zed/{system_constr_4sdi.xdc => system_constr_2sdi_2ch.xdc} (93%) create mode 100644 projects/ad4630_fmc/zed/system_constr_4sdi_1ch.xdc rename projects/ad4630_fmc/zed/{system_constr_8sdi.xdc => system_constr_4sdi_2ch.xdc} (94%) diff --git a/projects/ad4630_fmc/common/ad463x_bd.tcl b/projects/ad4630_fmc/common/ad463x_bd.tcl index 0be531bfbc3..5a3eaf4c424 100644 --- a/projects/ad4630_fmc/common/ad463x_bd.tcl +++ b/projects/ad4630_fmc/common/ad463x_bd.tcl @@ -5,13 +5,32 @@ source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl # system level parameters -set NUM_OF_SDI $ad_project_params(NUM_OF_SDI) -set CAPTURE_ZONE $ad_project_params(CAPTURE_ZONE) -set CLK_MODE $ad_project_params(CLK_MODE) -set DDR_EN $ad_project_params(DDR_EN) -set NO_REORDER $ad_project_params(NO_REORDER) +set LANES_PER_CHANNEL $ad_project_params(LANES_PER_CHANNEL) +set NUM_OF_CHANNEL $ad_project_params(NUM_OF_CHANNEL) +set CAPTURE_ZONE $ad_project_params(CAPTURE_ZONE) +set CLK_MODE $ad_project_params(CLK_MODE) +set DDR_EN $ad_project_params(DDR_EN) +set INTERLEAVE_MODE $ad_project_params(INTERLEAVE_MODE) + +if {$INTERLEAVE_MODE == 1} { + if {$LANES_PER_CHANNEL > 1 || $NUM_OF_CHANNEL != 2} { + puts "ERROR: Interleave mode is only supported with 2 channels (NUM_OF_CHANNEL == 2) and 1 lane per channel (LANES_PER_CHANNEL == 1)." + exit 2 + } + set NUM_OF_SDI 1 + # REORDER is mandatory in interleaved mode + set NO_REORDER 0 +} else { + set NUM_OF_SDI [expr {$ad_project_params(NUM_OF_CHANNEL) * $ad_project_params(LANES_PER_CHANNEL)}] + if {$NUM_OF_SDI > 2} { + # REORDER is mandatory when more than 2 lanes are used + set NO_REORDER 0 + } else { + set NO_REORDER 1 + } +} -puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ; DDR_EN: $DDR_EN ; NO_REORDER: $NO_REORDER" +puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ; DDR_EN: $DDR_EN ; INTERLEAVE_MODE: $INTERLEAVE_MODE" # block design ports and interfaces # specify the CNV generator's reference clock frequency in MHz @@ -36,6 +55,7 @@ create_bd_port -dir I ad463x_echo_sclk create_bd_port -dir I ad463x_busy create_bd_port -dir O ad463x_cnv +create_bd_port -dir I ad463x_trigger create_bd_port -dir I ad463x_ext_clk create_bd_port -dir O max17687_sync_clk @@ -77,7 +97,7 @@ ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_3 set sampling_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $adc_sampling_rate))] ## setup the pulse period for the MAX17687 and LT8608 SYNC signal -set max17687_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $max17687_sync_freq))] +set max17687_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $max17687_sync_freq))] ad_ip_instance axi_pwm_gen cnv_generator ad_ip_parameter cnv_generator CONFIG.N_PWMS 2 @@ -93,17 +113,8 @@ ad_ip_parameter sync_generator CONFIG.PULSE_0_PERIOD $max17687_cycle ad_ip_parameter sync_generator CONFIG.PULSE_0_WIDTH [expr int(ceil(double($max17687_cycle) / 2))] if {$NO_REORDER == 0} { - ad_ip_instance spi_axis_reorder data_reorder ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI - -} elseif {$NO_REORDER == 1} { - - if {$CAPTURE_ZONE == 2} { - puts "ERROR: Invalid configuration - Disabling Reorder IP is invalid for Capture Zone 2." - exit 2 - } - } # dma to receive data stream @@ -116,19 +127,23 @@ ad_ip_parameter axi_ad463x_dma CONFIG.AXI_SLICE_DEST 1 ad_ip_parameter axi_ad463x_dma CONFIG.AXI_SLICE_SRC 1 if {$NO_REORDER == 0} { ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_SRC 64 -} elseif {$NO_REORDER == 1} { - if {$NUM_OF_SDI == 1} { - ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_SRC 32 - } elseif {$NUM_OF_SDI == 2} { - ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_SRC 64 - } +} else { + #REORDER BYPASSED + ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(32 * $NUM_OF_SDI, 64)] } - + ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_DEST 64 +# or logic for CNV generation +ad_ip_instance ilvector_logic or_logic_cnv +ad_ip_parameter or_logic_cnv CONFIG.C_SIZE 1 +ad_ip_parameter or_logic_cnv CONFIG.C_OPERATION or + +ad_connect cnv_generator/pwm_1 or_logic_cnv/Op1 +ad_connect ad463x_trigger or_logic_cnv/Op2 + # Trigger for SPI offload if {$CAPTURE_ZONE == 1} { - ## SPI mode is using the echo SCLK, on echo SPI and Master mode the BUSY # is used for SDI latching switch $CLK_MODE { @@ -137,7 +152,7 @@ if {$CAPTURE_ZONE == 1} { } 1 - 2 { - puts "ERROR: Invalid configuration option. CAPTURE_ZONE 1 can be used only in SPI mode (CLK_MODE == 1)." + puts "ERROR: Invalid configuration option. CAPTURE_ZONE 1 can be used only in SPI mode (CLK_MODE == 0)." exit 2 } default { @@ -159,6 +174,7 @@ if {$CAPTURE_ZONE == 1} { ad_connect ad463x_busy busy_sync/in_bits ad_connect busy_sync/out_bits busy_capture/signal_in ad_connect $hier_spi_engine/trigger busy_capture/signal_out + ## SDI is latched by the SPIE execution module if {$NO_REORDER == 0} { ad_connect $hier_spi_engine/m_axis_sample data_reorder/s_axis @@ -167,7 +183,6 @@ if {$CAPTURE_ZONE == 1} { } } elseif {$CAPTURE_ZONE == 2} { - # Zone 2 - trigger to next consecutive CNV ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_offload CONFIG.ASYNC_TRIG 1 ad_connect cnv_generator/pwm_0 $hier_spi_engine/trigger @@ -179,7 +194,11 @@ if {$CAPTURE_ZONE == 1} { switch $CLK_MODE { 0 { ## SDI is latched by the SPIE execution module - ad_connect $hier_spi_engine/m_axis_sample data_reorder/s_axis + if {$NO_REORDER == 0} { + ad_connect $hier_spi_engine/m_axis_sample data_reorder/s_axis + } else { + ad_connect $hier_spi_engine/m_axis_sample axi_ad463x_dma/s_axis + } } 1 - 2 { @@ -193,8 +212,12 @@ if {$CAPTURE_ZONE == 1} { ad_connect ad463x_busy data_capture/echo_sclk ad_connect ad463x_spi_sdi data_capture/data_in - ad_connect data_capture/m_axis data_reorder/s_axis - + ## SDI is latched by the SPIE execution module + if {$NO_REORDER == 0} { + ad_connect data_capture/m_axis data_reorder/s_axis + } else { + ad_connect data_capture/m_axis axi_ad463x_dma/s_axis + } } default { puts "ERROR: Invalid value for CLK_MODE (valid values are 0 or 1 or 2)." @@ -203,12 +226,11 @@ if {$CAPTURE_ZONE == 1} { } } else { - puts "ERROR: Invalid capture zone, please choose 1 or 2." exit 2 - } -ad_connect ad463x_cnv cnv_generator/pwm_1 + +ad_connect ad463x_cnv or_logic_cnv/Res ad_connect max17687_sync_clk sync_generator/pwm_0 # clocks diff --git a/projects/ad4630_fmc/zed/Makefile b/projects/ad4630_fmc/zed/Makefile index 8f0b0a9fdc9..03e1d7dd054 100644 --- a/projects/ad4630_fmc/zed/Makefile +++ b/projects/ad4630_fmc/zed/Makefile @@ -6,10 +6,13 @@ PROJECT_NAME := ad4630_fmc_zed -M_DEPS += system_constr_8sdi.xdc -M_DEPS += system_constr_4sdi.xdc -M_DEPS += system_constr_2sdi.xdc -M_DEPS += system_constr_1sdi.xdc +M_DEPS += system_constr_4sdi_2ch.xdc +M_DEPS += system_constr_4sdi_1ch.xdc +M_DEPS += system_constr_2sdi_2ch.xdc +M_DEPS += system_constr_2sdi_1ch.xdc +M_DEPS += system_constr_1sdi_2ch_interleave.xdc +M_DEPS += system_constr_1sdi_2ch.xdc +M_DEPS += system_constr_1sdi_1ch.xdc M_DEPS += ../common/ad463x_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc diff --git a/projects/ad4630_fmc/zed/README.md b/projects/ad4630_fmc/zed/README.md index 5ab446ca646..51f97fa75ee 100644 --- a/projects/ad4630_fmc/zed/README.md +++ b/projects/ad4630_fmc/zed/README.md @@ -24,43 +24,44 @@ need to be changed, as well as the Linux project configurations: The overwritable parameters from the environment are: - CLK_MODE: clocking mode of the device's digital interface - - 0 - SPI (default) - - 1 - Echo-clock or Master clock -- NUM_OF_SDI: the number of MISO lines of the SPI interface - - 1 - Interleaved - - 2 - 1LPC - - 4 - 2LPC (default) - - 8 - 4LPC + - 0 - SPI (default); + - 1 - Echo-clock or Master clock; +- NUM_OF_CHANNEL: the number of ADC channels + - 1 - AD403x devices; + - 2 - AD463x/adaq42xx devices (default). +- LANES_PER_CHANNEL: the number of MISO lanes of the SPI interface per channel + - 1 - 1 lane per channel: Interleaved mode or single lane per channel; + - 2 - 2 lanes per channel; + - 4 - 4 lanes per channel (default). - CAPTURE_ZONE: the capture zone of the next sample - - 1 - negative edge of BUSY - - 2 - next positive edge of CNV (default) -- DDR_EN: in echo and master clock mode, the SDI lines can have Single or Double data rates - - 0 - MISO runs on SDR (default) - - 1 - MISO runs on DDR -- NO_REORDER: removes the spi_axis_reorder from system for CAPTURE_ZONE = 1 and - NUM_OF_SDI = 1 (AD4030) or NUM_OF_SDI = 2 (AD4630) and directly connects the SPI - Engine to DMA - - 0 - spi_axis_reorder present (default) - - 1 - spi_axis_reorder removed + - 1 - negative edge of BUSY; + - 2 - next positive edge of CNV (default); +- DDR_EN: in echo or master clock mode, the MISO lanes can have Single or Double data rates + - 0 - MISO runs on SDR (default); + - 1 - MISO runs on DDR; +- INTERLEAVE_MODE: parameter used for NUM_OF_CHANNEL = 2 and LANES_PER_CHANNEL = 1 (ad463x). + Enabling INTERLEAVE_MODE for any other configuration is invalid. + - 0 - interleave mode disabled, each channel has their own MISO lanes. (default); + - 1 - interleave mode enabled, the ad463x ADC share the same MISO lanes. ### Example configurations -#### Clock mode SPI, MISO lines 4, Capture zone 2, SDR (default) +#### Clock mode SPI, 2 channels, MISO lanes 4 (2 per channel), Capture zone 2, SDR (default) This specific command is equivalent to running `make` only: ``` -make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=0 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=0 ``` Corresponding device trees: - [zynq-zed-adv7511-ad4630-24.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-24.dts) - [zynq-zed-adv7511-ad4630-16.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-16.dts) -#### Clock mode SPI, MISO lines 2, Capture zone 2, SDR +#### Clock mode SPI, 1 channel, MISO lane 1, Capture zone 2, SDR ``` -make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=0 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=0 ``` Corresponding device trees: @@ -71,62 +72,138 @@ Corresponding device trees: - [zynq-zed-adv7511-adaq4220.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4220.dts) - [zynq-zed-adv7511-adaq4224-24.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24.dts) -#### Clock mode SPI, MISO lines 4, Capture zone 2, SDR +#### 1-Channel options +#### Clock mode SPI, 1 channel, MISO lane 1, Capture zone 2, SDR ``` -make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=0 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=0 ``` -#### Clock mode SPI, MISO lines 8, Capture zone 2, SDR +#### Clock mode SPI, 1 channel, MISO lanes 2, Capture zone 2, SDR ``` -make CLK_MODE=0 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=0 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=0 ``` -#### Clock mode ECHO, MISO lines 2, Capture zone 2, SDR +#### Clock mode SPI, 1 channel, MISO lanes 4, Capture zone 2, SDR ``` -make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=0 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=0 ``` -#### Clock mode ECHO, MISO lines 4, Capture zone 2, SDR +#### Clock mode Echo, 1 channel, MISO lane 1, Capture zone 2, SDR ``` -make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=1 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=0 ``` -#### Clock mode ECHO, MISO lines 8, Capture zone 2, SDR +#### Clock mode Echo, 1 channel, MISO lanes 2, Capture zone 2, SDR ``` -make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=1 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=0 ``` -#### Clock mode ECHO, MISO lines 2, Capture zone 2, DDR +#### Clock mode Echo, 1 channel, MISO lanes 4, Capture zone 2, SDR ``` -make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=1 NO_REORDER=0 +make CLK_MODE=1 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=0 ``` -#### Clock mode ECHO, MISO lines 4, Capture zone 2, DDR +#### Clock mode Echo, 1 channel, MISO lane 1, Capture zone 2, DDR ``` -make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=1 NO_REORDER=0 +make CLK_MODE=1 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=1 ``` -#### Clock mode ECHO, MISO lines 8, Capture zone 2, DDR +#### Clock mode Echo, 1 channel, MISO lanes 2, Capture zone 2, DDR ``` -make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=1 NO_REORDER=0 +make CLK_MODE=1 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=1 ``` -#### Clock mode SPI, MISO lines 1, Capture zone 1, SDR (AD4030) +#### Clock mode Echo, 1 channel, MISO lanes 4, Capture zone 2, DDR ``` -make CLK_MODE=0 NUM_OF_SDI=1 CAPTURE_ZONE=1 DDR_EN=0 NO_REORDER=1 +make CLK_MODE=1 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=1 ``` -#### Clock mode SPI, MISO lines 2, Capture zone 1, SDR (AD4630) +#### 2-Channel options +#### Clock mode SPI, 2 channels, MISO lane 1, interleaved mode (1 MISO shared by both channels), Capture zone 2, SDR ``` -make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=1 DDR_EN=0 NO_REORDER=1 +make CLK_MODE=0 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=1 INTERLEAVE_MODE=1 CAPTURE_ZONE=2 DDR_EN=0 ``` + +#### Clock mode SPI, 2 channels, MISO lanes 2 (1 per channel), Capture zone 2, SDR + +``` +make CLK_MODE=0 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=0 +``` + +#### Clock mode SPI, 2 channels, MISO lanes 4 (2 per channel), Capture zone 2, SDR + +``` +make CLK_MODE=0 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=0 +``` + +#### Clock mode SPI, 2 channels, MISO lanes 8 (4 per channel), Capture zone 2, SDR + +``` +make CLK_MODE=0 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=0 +``` + +#### Clock mode Echo, 2 channels, MISO lane 1, interleaved mode (1 MISO shared by both channels), Capture zone 2, SDR + +``` +make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=1 INTERLEAVE_MODE=1 CAPTURE_ZONE=2 DDR_EN=0 +``` + +#### Clock mode Echo, 2 channels, MISO lanes 2 (1 per channel), Capture zone 2, SDR + +``` +make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=0 +``` + +#### Clock mode Echo, 2 channels, MISO lanes 4 (2 per channel), Capture zone 2, SDR + +``` +make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=0 +``` + +#### Clock mode Echo, 2 channels, MISO lanes 8 (4 per channel), Capture zone 2, SDR + +``` +make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=0 +``` + +#### Clock mode Echo, 2 channels, MISO lane 1, interleaved mode (1 MISO shared by both channels), Capture zone 2, DDR + +``` +make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=1 INTERLEAVE_MODE=1 CAPTURE_ZONE=2 DDR_EN=1 +``` + +#### Clock mode Echo, 2 channels, MISO lanes 2 (1 per channel), Capture zone 2, DDR + +``` +make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=1 +``` + +#### Clock mode Echo, 2 channels, MISO lanes 4 (2 per channel), Capture zone 2, DDR + +``` +make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=1 +``` + +#### Clock mode Echo, 2 channels, MISO lanes 8 (4 per channel), Capture zone 2, DDR + +``` +make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=1 +``` + +#### Unsupported options + +Any combination of NUM_OF_CHANNEL=1 and INTERLEAVE_MODE=1. It makes no sense to interleave the data of a single channel. + +Any combination of LANES_PER_CHANNEL > 1 and INTERLEAVE_MODE=1. It is necessary a single MISO lane for interleaving. + +Any combination of CLK_MODE=0 and DDR_EN=1. The DDR mode is available only valid for echo clock and host clock modes - see MODES REGISTER specification. \ No newline at end of file diff --git a/projects/ad4630_fmc/zed/system_bd.tcl b/projects/ad4630_fmc/zed/system_bd.tcl index a2bfc589676..5b01af53fbb 100644 --- a/projects/ad4630_fmc/zed/system_bd.tcl +++ b/projects/ad4630_fmc/zed/system_bd.tcl @@ -20,9 +20,10 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 set sys_cstring "CLK_MODE=$ad_project_params(CLK_MODE)\ -NUM_OF_SDI=$ad_project_params(NUM_OF_SDI)\ +LANES_PER_CHANNEL=$ad_project_params(LANES_PER_CHANNEL)\ +NUM_OF_CHANNEL=$ad_project_params(NUM_OF_CHANNEL)\ CAPTURE_ZONE=$ad_project_params(CAPTURE_ZONE)\ DDR_EN=$ad_project_params(DDR_EN)\ -NO_REORDER=$ad_project_params(NO_REORDER)" +INTERLEAVE_MODE=$ad_project_params(INTERLEAVE_MODE)" sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ad4630_fmc/zed/system_constr_1sdi.xdc b/projects/ad4630_fmc/zed/system_constr_1sdi_1ch.xdc similarity index 81% rename from projects/ad4630_fmc/zed/system_constr_1sdi.xdc rename to projects/ad4630_fmc/zed/system_constr_1sdi_1ch.xdc index ff30f115886..c72e814af6a 100644 --- a/projects/ad4630_fmc/zed/system_constr_1sdi.xdc +++ b/projects/ad4630_fmc/zed/system_constr_1sdi_1ch.xdc @@ -3,12 +3,14 @@ ### SPDX short identifier: ADIBSD ############################################################################### -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi] ; ## H07 FMC_LPC_LA02_P +# Constraints for 1 SDI, 1 Channel configuration # input delays for MISO lines (SDO for the device) # data is latched on negative edge set tsetup 5.6 set thold 1.4 +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi}] ; ## H07 FMC_LA02_P + set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi] \ No newline at end of file diff --git a/projects/ad4630_fmc/zed/system_constr_1sdi_2ch.xdc b/projects/ad4630_fmc/zed/system_constr_1sdi_2ch.xdc new file mode 100644 index 00000000000..14e0d0d2cb6 --- /dev/null +++ b/projects/ad4630_fmc/zed/system_constr_1sdi_2ch.xdc @@ -0,0 +1,20 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# Constraints for 1 SDI per channel, 2 Channels configuration with reorder (NO_REORDER=0) +# This results in 2 SDI lines total +# input delays for MISO lines (SDO for the device) +# data is latched on negative edge + +set tsetup 5.6 +set thold 1.4 + +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H10 FMC_LA04_P + +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[1]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[1]}] \ No newline at end of file diff --git a/projects/ad4630_fmc/zed/system_constr_1sdi_2ch_interleave.xdc b/projects/ad4630_fmc/zed/system_constr_1sdi_2ch_interleave.xdc new file mode 100644 index 00000000000..e4eae28b315 --- /dev/null +++ b/projects/ad4630_fmc/zed/system_constr_1sdi_2ch_interleave.xdc @@ -0,0 +1,17 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# Constraints for 1 SDI, 2 Channels configuration without reorder (NO_REORDER=1) +# This results in only 1 SDI line total +# input delays for MISO lines (SDO for the device) +# data is latched on negative edge + +set tsetup 5.6 +set thold 1.4 + +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P + +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}] \ No newline at end of file diff --git a/projects/ad4630_fmc/zed/system_constr_2sdi.xdc b/projects/ad4630_fmc/zed/system_constr_2sdi_1ch.xdc similarity index 76% rename from projects/ad4630_fmc/zed/system_constr_2sdi.xdc rename to projects/ad4630_fmc/zed/system_constr_2sdi_1ch.xdc index 179c562f7f4..d5ce52057b9 100644 --- a/projects/ad4630_fmc/zed/system_constr_2sdi.xdc +++ b/projects/ad4630_fmc/zed/system_constr_2sdi_1ch.xdc @@ -3,16 +3,17 @@ ### SPDX short identifier: ADIBSD ############################################################################### -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H10 FMC_LPC_LA04_P - +# Constraints for 2 SDI, 1 Channel configuration # input delays for MISO lines (SDO for the device) # data is latched on negative edge set tsetup 5.6 set thold 1.4 +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LA02_N + set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]] \ No newline at end of file diff --git a/projects/ad4630_fmc/zed/system_constr_4sdi.xdc b/projects/ad4630_fmc/zed/system_constr_2sdi_2ch.xdc similarity index 93% rename from projects/ad4630_fmc/zed/system_constr_4sdi.xdc rename to projects/ad4630_fmc/zed/system_constr_2sdi_2ch.xdc index 0aca6b40eab..47bea30eff9 100644 --- a/projects/ad4630_fmc/zed/system_constr_4sdi.xdc +++ b/projects/ad4630_fmc/zed/system_constr_2sdi_2ch.xdc @@ -3,17 +3,18 @@ ### SPDX short identifier: ADIBSD ############################################################################### -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LA02_N -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] ; ## H10 FMC_LA04_P -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[3]}] ; ## H11 FMC_LA04_N - +# Constraints for 2 SDI per channel, 2 Channels configuration (4 SDI lines total) # input delays for MISO lines (SDO for the device) # data is latched on negative edge set tsetup 5.6 set thold 1.4 +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LA02_N +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] ; ## H10 FMC_LA04_P +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[3]}] ; ## H11 FMC_LA04_N + set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[1]}] @@ -21,4 +22,4 @@ set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_po set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[2]}] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[2]}] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[3]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[3]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[3]}] \ No newline at end of file diff --git a/projects/ad4630_fmc/zed/system_constr_4sdi_1ch.xdc b/projects/ad4630_fmc/zed/system_constr_4sdi_1ch.xdc new file mode 100644 index 00000000000..3f12c9481c9 --- /dev/null +++ b/projects/ad4630_fmc/zed/system_constr_4sdi_1ch.xdc @@ -0,0 +1,25 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# Constraints for 4 SDI, 1 Channel configuration +# input delays for MISO lines (SDO for the device) +# data is latched on negative edge + +set tsetup 5.6 +set thold 1.6 + +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[3]] ; ## G10 FMC_LPC_LA03_N + +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[2]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[2]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[3]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[3]] \ No newline at end of file diff --git a/projects/ad4630_fmc/zed/system_constr_8sdi.xdc b/projects/ad4630_fmc/zed/system_constr_4sdi_2ch.xdc similarity index 94% rename from projects/ad4630_fmc/zed/system_constr_8sdi.xdc rename to projects/ad4630_fmc/zed/system_constr_4sdi_2ch.xdc index d8819d0e1eb..db34ea59f4d 100644 --- a/projects/ad4630_fmc/zed/system_constr_8sdi.xdc +++ b/projects/ad4630_fmc/zed/system_constr_4sdi_2ch.xdc @@ -3,6 +3,13 @@ ### SPDX short identifier: ADIBSD ############################################################################### +# Constraints for 4 SDI per channel, 2 Channels configuration (8 SDI lines total) +# input delays for MISO lines (SDO for the device) +# data is latched on negative edge + +set tsetup 5.6 +set thold 1.6 + set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P @@ -12,10 +19,6 @@ set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_s set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[6]] ; ## D11 FMC_LPC_LA05_P set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[7]] ; ## D12 FMC_LPC_LA05_N -set tsetup 5.6 -set thold 1.6 - -# input delays for MISO lines (SDO for the device) set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]] @@ -31,4 +34,4 @@ set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_p set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[6]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[6]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[7]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[7]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[7]] \ No newline at end of file diff --git a/projects/ad4630_fmc/zed/system_project.tcl b/projects/ad4630_fmc/zed/system_project.tcl index 45d56750e6c..b4483e297e4 100644 --- a/projects/ad4630_fmc/zed/system_project.tcl +++ b/projects/ad4630_fmc/zed/system_project.tcl @@ -13,7 +13,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # How to use over-writable parameters from the environment: # # e.g. -# make NUM_OF_SDI=4 CAPTURE_ZONE=2 +# make LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 # # # Parameter description: @@ -23,12 +23,16 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # 0 - SPI Mode # 1 - Echo-clock or Master clock mode # -# NUM_OF_SDI : the number of MOSI lines of the SPI interface +# NUM_OF_CHANNEL : the number of ADC channels # -# 1 - Interleaved mode -# 2 - 1 lane per channel -# 4 - 2 lanes per channel -# 8 - 4 lanes per channel +# 1 - AD403x devices +# 2 - AD463x/adaq42xx devices +# +# LANES_PER_CHANNEL : the number of MOSI lines of the SPI interface +# +# 1 - 1 lane per channel: Interleaved mode or single lane per channel +# 2 - 2 lanes per channel +# 4 - 4 lanes per channel # # CAPTURE_ZONE : the capture zone of the next sample # There are two capture zones for AD4624-30: @@ -43,24 +47,24 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # 0 - MISO runs on SDR # 1 - MISO runs on DDR # -# NO_REORDER : Parameter used for CAPTURE_ZONE = 1 and NUM_OF_SDI = 1 (ad4030) -# or NUM_OF_SDI = 2 (ad4630) to connect the SPI Engine directly to DMA bypassing -# the spi_axis_reorder IP +# INTERLEAVE_MODE: parameter used for NUM_OF_CHANNEL = 2 and LANES_PER_CHANNEL = 1 (ad463x). +# Enabling INTERLEAVE_MODE for any other configuration is invalid. # -# 0 - spi_axis_reorder present in the system -# 1 - spi_axis_reorder removed from the system +# 0 - interleave mode disabled, each channel has its own SDI line +# 1 - interleave mode enabled, the ad463x ADC share the same SDI line # # Example: # -# make NUM_OF_SDI=2 CAPTURE_ZONE=2 +# make CLK_MODE=0 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=0 INTERLEAVE_MODE=0 # adi_project ad4630_fmc_zed 0 [list \ - CLK_MODE [get_env_param CLK_MODE 0] \ - NUM_OF_SDI [get_env_param NUM_OF_SDI 4] \ - CAPTURE_ZONE [get_env_param CAPTURE_ZONE 2] \ - DDR_EN [get_env_param DDR_EN 0] \ - NO_REORDER [get_env_param NO_REORDER 0] ] + CLK_MODE [get_env_param CLK_MODE 0] \ + LANES_PER_CHANNEL [get_env_param LANES_PER_CHANNEL 2] \ + NUM_OF_CHANNEL [get_env_param NUM_OF_CHANNEL 2] \ + CAPTURE_ZONE [get_env_param CAPTURE_ZONE 2] \ + DDR_EN [get_env_param DDR_EN 0] \ + INTERLEAVE_MODE [get_env_param INTERLEAVE_MODE 0] ] adi_project_files ad4630_fmc_zed [list \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ @@ -69,26 +73,53 @@ adi_project_files ad4630_fmc_zed [list \ "system_constr.xdc" \ "system_top.v" ] -switch [get_env_param NUM_OF_SDI 4] { +switch [get_env_param LANES_PER_CHANNEL 2] { 1 { - adi_project_files ad4630_fmc_zed [list \ - "system_constr_1sdi.xdc" ] + # For 1 SDI, check NUM_OF_CHANNEL + if {[get_env_param NUM_OF_CHANNEL 2] == 1} { + # 1 channel, 1 SDI + adi_project_files ad4630_fmc_zed [list \ + "system_constr_1sdi_1ch.xdc" ] + } else { + # 2 channels, check INTERLEAVE_MODE + if {[get_env_param INTERLEAVE_MODE 0] == 0} { + # INTERLEAVE_MODE=0: 2 SDI lines (1 per channel) + adi_project_files ad4630_fmc_zed [list \ + "system_constr_1sdi_2ch.xdc" ] + } else { + # INTERLEAVE_MODE=1: valid for AD463x only, both channels share the same SDI line + adi_project_files ad4630_fmc_zed [list \ + "system_constr_1sdi_2ch_interleave.xdc" ] + } + } } 2 { - adi_project_files ad4630_fmc_zed [list \ - "system_constr_2sdi.xdc" ] + # For 2 SDI, check NUM_OF_CHANNEL + if {[get_env_param NUM_OF_CHANNEL 2] == 1} { + # 1 channel, 2 SDI + adi_project_files ad4630_fmc_zed [list \ + "system_constr_2sdi_1ch.xdc" ] + } else { + # 2 channels, 4 SDI total (2 per channel) + adi_project_files ad4630_fmc_zed [list \ + "system_constr_2sdi_2ch.xdc" ] + } } 4 { - adi_project_files ad4630_fmc_zed [list \ - "system_constr_4sdi.xdc" ] - } - 8 { - adi_project_files ad4630_fmc_zed [list \ - "system_constr_8sdi.xdc" ] + # For 4 SDI, check NUM_OF_CHANNEL + if {[get_env_param NUM_OF_CHANNEL 2] == 1} { + # 1 channel, 4 SDI + adi_project_files ad4630_fmc_zed [list \ + "system_constr_4sdi_1ch.xdc" ] + } else { + # 2 channels, 8 SDI total (4 per channel) + adi_project_files ad4630_fmc_zed [list \ + "system_constr_4sdi_2ch.xdc" ] + } } default { adi_project_files ad4630_fmc_zed [list \ - "system_constr_2sdi.xdc" ] + "system_constr_4sdi_2ch.xdc" ] } } diff --git a/projects/ad4630_fmc/zed/system_top.v b/projects/ad4630_fmc/zed/system_top.v index cf55b9eea60..5a191e414ee 100644 --- a/projects/ad4630_fmc/zed/system_top.v +++ b/projects/ad4630_fmc/zed/system_top.v @@ -117,11 +117,13 @@ module system_top #( wire [ 1:0] iic_mux_sda_o_s; wire iic_mux_sda_t_s; wire ad463x_echo_sclk_s; + wire ad463x_trigger; // instantiations - assign gpio_i[63:36] = 27'b0; - assign max17687_en = 1'b1; + assign gpio_i[63:37] = 26'b0; + assign max17687_en = 1'b1; + assign ad463x_trigger = gpio_o[36]; ad_data_clk #( .SINGLE_ENDED (1) @@ -243,6 +245,7 @@ module system_top #( .ad463x_echo_sclk (ad463x_echo_sclk_s), .ad463x_busy (ad463x_busy), .ad463x_cnv (ad463x_cnv), + .ad463x_trigger (ad463x_trigger), .ad463x_ext_clk (ext_clk_s), .max17687_sync_clk (max17687_sync_clk), .otg_vbusoc (otg_vbusoc), From 7641442bbd4740c10e32bc87b1022ea8a2f7c6db Mon Sep 17 00:00:00 2001 From: caosjr Date: Sun, 23 Nov 2025 11:36:10 -0300 Subject: [PATCH 2/3] projects/ad4630_fmc: update AD4630_FMC documentation Updated the documentation with the new variables and features of the AD4630_FMC project. It is describing how to compile with the NUM_OF_CHANNEL, LANES_PER_CHANNEL, and INTERLEAVE_MODE. It also describes the EMIO inserted for controlling the CNV output. Signed-off-by: Carlos Souza --- .../ad4630_fmc/ad463x_hdl_cm0_cz1_1.svg | 2423 +++++++-------- .../ad463x_hdl_cm0_cz1_no_reorder.svg | 2404 ++++++++------- .../ad4630_fmc/ad463x_hdl_cm0_cz2_1.svg | 192 +- .../ad4630_fmc/ad463x_hdl_cm1_cz2_1.svg | 255 +- .../ad4630_fmc/adaq42xx_hdl_cm0_cz2_1.svg | 2593 +++++++++-------- .../ad4630_fmc/adaq42xx_hdl_cm1_cz2_1.svg | 2568 ++++++++-------- docs/projects/ad4630_fmc/index.rst | 113 +- 7 files changed, 5418 insertions(+), 5130 deletions(-) diff --git a/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_1.svg b/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_1.svg index cbaf0e184d9..ad22c2ca259 100644 --- a/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_1.svg +++ b/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_1.svg @@ -1,13 +1,13 @@ + xmlns:dc="http://purl.org/dc/elements/1.1/"> - - - - - - + + + inkscape:isstock="true" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243083" + preserveAspectRatio="xMidYMid"> + inkscape:collect="always" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243083" + preserveAspectRatio="xMidYMid"> + inkscape:stockid="TriangleInM"> + inkscape:stockid="TriangleInM" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243078" + preserveAspectRatio="xMidYMid"> + inkscape:stockid="TriangleOutM" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243078" + preserveAspectRatio="xMidYMid"> + inkscape:swatch="solid"> + inkscape:isstock="true" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243078" + preserveAspectRatio="xMidYMid"> + inkscape:isstock="true" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243083" + preserveAspectRatio="xMidYMid"> + inkscape:isstock="true" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243083" + preserveAspectRatio="xMidYMid"> @@ -1142,12 +1151,12 @@ orient="auto" refY="0" refX="0" - id="marker6925-8-3" + id="marker1216-0-3-1-2-3" style="overflow:visible" inkscape:isstock="true"> @@ -1157,12 +1166,12 @@ orient="auto" refY="0" refX="0" - id="marker6925-9-4" + id="marker1216-0-3-1-2-9-9" style="overflow:visible" inkscape:isstock="true"> @@ -1172,12 +1181,12 @@ orient="auto" refY="0" refX="0" - id="marker7155-2" + id="marker1216-0-3-1-2-9-6" style="overflow:visible" inkscape:isstock="true"> @@ -1187,12 +1196,12 @@ orient="auto" refY="0" refX="0" - id="marker1216-0-3-9-6" + id="marker1216-0-3-1-2-9-4" style="overflow:visible" inkscape:isstock="true"> @@ -1202,12 +1211,12 @@ orient="auto" refY="0" refX="0" - id="marker1216-0-3-9-3" + id="marker1216-0-3-1-2-9-4-2" style="overflow:visible" inkscape:isstock="true"> @@ -1217,12 +1226,12 @@ orient="auto" refY="0" refX="0" - id="marker1216-0-3-9-3-6" + id="marker1216-0-3-1-2-9-4-2-7" style="overflow:visible" inkscape:isstock="true"> @@ -1232,12 +1241,12 @@ orient="auto" refY="0" refX="0" - id="marker1216-0-3-9-3-6-1" + id="marker6925-9-4" style="overflow:visible" inkscape:isstock="true"> @@ -1247,31 +1256,31 @@ inkscape:document-rotation="0" inkscape:snap-global="true" inkscape:snap-page="true" - showguides="false" + showguides="true" inkscape:window-maximized="1" inkscape:window-y="-8" - inkscape:window-x="4763" - inkscape:window-height="1272" - inkscape:window-width="2400" + inkscape:window-x="1912" + inkscape:window-height="729" + inkscape:window-width="1280" units="px" showgrid="true" inkscape:current-layer="layer1" inkscape:document-units="px" - inkscape:cy="358.57143" - inkscape:cx="481.07143" - inkscape:zoom="1.4" + inkscape:cy="490.42906" + inkscape:cx="534.3707" + inkscape:zoom="0.98994949" inkscape:pageshadow="2" inkscape:pageopacity="0.0" borderopacity="1.0" bordercolor="#666666" pagecolor="#ffffff" id="base" - inkscape:showpageshadow="2" inkscape:pagecheckerboard="0" + inkscape:showpageshadow="2" inkscape:deskcolor="#d1d1d1"> - - - - BUSY CDC - - - - - - - - - - - - - - - - - - Ethernet - UART - DDRx - SPI - I + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C - Interrupts - - Timer - - - MEMORY INTERCONNECT - Zedboard - - - FMC CONNECTOR - - - AD463X_DMA - 80MHz - - - - ARM (Zynq) - Zynq SoC - - - SPI ENGINE FRAMEWORK - - - - - - - - - - MISO/SDI[7:0] - CS - MOSI/SDO - SCLK - - - - - ECHO SCLK - - - - - AXI PWMGEN - - CNV - - - - AXI CLKGEN - - - spi_clk = 160MHz - sys_clk = 100MHz - - - - - - - - REF_CLK - 100MHz - - - INTERCONNECT - - - - - BUSY - trigger - + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.8633px;font-family:Arial;-inkscape-font-specification:'Arial Bold';baseline-shift:super;stroke-width:1.1434px">2C + Interrupts + + Timer + + MEMORY INTERCONNECT + Zedboard + + + FMC CONNECTOR + + + AD463X_DMA + 80MHz + + + ARM (Zynq) + Zynq SoC + + + + + MISO/SDI[7:0] + SPI ENGINE FRAMEWORK + CS + MOSI/SDO + SCLK + + + + + + + + AXI PWMGEN + GPIO + CNV + BUSY + TRIGGER + + AXI CLKGEN + spi_clk = 160MHz + sys_clk = 100MHz + + + + + + + + REF_CLK + 100MHz + + INTERCONNECT + + ECHO SCLK + + + + + + + + + + + + + + + + + + + + + - - - - - + id="g8811" + transform="matrix(1.2472877,0,0,1.2472877,-157.97249,-19.934072)" + style="fill:#ffffff;fill-opacity:1;stroke:#ffffff;stroke-opacity:1;shape-rendering:crispEdges"> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#ffffff;stroke-width:0.479248;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + d="m 371.16019,393.86166 h 6.77743 v 5.24892 h -6.77743 z" + id="rect8801" /> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#ffffff;stroke-width:0.479248;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + d="m 383.3136,393.86166 h 6.77743 v 5.24892 h -6.77743 z" + id="rect8809" /> + + + + + + + + + + + + + + + + + + + + + + + + 32b - - - OFFLOAD - - - + id="g6072" + transform="translate(0,-60)"> REGMAP + style="font-size:16px;stroke-width:2.5">OFFLOAD + trigger + + REGMAP + + EXECUTION + id="g6913" + transform="matrix(0.80188679,0,0,1,-95.471692,-60.654586)" + style="shape-rendering:crispEdges"> + id="rect35512-6-7" + style="display:inline;fill:#e5e5e5;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.34737;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;paint-order:normal;shape-rendering:crispEdges;enable-background:new" /> DATA EXECUTION + style="font-size:17.8675px;text-align:center;text-anchor:middle;stroke-width:2.5" + id="tspan6907">REORDER + + - - - DATA REORDER - + id="g4625-7-7" + style="shape-rendering:crispEdges" + transform="translate(80.562487,34.316332)"> + + BUSY CDC + + OR + DATA REORDER is present depending on the parameters combination. + + + + + diff --git a/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_no_reorder.svg b/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_no_reorder.svg index 7492e8cb49e..431aace6279 100644 --- a/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_no_reorder.svg +++ b/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_no_reorder.svg @@ -1,13 +1,13 @@ - - - - - - + x="690.74585" + y="460.74579" + width="200" + height="130" + id="rect39035" /> + + inkscape:isstock="true" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243083" + preserveAspectRatio="xMidYMid"> + inkscape:collect="always" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243083" + preserveAspectRatio="xMidYMid"> + inkscape:stockid="TriangleInM"> + inkscape:stockid="TriangleInM" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243078" + preserveAspectRatio="xMidYMid"> + inkscape:stockid="TriangleOutM" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243078" + preserveAspectRatio="xMidYMid"> + inkscape:isstock="true" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243078" + preserveAspectRatio="xMidYMid"> + inkscape:isstock="true" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243083" + preserveAspectRatio="xMidYMid"> + inkscape:isstock="true" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243083" + preserveAspectRatio="xMidYMid"> @@ -1147,12 +1151,12 @@ orient="auto" refY="0" refX="0" - id="marker6925-8-3" + id="marker1216-0-3-1-2-3" style="overflow:visible" inkscape:isstock="true"> @@ -1162,27 +1166,12 @@ orient="auto" refY="0" refX="0" - id="marker6925-9-4" - style="overflow:visible" - inkscape:isstock="true"> - - - @@ -1192,12 +1181,12 @@ orient="auto" refY="0" refX="0" - id="marker1216-0-3-9-6" + id="marker1216-0-3-1-2-9-6" style="overflow:visible" inkscape:isstock="true"> @@ -1207,12 +1196,12 @@ orient="auto" refY="0" refX="0" - id="marker1216-0-3-9-3" + id="marker1216-0-3-1-2-9-4" style="overflow:visible" inkscape:isstock="true"> @@ -1222,12 +1211,12 @@ orient="auto" refY="0" refX="0" - id="marker1216-0-3-9-3-6" + id="marker1216-0-3-1-2-9-4-2" style="overflow:visible" inkscape:isstock="true"> @@ -1237,12 +1226,12 @@ orient="auto" refY="0" refX="0" - id="marker1216-0-3-9-3-6-1" + id="marker1216-0-3-1-2-9-4-2-7" style="overflow:visible" inkscape:isstock="true"> @@ -1252,12 +1241,12 @@ orient="auto" refY="0" refX="0" - id="marker1216-0-3-1-2-9-5-6" + id="marker6925-9-4" style="overflow:visible" inkscape:isstock="true"> @@ -1267,31 +1256,31 @@ inkscape:document-rotation="0" inkscape:snap-global="true" inkscape:snap-page="true" - showguides="false" + showguides="true" inkscape:window-maximized="1" - inkscape:window-y="-8" + inkscape:window-y="54" inkscape:window-x="-8" - inkscape:window-height="1122" + inkscape:window-height="1009" inkscape:window-width="1920" units="px" showgrid="true" - inkscape:current-layer="g11134" + inkscape:current-layer="layer1" inkscape:document-units="px" - inkscape:cy="606.78571" - inkscape:cx="481.42857" - inkscape:zoom="1.4" + inkscape:cy="551.79583" + inkscape:cx="563.16004" + inkscape:zoom="1.979899" inkscape:pageshadow="2" inkscape:pageopacity="0.0" borderopacity="1.0" bordercolor="#666666" pagecolor="#ffffff" id="base" - inkscape:showpageshadow="2" inkscape:pagecheckerboard="0" + inkscape:showpageshadow="2" inkscape:deskcolor="#d1d1d1"> - - - - BUSY CDC - - - - - - - - - - - - - - - - - - Ethernet - UART - DDRx - SPI - I + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C - Interrupts - - Timer - - - MEMORY INTERCONNECT - Zedboard - - - FMC CONNECTOR - - - AD463X_DMA - 80MHz - - - - ARM (Zynq) - Zynq SoC - - - SPI ENGINE FRAMEWORK - - - - - - - - - - MISO/SDI[7:0] - CS - MOSI/SDO - SCLK - - - - - ECHO SCLK - - - AXI PWMGEN - - CNV - - - - AXI CLKGEN - - - spi_clk = 160MHz - sys_clk = 100MHz - - - - - - - - REF_CLK - 100MHz - - - INTERCONNECT - - - - - BUSY - trigger - - - EVAL-AD4030-24 - EVAL-AD4630-24 - CLK_MODE=0 NUM_OF_SDI=1 CAPTURE_ZONE=1 NO_REORDER=1 (ad4030)CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=1 NO_REORDER=1 (ad4630) - + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.8633px;font-family:Arial;-inkscape-font-specification:'Arial Bold';baseline-shift:super;stroke-width:1.1434px">2C + Interrupts + + Timer + + MEMORY INTERCONNECT + Zedboard + + + FMC CONNECTOR + + + AD463X_DMA + 80MHz + + + ARM (Zynq) + Zynq SoC + + + + + MISO/SDI[7:0] + SPI ENGINE FRAMEWORK + CS + MOSI/SDO + SCLK + + + + + + + + AXI PWMGEN + GPIO + CNV + BUSY + TRIGGER + + AXI CLKGEN + spi_clk = 160MHz + sys_clk = 100MHz + + + + + + + + REF_CLK + 100MHz + + INTERCONNECT + + ECHO SCLK + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - + id="g8811" + transform="matrix(1.2472877,0,0,1.2472877,-157.97249,-19.934072)" + style="fill:#ffffff;fill-opacity:1;stroke:#ffffff;stroke-opacity:1;shape-rendering:crispEdges"> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#ffffff;stroke-width:0.479248;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + d="m 371.16019,393.86166 h 6.77743 v 5.24892 h -6.77743 z" + id="rect8801" /> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#ffffff;stroke-width:0.479248;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + d="m 383.3136,393.86166 h 6.77743 v 5.24892 h -6.77743 z" + id="rect8809" /> + + + + + + + + + + + + + + + + + + + + + + + + 32b - - - OFFLOAD - - - + id="g6072" + transform="translate(0,-60)"> REGMAP + style="font-size:16px;stroke-width:2.5">OFFLOAD + trigger + + REGMAP + + EXECUTION + + transform="translate(80.562487,34.316332)"> + y="883.24304" + x="267.07892" + height="40.000015" + width="84.999992" + id="rect35512-6-7-6" + style="display:inline;fill:#e5e5e5;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1.50881;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;paint-order:normal;shape-rendering:crispEdges;enable-background:new" /> EXECUTION + style="font-size:16px;text-align:center;text-anchor:middle;stroke-width:2.2387" + id="tspan6907-3">BUSY CDC + + OR + + + + + diff --git a/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz2_1.svg b/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz2_1.svg index 6e689309e32..d3755516eea 100644 --- a/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz2_1.svg +++ b/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz2_1.svg @@ -1,13 +1,13 @@ - - - + inkscape:stockid="TriangleOutM" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243078" + preserveAspectRatio="xMidYMid"> + + + + style="display:inline;opacity:1;fill:#000000;fill-opacity:0;fill-rule:nonzero;stroke:#000000;stroke-width:1.51069;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> + style="display:inline;opacity:1;vector-effect:none;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.1981;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> AXI PWMGEN - - CNV @@ -1771,15 +1763,15 @@ sodipodi:nodetypes="cc" inkscape:connector-curvature="0" id="path1206-1-0-95-1-7-7" - d="M 685.12089,322.41327 H 534.11429" + d="M 685.12089,398.14977 H 534.11429" style="display:inline;fill:none;stroke:#000000;stroke-width:2.18646;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1216-0-3-1-2-9-5);shape-rendering:crispEdges;enable-background:new" /> REF_CLK @@ -1787,13 +1779,13 @@ xml:space="preserve" style="font-style:normal;font-weight:normal;font-size:11.6611px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.874582" x="594.99811" - y="341.26895" + y="414.73434" id="text1555" transform="scale(0.97000757,1.0309198)">100MHz ECHO SCLK + + trigger - @@ -2294,5 +2291,72 @@ sodipodi:nodetypes="cc" /> + + GPIO + CNV + TRIGGER + + OR + + diff --git a/docs/projects/ad4630_fmc/ad463x_hdl_cm1_cz2_1.svg b/docs/projects/ad4630_fmc/ad463x_hdl_cm1_cz2_1.svg index d1a6381600d..fe9ea24a31f 100644 --- a/docs/projects/ad4630_fmc/ad463x_hdl_cm1_cz2_1.svg +++ b/docs/projects/ad4630_fmc/ad463x_hdl_cm1_cz2_1.svg @@ -1,13 +1,13 @@ + inkscape:stockid="TriangleOutM" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243078" + preserveAspectRatio="xMidYMid"> + + + @@ -1319,12 +1343,12 @@ + style="display:inline;opacity:1;fill:#000000;fill-opacity:0;fill-rule:nonzero;stroke:#000000;stroke-width:1.52254;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> + style="display:inline;opacity:1;vector-effect:none;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.23233;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> ECHO SCLK AXI PWMGEN - - CNV @@ -1919,15 +1927,15 @@ sodipodi:nodetypes="cc" inkscape:connector-curvature="0" id="path1206-1-0-95-1-7-7" - d="M 721.47882,370.71457 H 570.47222" + d="M 721.47882,462.68032 H 570.47222" style="display:inline;fill:none;stroke:#000000;stroke-width:2.18646;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1216-0-3-1-2-9-5);shape-rendering:crispEdges;enable-background:new" /> REF_CLK @@ -1935,13 +1943,13 @@ xml:space="preserve" style="font-style:normal;font-weight:normal;font-size:11.6611px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.874582" x="646.45837" - y="391.08093" + y="480.28891" id="text1555" transform="scale(0.97000757,1.0309198)">100MHz BUSY + + GPIO + CNV + TRIGGER + + OR + style="fill:none;stroke:#000000;stroke-width:1.24191;stroke-linejoin:round;marker-end:url(#TriangleOutM-2-8-2);shape-rendering:crispEdges" + d="m 549.3846,362.08467 h 70.41318" + id="path3" + sodipodi:nodetypes="cc" /> + + trigger + + + + + + OFFLOAD + - - - - OFFLOAD - - - - - + inkscape:collect="always" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243083" + preserveAspectRatio="xMidYMid"> @@ -213,7 +201,7 @@ @@ -228,7 +216,7 @@ inkscape:stockid="TriangleInM"> @@ -244,7 +232,7 @@ inkscape:stockid="TriangleOutM"> @@ -260,7 +248,7 @@ inkscape:stockid="TriangleInM"> @@ -273,10 +261,14 @@ refX="0" refY="0" orient="auto" - inkscape:stockid="TriangleOutM"> + inkscape:stockid="TriangleOutM" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243078" + preserveAspectRatio="xMidYMid"> @@ -288,12 +280,16 @@ refX="0" id="marker16080" style="overflow:visible" - inkscape:isstock="true"> + inkscape:isstock="true" + viewBox="0 0 8.519053 9.8486161" + markerWidth="8.5190525" + markerHeight="9.8486166" + preserveAspectRatio="xMidYMid"> + + + + inkscape:pagecheckerboard="0" + inkscape:showpageshadow="2" + inkscape:deskcolor="#d1d1d1"> + type="xygrid" + spacingy="1" + spacingx="1" + units="px" + visible="true" /> @@ -1267,1089 +1289,1072 @@ + style="display:inline;opacity:1;fill:#000000;fill-opacity:0;fill-rule:nonzero;stroke:#000000;stroke-width:1.52139;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> + + + + - + transform="matrix(1.1787565,0,0,1.1091093,-162.59067,607.01092)" + id="g1870" + style="shape-rendering:crispEdges"> - - - - - - - - - - - - Ethernet - UART - DDRx - SPI - I2C - Interrupts - - Timer - - - MEMORY INTERCONNECT - Zedboard - - - FMC CONNECTOR - - - AD463X_DMA - 80MHz - - - - ARM (Zynq) - Zynq SoC - - - - - MISO/SDI[4:0] - SPI ENGINE FRAMEWORK - CS - MOSI/SDO - SCLK - - - - - + style="display:inline;fill:#a2dcea;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + d="M 444.94011,-75.71611 V -1.20552" + id="path4179-9" + inkscape:connector-curvature="0" /> + style="display:inline;fill:#a2dcea;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + d="M 342.41856,-75.71611 V -1.20552" + id="path4179-0" + inkscape:connector-curvature="0" /> - - - AXI PWMGEN - GPIO + style="display:inline;fill:#a2dcea;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + d="M 368.04896,-75.71611 V -1.20552" + id="path4179-4" + inkscape:connector-curvature="0" /> + style="display:inline;fill:#a2dcea;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + d="M 393.67935,-75.71611 V -1.20552" + id="path4179-7" + inkscape:connector-curvature="0" /> + style="display:inline;fill:#a2dcea;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + d="M 419.30971,-75.71611 V -1.20552" + id="path4179-41" + inkscape:connector-curvature="0" /> - CNV - PGIA A0 - PGIA A1 - EN - RST + style="display:inline;fill:#a2dcea;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + d="M 316.78817,-75.71611 V -1.20552" + id="path4179-0-3" + inkscape:connector-curvature="0" /> + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + + MEMORY INTERCONNECT + Zedboard + + + FMC CONNECTOR + + + AD463X_DMA + 80MHz + + + + ARM (Zynq) + Zynq SoC + + + + + + MISO/SDI[4:0] + SPI ENGINE FRAMEWORK + CS + MOSI/SDO + SCLK + + + + + + + + + + AXI PWMGEN + GPIO + PGIA A0 + PGIA A1 + EN + RST + - - - + + AXI CLKGEN - + sodipodi:role="line">AXI CLKGEN - spi_clk = 160MHz - sys_clk = 100MHz - - - - - - - - REF_CLK - SYNC - 100MHz + + spi_clk = 160MHz + sys_clk = 100MHz + + + + + + + + REF_CLK + SYNC + 100MHz + 400KHz + + 400KHz - - - INTERCONNECT - - - - - - ECHO SCLK - - - - - + style="font-size:11.6611px;stroke-width:1.74916;stroke-miterlimit:4;stroke-dasharray:none">INTERCONNECT - - - - - - - - - - - - - - - - - + + + ECHO SCLK + + + + + + + + + + + + + + + + + + + + + + - - - - - - + id="g8811" + transform="matrix(1.2472877,0,0,1.2472877,-157.97249,-19.934072)" + style="fill:#ffffff;fill-opacity:1;stroke:#ffffff;stroke-opacity:1;shape-rendering:crispEdges"> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#ffffff;stroke-width:0.479248;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + d="m 371.16019,393.86166 h 6.77743 v 5.24892 h -6.77743 z" + id="rect8801" /> - - - - - - - - - - - - - - - - - - - - - - - - + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#ffffff;stroke-width:0.479248;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + d="m 383.3136,393.86166 h 6.77743 v 5.24892 h -6.77743 z" + id="rect8809" /> + + + + + + + + + + + + + + + + + + + + + + + + - - - OFFLOAD - trigger - - - - + id="g6072"> REGMAP + style="font-size:16px;stroke-width:2.5">OFFLOAD + trigger + + REGMAP + + EXECUTION + id="g6913" + transform="matrix(0.80188679,0,0,1,-95.471692,-0.6545857)" + style="shape-rendering:crispEdges"> + id="rect35512-6-7" + style="display:inline;fill:#e5e5e5;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.34737;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;paint-order:normal;shape-rendering:crispEdges;enable-background:new" /> EXECUTION - - - - - DATA REORDER - - - + sodipodi:role="line" + style="font-size:17.8675px;text-align:center;text-anchor:middle;stroke-width:2.5">DATA REORDER + + + + + + + CNV + + OR + + + + TRIGGER + diff --git a/docs/projects/ad4630_fmc/adaq42xx_hdl_cm1_cz2_1.svg b/docs/projects/ad4630_fmc/adaq42xx_hdl_cm1_cz2_1.svg index c7a14e35315..8c5d7458803 100644 --- a/docs/projects/ad4630_fmc/adaq42xx_hdl_cm1_cz2_1.svg +++ b/docs/projects/ad4630_fmc/adaq42xx_hdl_cm1_cz2_1.svg @@ -1,13 +1,13 @@ @@ -61,7 +61,7 @@ inkscape:connector-curvature="0" id="path6923" d="M 5.77,0 -2.88,5 V -5 Z" - style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1" transform="scale(0.4)" /> + inkscape:collect="always" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243078" + preserveAspectRatio="xMidYMid"> @@ -215,7 +219,7 @@ @@ -230,7 +234,7 @@ inkscape:stockid="TriangleInM"> @@ -243,10 +247,14 @@ refX="0" refY="0" orient="auto" - inkscape:stockid="TriangleOutM"> + inkscape:stockid="TriangleOutM" + viewBox="0 0 4.2595265 4.9243081" + markerWidth="4.2595263" + markerHeight="4.9243078" + preserveAspectRatio="xMidYMid"> @@ -262,7 +270,7 @@ inkscape:stockid="TriangleInM"> @@ -278,7 +286,7 @@ inkscape:stockid="TriangleOutM"> @@ -295,7 +303,7 @@ inkscape:connector-curvature="0" id="path16078" d="M 5.77,0 -2.88,5 V -5 Z" - style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1" transform="scale(-0.8)" /> + + + + inkscape:pagecheckerboard="0" + inkscape:showpageshadow="2" + inkscape:deskcolor="#d1d1d1"> + type="xygrid" + spacingy="1" + spacingx="1" + units="px" + visible="true" /> @@ -1330,1087 +1364,1070 @@ - - - + + DATA CAPTURE - - - - - + sodipodi:role="line" + style="font-size:17.8675px;text-align:center;text-anchor:middle;stroke-width:2.5">DATA CAPTURE + + + + + style="display:inline;opacity:1;fill:#000000;fill-opacity:0;fill-rule:nonzero;stroke:#000000;stroke-width:1.57159;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + + MEMORY INTERCONNECT + Zedboard + + + FMC CONNECTOR + + + AD463X_DMA + 80MHz + + + + ARM (Zynq) + Zynq SoC + + + SPI ENGINE FRAMEWORK + + + + + + id="g4597" + transform="matrix(1.1787565,0,0,1.1091093,-162.59067,683.08501)" + style="shape-rendering:crispEdges"> + id="path1206-1-0" + d="m 528.80556,65.68088 h 145" + style="display:inline;opacity:1;fill:none;stroke:#000000;stroke-width:1.99314;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1216-0-3);shape-rendering:crispEdges;enable-background:new" /> + id="path1206-1-0-8" + d="m 679.80556,105.36783 h -145" + style="display:inline;opacity:1;fill:none;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1216-0-3-9);shape-rendering:crispEdges;enable-background:new" /> - - - - - - - - - - - Ethernet - UART - DDRx - SPI - I2C - Interrupts - - Timer - - + id="path1206-1-0-95-1" + d="m 528.80556,123.60293 h 145" + style="display:inline;opacity:1;fill:none;stroke:#000000;stroke-width:1.98635;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1216-0-3-1-2);shape-rendering:crispEdges;enable-background:new" /> MEMORY INTERCONNECT + y="99.872658" + x="556.22998" + id="tspan2399-1-6-6-1" + sodipodi:role="line">MISO/SDI[7:0] Zedboard - - + y="61.910927" + x="591.82037" + id="tspan2399-1-6-6-1-8-6" + sodipodi:role="line">CS FMC CONNECTOR - - - AD463X_DMA + y="79.966576" + x="564.90875" + id="tspan2399-1-6-6-1-8-1" + sodipodi:role="line">MOSI/SDO 80MHz - - - - ARM (Zynq) - Zynq SoC - - - SPI ENGINE FRAMEWORK - - - - + y="119.83069" + x="585.91302" + id="tspan2399-1-6-6-1-8-62" + sodipodi:role="line">SCLK - - - - - MISO/SDI[7:0] - CS - MOSI/SDO - SCLK - - - - ECHO SCLK - - - AXI PWMGEN + id="path1206-9-4-1" + d="m 612.8521,47.69959 h -20" + style="display:inline;opacity:1;fill:none;stroke:#000000;stroke-width:1.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> - CNV + id="path1206-1-0-95-1-9" + d="m 528.80556,83.67169 h 145" + style="display:inline;opacity:1;fill:none;stroke:#000000;stroke-width:1.99314;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1216-0-3-1-2-0);shape-rendering:crispEdges;enable-background:new" /> + id="path1206-1-0-95-1-75" + d="m 679.84895,44.712924 h -145" + style="display:inline;fill:none;stroke:#000000;stroke-width:1.98635;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1216-0-3-1-2-3);shape-rendering:crispEdges;enable-background:new" /> SYNC + y="40.940685" + x="565.95288" + id="tspan2399-1-6-6-1-8-62-56" + sodipodi:role="line">ECHO SCLK + + + AXI PWMGEN + + SYNC + - - - + + AXI CLKGEN - + sodipodi:role="line">AXI CLKGEN - spi_clk = 160MHz - sys_clk = 100MHz - - - - - - - - REF_CLK - 100MHz + + spi_clk = 160MHz + sys_clk = 100MHz + + + + + + + + REF_CLK + 100MHz + 400KHz + + 400KHz - - - INTERCONNECT - - - - - BUSY - - trigger + style="font-size:11.6611px;stroke-width:1.74916;stroke-miterlimit:4;stroke-dasharray:none">INTERCONNECT - - - - - - - - - - - - - - - - - + + BUSY + trigger + + + + + + + + + + + + + + + + + + + - - - - - - + id="g8811" + transform="matrix(1.2472877,0,0,1.2472877,-157.97249,-19.934072)" + style="fill:#ffffff;fill-opacity:1;stroke:#ffffff;stroke-opacity:1;shape-rendering:crispEdges"> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#ffffff;stroke-width:0.479248;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + d="m 371.16019,393.86166 h 6.77743 v 5.24892 h -6.77743 z" + id="rect8801" /> - - - - - - - - - - - - - - - - - - - - - - - - + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#ffffff;stroke-width:0.479248;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + d="m 383.3136,393.86166 h 6.77743 v 5.24892 h -6.77743 z" + id="rect8809" /> + + + + + + + + + + + + + + + + + + + + + + + + - - - + OFFLOAD - + sodipodi:role="line" + style="font-size:16px;text-align:center;text-anchor:middle;stroke-width:2.5">OFFLOAD + + REGMAP + + EXECUTION + id="g6913" + transform="matrix(0.80188679,0,0,1,62.528288,37.345414)" + style="shape-rendering:crispEdges"> REGMAP - - - - EXECUTION - - - - - DATA REORDER - - + sodipodi:role="line" + style="font-size:17.8675px;text-align:center;text-anchor:middle;stroke-width:2.5">DATA REORDER + GPIO - - + transform="matrix(1.1787565,0,0,1.1091093,-142.5907,624.36742)">GPIO PGIA A0 PGIA A1 EN RST + TRIGGER + style="fill:none;stroke:#000000;stroke-width:1.42;stroke-linejoin:round;marker-end:url(#TriangleOutM-2)" + d="m 450.72277,1000.7445 187.65544,-0.068" + id="path1" + sodipodi:nodetypes="cc" /> + style="fill:none;stroke:#000000;stroke-width:1.42;stroke-linejoin:round;marker-end:url(#TriangleOutM-2)" + d="M 450.00003,1020.6765 H 637.7539" + id="path2" + sodipodi:nodetypes="cc" /> + + + CNV + + OR + + + + diff --git a/docs/projects/ad4630_fmc/index.rst b/docs/projects/ad4630_fmc/index.rst index ef946c57752..c2e2dee529c 100644 --- a/docs/projects/ad4630_fmc/index.rst +++ b/docs/projects/ad4630_fmc/index.rst @@ -111,32 +111,42 @@ SPI mode - transfer zone 1 The main aspect of this mode is the fact that it is using the BUSY signal from the ADC to trigger the Offload module. Data is then clocked out by the -Execution module and transferred to the DMA by the Offload module. CNV is -always generated by the AXI PWM GEN IP core regardless of the mode. Zone 1 -transfer is not currently supported by the pre-compiled HDL files that are -included in the SD card image that is provided with the evaluation board. +Execution module and transferred to the DMA by the Offload module. CNV is an "or" +function of the AXI PWM GEN IP and the ad463x_trigger (EMIO) regardless of the +mode. It is the software responsibility to configure the correct behavior for +the trigger source. Zone 1 transfer is not currently supported by the +pre-compiled HDL files that are included in the SD card image that is provided +with the evaluation board. .. image:: ad463x_hdl_cm0_cz1_1.svg :width: 800 :align: center :alt: AD4630_FMC SPI mode - transfer zone 1 block diagram -For 1 SDI (:adi:`AD4030`) or 2 SDIs (:adi:`AD4630`) a special mode can be built, -that bypasses the spi_axis_reorder IP and connects the SPI Engine Offload directly -to DMA. For **other** number of SDIs this special mode **is not expected to work**. +The DATA REORDER IP (spi_axis_reorder) is instantiated according to the +combination of the NUM_OF_CHANNEL and LANES_PER_CHANNEL parameters. The +following modes does not use the spi_axis_reorder IP and directly connects the +SPI Engine Offload to the DMA: + +- 1 MISO/SDI (:adi:`AD4030`) - NUM_OF_CHANNEL = 1 LANES_PER_CHANNEL = 1; +- 2 MISOs/SDIs (:adi:`AD4030`) - NUM_OF_CHANNEL = 1 LANES_PER_CHANNEL = 2; +- 2 MISOs/SDIs (:adi:`AD4630`) - NUM_OF_CHANNEL = 2 LANES_PER_CHANNEL = 1. + +The last case may instantiate spi_axis_reorder IP if INTERLEAVE_MODE=1 is used. .. image:: ad463x_hdl_cm0_cz1_no_reorder.svg :width: 800 :align: center :alt: AD4630_FMC SPI mode - transfer zone 1 block diagram without using the spi_axis_reorder IP - + SPI mode - transfer zone 2 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -In this mode, the BUSY signal is not used and both the CNV and the Offload -trigger signals are generated by the AXI PWM GEN core. The reason for using two -PWM outputs instead of a common one is to accommodate for the averaging mode -where the two signals will have different frequencies. +In this mode, the BUSY signal is not used. Offload trigger is generated by the AXI +PWM GEN core. CNV is still generated by the "or" function of the AXI PWM GEN and the +ad463x_trigger (EMIO). The reason for using two PWM outputs instead of a common one +is to accommodate for the averaging mode where the two signals will have different +frequencies. .. image:: ad463x_hdl_cm0_cz2_1.svg :width: 800 @@ -153,9 +163,11 @@ Echo clock mode - transfer zone 2 In this configuration, the ADC's BUSY-SCKOUT pin functions as a bit-clock output and is generated by looping-through the host’s SCK. The SPI engine is -driving the SPI signals except it is no longer reading the data. For this -purpose, the Data Capture IP is used. This also allows for reading data in DDR -mode. +driving the SPI signals except it is no longer reading the data. In echo clock +mode, data reading reading is done by a dedicated Data Capture IP that is +configured to capture data either in SDR or DDR mode. +Again, CNV is generated by the "or" function of the AXI PWM GEN and the +ad463x_trigger (EMIO). .. image:: ad463x_hdl_cm1_cz2_1.svg :width: 800 @@ -167,14 +179,32 @@ mode. :align: center :alt: ADAQ4224_FMC Echo clock mode - transfer zone 2 block diagram -The design supports the following interface and clock modes both in SDR and DDR: +The design supports the following modes: + +.. list-table:: + :header-rows: 1 -================== ================== ================== ================== -Mode 1 Lane per channel 2 Lane per channel 4 lane per channel -================== ================== ================== ================== -SPI mode yes yes yes -Echo Clock mode yes yes yes -================== ================== ================== ================== + * - Mode + - 1 Lane per channel + - 2 Lanes per channel + - 4 Lanes per channel + - Interleave + - SDR + - DDR + * - SPI mode + - yes + - yes + - yes + - yes + - yes + - no + * - Echo Clock mode + - yes + - yes + - yes + - yes + - yes + - yes Configuration modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -182,16 +212,20 @@ Configuration modes The CLK_MODE configuration parameter defines clocking mode of the device's digital interface: -- 0 - SPI mode -- 1 - Echo-clock or Master clock mode +- 0 - SPI mode; +- 1 - Echo-clock or Master clock mode. + +The NUM_OF_CHANNEL configuration parameter defines the number of ADC channels: + +- 1 - AD403x devices; +- 2 - AD463x/adaq42xx devices (default). -The NUM_OF_SDI configuration parameter defines the number of MOSI lines of the -SPI interface: +The LANES_PER_CHANNEL configuration parameter defines the number of MISO lanes +per channel of the SPI interface: -- 1 - Interleaved mode -- 2 - 1 lane per channel, -- 4 - 2 lanes per channel -- 8 - 4 lanes per channel +- 1 - 1 lane per channel: Interleaved mode or single lane per channel; +- 2 - 2 lanes per channel; +- 4 - 4 lanes per channel (default). The CAPTURE_ZONE configuration parameter defines the capture zone of the next sample. There are two capture zones: @@ -206,12 +240,13 @@ and master clock mode the SDI lines can have Single or Double Data Rates: - 0 - MISO runs on SDR - 1 - MISO runs on DDR. -The ``NO_REORDER`` configuration parameter removes the spi_axis_reorder IP from -the system for CAPTURE_ZONE = 1 and NUM_OF_SDI = 1 (AD4030) or NUM_OF_SDI = 2 -(AD4630) and directly connects the SPI Engine to DMA: +The INTERLEAVE_MODE configuration parameter defines whether the interleaved +mode is enabled or disabled. Interleaved mode can be only used for +NUM_OF_CHANNEL = 2 and LANES_PER_CHANNEL = 1 (ad463x). Enabling INTERLEAVE_MODE +for any other configuration is invalid. -- 0 - spi_axis_reorder present (default) -- 1 - spi_axis_reorder removed +- 0 - interleave mode disabled, each channel has their own MISO lanes. (default); +- 1 - interleave mode enabled, the ad463x ADC share the same MISO lanes. CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -318,6 +353,10 @@ The Software GPIO number is calculated as follows: - INOUT - 35 - 89 + * - ad463x_trigger + - OUT + - 36 + - 90 .. admonition:: Legend :class: note @@ -360,11 +399,11 @@ by the configuration used: if the following command was run -``make NUM_OF_SDI=4 CAPTURE_ZONE=2`` +``make NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2`` then the folder name will be: -``NUMOFSDI4_CAPTUREZONE2`` +``NUMOFCHANNEL2_NUMOFSDI4_CAPTUREZONE2`` A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. From 1b35e5b980886a9e3b4909b2d79791160a7d37d5 Mon Sep 17 00:00:00 2001 From: caosjr Date: Thu, 27 Nov 2025 14:54:40 -0300 Subject: [PATCH 3/3] update: review fixes Signed-off-by: Carlos Souza --- projects/ad4630_fmc/common/ad463x_bd.tcl | 2 +- projects/ad4630_fmc/zed/Makefile | 15 +++---- projects/ad4630_fmc/zed/system_constr.xdc | 34 +++++++-------- .../ad4630_fmc/zed/system_constr_1sdi_1ch.xdc | 6 +-- .../ad4630_fmc/zed/system_constr_1sdi_2ch.xdc | 20 --------- .../zed/system_constr_1sdi_2ch_interleave.xdc | 6 +-- .../ad4630_fmc/zed/system_constr_2sdi_1ch.xdc | 8 ++-- .../ad4630_fmc/zed/system_constr_2sdi_2ch.xdc | 15 +++---- .../ad4630_fmc/zed/system_constr_4sdi_1ch.xdc | 4 +- .../ad4630_fmc/zed/system_constr_4sdi_2ch.xdc | 42 +++++++------------ .../ad4630_fmc/zed/system_constr_8sdi_2ch.xdc | 37 ++++++++++++++++ projects/ad4630_fmc/zed/system_project.tcl | 24 +++++------ projects/ad4630_fmc/zed/system_top.v | 2 +- 13 files changed, 108 insertions(+), 107 deletions(-) delete mode 100644 projects/ad4630_fmc/zed/system_constr_1sdi_2ch.xdc create mode 100644 projects/ad4630_fmc/zed/system_constr_8sdi_2ch.xdc diff --git a/projects/ad4630_fmc/common/ad463x_bd.tcl b/projects/ad4630_fmc/common/ad463x_bd.tcl index 5a3eaf4c424..e25ba1537b7 100644 --- a/projects/ad4630_fmc/common/ad463x_bd.tcl +++ b/projects/ad4630_fmc/common/ad463x_bd.tcl @@ -13,7 +13,7 @@ set DDR_EN $ad_project_params(DDR_EN) set INTERLEAVE_MODE $ad_project_params(INTERLEAVE_MODE) if {$INTERLEAVE_MODE == 1} { - if {$LANES_PER_CHANNEL > 1 || $NUM_OF_CHANNEL != 2} { + if {$LANES_PER_CHANNEL != 1 || $NUM_OF_CHANNEL != 2} { puts "ERROR: Interleave mode is only supported with 2 channels (NUM_OF_CHANNEL == 2) and 1 lane per channel (LANES_PER_CHANNEL == 1)." exit 2 } diff --git a/projects/ad4630_fmc/zed/Makefile b/projects/ad4630_fmc/zed/Makefile index 03e1d7dd054..7506d13987f 100644 --- a/projects/ad4630_fmc/zed/Makefile +++ b/projects/ad4630_fmc/zed/Makefile @@ -1,18 +1,19 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### PROJECT_NAME := ad4630_fmc_zed -M_DEPS += system_constr_4sdi_2ch.xdc -M_DEPS += system_constr_4sdi_1ch.xdc -M_DEPS += system_constr_2sdi_2ch.xdc -M_DEPS += system_constr_2sdi_1ch.xdc -M_DEPS += system_constr_1sdi_2ch_interleave.xdc -M_DEPS += system_constr_1sdi_2ch.xdc M_DEPS += system_constr_1sdi_1ch.xdc +M_DEPS += system_constr_1sdi_2ch_interleave.xdc +M_DEPS += system_constr_2sdi_1ch.xdc +M_DEPS += system_constr_2sdi_2ch.xdc +M_DEPS += system_constr_4sdi_1ch.xdc +M_DEPS += system_constr_4sdi_2ch.xdc +M_DEPS += system_constr_8sdi_2ch.xdc + M_DEPS += ../common/ad463x_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc diff --git a/projects/ad4630_fmc/zed/system_constr.xdc b/projects/ad4630_fmc/zed/system_constr.xdc index 1a2dae34580..71743b8bd71 100644 --- a/projects/ad4630_fmc/zed/system_constr.xdc +++ b/projects/ad4630_fmc/zed/system_constr.xdc @@ -1,25 +1,25 @@ ############################################################################### -## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### # ad463x_fmc SPI interface -set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo] ; ## C11 FMC_LA06_N -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sclk] ; ## G6 FMC_LA00_CC_P -set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_cs] ; ## G7 FMC_LA00_CC_N - -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad463x_echo_sclk] ; ## D20 FMC_LA17_CC_P -set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad463x_resetn] ; ## D9 FMC_LA01_CC_N -set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_busy] ; ## C22 FMC_LA18_CC_P -set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_cnv] ; ## D8 FMC_LA01_CC_P -set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_ext_clk] ; ## H4 FMC_CLK0_P - -set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[0]}] ; ## G12 FMC-LA08_P -set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[1]}] ; ## G13 FMC-LA08_N - -set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst] ; ## H13 FMC-LA07_P -set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en] ; ## H14 FMC-LA07_N -set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk] ; ## D21 FMC-LA17_N_CC +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sclk] ; ## G6 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_cs] ; ## G7 FMC_LPC_LA00_CC_N + +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad463x_echo_sclk] ; ## D20 FMC_LPC_LA17_CC_P +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad463x_resetn] ; ## D9 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_busy] ; ## C22 FMC_LPC_LA18_CC_P +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_cnv] ; ## D8 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_ext_clk] ; ## H4 FMC_LPC_CLK0_P + +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[0]}] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[1]}] ; ## G13 FMC_LPC_LA08_N + +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk] ; ## D21 FMC_LPC_LA17_N_CC # external clock, that drives the CNV generator, must have a maximum 100 MHz frequency create_clock -period 10.000 -name cnv_ext_clk [get_ports ad463x_ext_clk] diff --git a/projects/ad4630_fmc/zed/system_constr_1sdi_1ch.xdc b/projects/ad4630_fmc/zed/system_constr_1sdi_1ch.xdc index c72e814af6a..0b5025203d6 100644 --- a/projects/ad4630_fmc/zed/system_constr_1sdi_1ch.xdc +++ b/projects/ad4630_fmc/zed/system_constr_1sdi_1ch.xdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -10,7 +10,7 @@ set tsetup 5.6 set thold 1.4 -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi}] ; ## H07 FMC_LA02_P +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi}] ; ## H07 FMC_LPC_LA02_P set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi] \ No newline at end of file +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi] diff --git a/projects/ad4630_fmc/zed/system_constr_1sdi_2ch.xdc b/projects/ad4630_fmc/zed/system_constr_1sdi_2ch.xdc deleted file mode 100644 index 14e0d0d2cb6..00000000000 --- a/projects/ad4630_fmc/zed/system_constr_1sdi_2ch.xdc +++ /dev/null @@ -1,20 +0,0 @@ -############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# Constraints for 1 SDI per channel, 2 Channels configuration with reorder (NO_REORDER=0) -# This results in 2 SDI lines total -# input delays for MISO lines (SDO for the device) -# data is latched on negative edge - -set tsetup 5.6 -set thold 1.4 - -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H10 FMC_LA04_P - -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[1]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[1]}] \ No newline at end of file diff --git a/projects/ad4630_fmc/zed/system_constr_1sdi_2ch_interleave.xdc b/projects/ad4630_fmc/zed/system_constr_1sdi_2ch_interleave.xdc index e4eae28b315..a7675265904 100644 --- a/projects/ad4630_fmc/zed/system_constr_1sdi_2ch_interleave.xdc +++ b/projects/ad4630_fmc/zed/system_constr_1sdi_2ch_interleave.xdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -11,7 +11,7 @@ set tsetup 5.6 set thold 1.4 -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LPC_LA02_P set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}] \ No newline at end of file +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}] diff --git a/projects/ad4630_fmc/zed/system_constr_2sdi_1ch.xdc b/projects/ad4630_fmc/zed/system_constr_2sdi_1ch.xdc index d5ce52057b9..b5dbe7105b9 100644 --- a/projects/ad4630_fmc/zed/system_constr_2sdi_1ch.xdc +++ b/projects/ad4630_fmc/zed/system_constr_2sdi_1ch.xdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -10,10 +10,10 @@ set tsetup 5.6 set thold 1.4 -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LA02_N +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LPC_LA02_N set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]] \ No newline at end of file +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]] diff --git a/projects/ad4630_fmc/zed/system_constr_2sdi_2ch.xdc b/projects/ad4630_fmc/zed/system_constr_2sdi_2ch.xdc index 47bea30eff9..d1342aa104f 100644 --- a/projects/ad4630_fmc/zed/system_constr_2sdi_2ch.xdc +++ b/projects/ad4630_fmc/zed/system_constr_2sdi_2ch.xdc @@ -1,25 +1,20 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### -# Constraints for 2 SDI per channel, 2 Channels configuration (4 SDI lines total) +# Constraints for 1 SDI per channel, 2 Channels configuration with reorder (NO_REORDER=0) +# This results in 2 SDI lines total # input delays for MISO lines (SDO for the device) # data is latched on negative edge set tsetup 5.6 set thold 1.4 -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LA02_N -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] ; ## H10 FMC_LA04_P -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[3]}] ; ## H11 FMC_LA04_N +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H10 FMC_LPC_LA04_P set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[1]}] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[1]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[2]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[2]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[3]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[3]}] \ No newline at end of file diff --git a/projects/ad4630_fmc/zed/system_constr_4sdi_1ch.xdc b/projects/ad4630_fmc/zed/system_constr_4sdi_1ch.xdc index 3f12c9481c9..d7486a705a4 100644 --- a/projects/ad4630_fmc/zed/system_constr_4sdi_1ch.xdc +++ b/projects/ad4630_fmc/zed/system_constr_4sdi_1ch.xdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -22,4 +22,4 @@ set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_p set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[2]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[2]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[3]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[3]] \ No newline at end of file +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[3]] diff --git a/projects/ad4630_fmc/zed/system_constr_4sdi_2ch.xdc b/projects/ad4630_fmc/zed/system_constr_4sdi_2ch.xdc index db34ea59f4d..35c81ab3ff9 100644 --- a/projects/ad4630_fmc/zed/system_constr_4sdi_2ch.xdc +++ b/projects/ad4630_fmc/zed/system_constr_4sdi_2ch.xdc @@ -1,37 +1,25 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### -# Constraints for 4 SDI per channel, 2 Channels configuration (8 SDI lines total) +# Constraints for 2 SDI per channel, 2 Channels configuration (4 SDI lines total) # input delays for MISO lines (SDO for the device) # data is latched on negative edge set tsetup 5.6 -set thold 1.6 +set thold 1.4 -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[3]] ; ## G10 FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[4]] ; ## H10 FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[5]] ; ## H11 FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[6]] ; ## D11 FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[7]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[3]}] ; ## H11 FMC_LPC_LA04_N -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[2]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[2]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[3]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[3]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[4]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[4]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[5]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[5]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[6]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[6]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[7]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[7]] \ No newline at end of file +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[1]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[1]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[2]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[2]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[3]}] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[3]}] diff --git a/projects/ad4630_fmc/zed/system_constr_8sdi_2ch.xdc b/projects/ad4630_fmc/zed/system_constr_8sdi_2ch.xdc new file mode 100644 index 00000000000..d709c5729a5 --- /dev/null +++ b/projects/ad4630_fmc/zed/system_constr_8sdi_2ch.xdc @@ -0,0 +1,37 @@ +############################################################################### +## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# Constraints for 4 SDI per channel, 2 Channels configuration (8 SDI lines total) +# input delays for MISO lines (SDO for the device) +# data is latched on negative edge + +set tsetup 5.6 +set thold 1.6 + +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[3]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[4]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[5]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[6]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[7]] ; ## D12 FMC_LPC_LA05_N + +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[2]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[2]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[3]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[3]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[4]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[4]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[5]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[5]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[6]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[6]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[7]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[7]] diff --git a/projects/ad4630_fmc/zed/system_project.tcl b/projects/ad4630_fmc/zed/system_project.tcl index b4483e297e4..6701e80a9f9 100644 --- a/projects/ad4630_fmc/zed/system_project.tcl +++ b/projects/ad4630_fmc/zed/system_project.tcl @@ -75,17 +75,17 @@ adi_project_files ad4630_fmc_zed [list \ switch [get_env_param LANES_PER_CHANNEL 2] { 1 { - # For 1 SDI, check NUM_OF_CHANNEL + # For 1 lane per channel, check NUM_OF_CHANNEL if {[get_env_param NUM_OF_CHANNEL 2] == 1} { - # 1 channel, 1 SDI + # 1 channel, 1 SDI lane adi_project_files ad4630_fmc_zed [list \ "system_constr_1sdi_1ch.xdc" ] } else { # 2 channels, check INTERLEAVE_MODE if {[get_env_param INTERLEAVE_MODE 0] == 0} { - # INTERLEAVE_MODE=0: 2 SDI lines (1 per channel) + # INTERLEAVE_MODE=0: 2 SDI lanes (1 per channel) adi_project_files ad4630_fmc_zed [list \ - "system_constr_1sdi_2ch.xdc" ] + "system_constr_2sdi_2ch.xdc" ] } else { # INTERLEAVE_MODE=1: valid for AD463x only, both channels share the same SDI line adi_project_files ad4630_fmc_zed [list \ @@ -94,27 +94,27 @@ switch [get_env_param LANES_PER_CHANNEL 2] { } } 2 { - # For 2 SDI, check NUM_OF_CHANNEL + # For 2 lanes per channel, check NUM_OF_CHANNEL if {[get_env_param NUM_OF_CHANNEL 2] == 1} { - # 1 channel, 2 SDI + # 1 channel, 2 SDI lanes adi_project_files ad4630_fmc_zed [list \ "system_constr_2sdi_1ch.xdc" ] } else { - # 2 channels, 4 SDI total (2 per channel) + # 2 channels, 4 SDI lanes (2 per channel) adi_project_files ad4630_fmc_zed [list \ - "system_constr_2sdi_2ch.xdc" ] + "system_constr_4sdi_2ch.xdc" ] } } 4 { - # For 4 SDI, check NUM_OF_CHANNEL + # For 4 lanes per channel, check NUM_OF_CHANNEL if {[get_env_param NUM_OF_CHANNEL 2] == 1} { - # 1 channel, 4 SDI + # 1 channel, 4 SDI lanes adi_project_files ad4630_fmc_zed [list \ "system_constr_4sdi_1ch.xdc" ] } else { - # 2 channels, 8 SDI total (4 per channel) + # 2 channels, 8 SDI lanes (4 per channel) adi_project_files ad4630_fmc_zed [list \ - "system_constr_4sdi_2ch.xdc" ] + "system_constr_8sdi_2ch.xdc" ] } } default { diff --git a/projects/ad4630_fmc/zed/system_top.v b/projects/ad4630_fmc/zed/system_top.v index 5a191e414ee..d9d95116818 100644 --- a/projects/ad4630_fmc/zed/system_top.v +++ b/projects/ad4630_fmc/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are