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@Csomi Csomi released this Mar 26, 2019 · 1 commit to hdl_2018_r2 since this release

Changelog:

  1. Supported tools version for this release are:

  2. Major updates:

    • all unsupported projects are moved to a different branch
    • GTM projects are moved to gtm_projects branch (precision converters with SPI Engine)
    • CORDIC based DDS
    • several DMAC improvements
  3. Library updates:

    • Generic transport layer core for JESD204
  4. New projects:

    • USRPE31x
  5. Reference links: TBD

Assets 2

@Csomi Csomi released this Jun 22, 2018 · 1 commit to hdl_2018_r1 since this release

Changelog:

  1. Supported tools version for this release are:

  2. Major updates:

    • Improve Make files.
    • Delete or move deprecated or unused projects: usrpe31x, adrv9364z7020_ccusb, adrv9364z7035_ccusb, adrv9364z7020_ccpci, adv7511_ac701, adv7511_kcu105, adv7511_mitx, adv7511_vc707, adv7511_kc705, cftls, usb_fx3, cn0363_microzed, fmcomms2_ac701, fmcomms2_mitx045, m2k_zed, imageon_zc706
    • Move GTM projects to different branch (gtm_projects)
  3. Library updates:

    • general cleanup of warnings
    • explicitly define clocks and resets in Xilinx IP
    • axi_clkgen supports Ultrascale
  4. New projects:

    • adrv9009_zcu102
    • sidekiqz2
  5. Reference links:

Assets 2
Apr 13, 2018
The following deprecated porjects can be found here:
  * ADRV9361Z7035_ccpci_lvds

  * ADRV9361Z7035_ccusb_lvds

  * ADRV9364Z7020_ccusb_lvds

  * ADRV7511 with VC707, KC705 and KCU105

@Csomi Csomi released this Feb 18, 2018

Change log:

  1. Supported tools version for this release are:
  2. Major updates:
  3. Library updates:
    • 1PPS receiver for axi_ad9361
    • avl_dacfifo for pl_ddrx offload (integrated to adrv9371/a10soc)
    • util_upack/util_rfifo - add valid signal turn around
  4. Projects updates:
    • Rename pzsdr1 to adrv9364z7020
    • Rename pzsdr2 to adrv9361z7035
    • Several new porting:
      • adrv9371x to kcu105/zcu102
      • fmcomms2 to kcu105
      • daq1 to zed
      • daq3 to zcu102
    • Add adrv9379/zc706
    • Add util_dacfifo to daq3/a10gx
    • Add ad738x_fmc/zed

Note: The A10GX based projects may fail from time to time, as the synthesizer, router and mapper may not find a valid configuration. In case this happens, try regenerating the design with reduced address width for the ADC/DAC BRAM FIFOs.

*EXCEPTIONS: All the projects, that are using ZCU102 development platform, should be built with Vivado 2017.2, simply because Vivado 2016.4 does not support the production version of the FPGA (xczu9eg-ffvb1156-2-i).

Assets 2

@Csomi Csomi released this Apr 21, 2017

Change log:

  1. Supported tools version for this release are:
  2. Major updates:
    • IP cores that are specific to FPGA devices are moved into their own respective folders (altera/xilinx)
    • The JESD transceiver frame work has changed. The IP cores now support asymmetrical lane sharing across transmit and receive links while supporting dynamic reconfiguration. The Xilinx projects, the ADI transceiver cores may now be replaced with Xilinx JESD PHY IP at the expense of Eye Scan function.
    • The AD9361 IP core for Altera supports 1R1T mode as well as separate clock, receive and transmit primitives. The core supports both Cyclone V and Arria 10 devices.
    • Additional features added to axi_ad9361 IP core:
      • CMOS support
      • New parameters for finer data path configuration
      • TDD support, with optional ENABLE/TXNRX pin control by software.
    • Altera support for axi_ad9152
    • Add xilinx/axi_dacfifo for high speed DAC paths
  3. Library changes:
    • Added new IP cores:
      • util_adxcvr
      • avl_adxcvr
      • axi_adxcvr
      • axi_ad9684
      • axi_ad9162
      • axi_ad7616
    • Removed obsolete and unsupported cores:
      • util_jesd_gt
      • util_gtlb
      • axi_jesd_gt
  4. Project changes:
    • Supports Arria 10 SOC, Zynq MP SOC Ultrascale+ devices
    • DAQ1: add CPLD logic and new ADC core (axi_ad9684)
    • PZSDR moved to PZSDR2
    • FMCOMMS2: add support for A10GX and ZCU102
    • Removed obsolete and unsupported projects
      • FMCOMMS6
    • New projects:
      • ADRV9371X
      • FMCOMMS11
      • PZSDR1
      • PLUTO
      • USRPE31X
  5. Unsupported or in development projects (do NOT use):
    • The FMCOMMS2 projects on Arria 10 devices is provided as a template ONLY. The project will NOT work on hardware (A10GX or A10SOC) due to Altera's lack of knowledge on their device bank/FMC pin assignments.
    • CFTL_CIP and CFTL_STD
    • FMCOMMS2 ZC706 Partial Reconfiguration (zc706pr)
Assets 2

@Csomi Csomi released this Dec 12, 2016 · 4 commits to hdl_2016_r1 since this release

Change log:

  1. Supported tools version for this release are :
  2. Library changes :
    • fix data clipping for AXI_HDMI_TX
    • patch for UTIL_DACFIFO
  3. Project changes: None
  4. New projects:
    • AD7768EVB

Note: The project using the KCU105 carrier requires the following patches

The setup we use is listed below, you may change it to suit your needs.

AR66031
  1. Download the zip file from www.xilinx.com/support/answers/66031.html
  2. mkdir -p /opt/Xilinx/Vivado/2015.4/KCU105/AR66031
  3. unzip ~/Downloads/AR66031_Vivado_2015_4_preliminary_rev66031.zip
    -d /opt/Xilinx/Vivado/2015.4/KCU105/AR66031/
  4. export MYVIVADO=/opt/Xilinx/Vivado/2015.4/KCU105/AR66031/vivado
AR66052
  1. Download the verilog file from www.xilinx.com/support/answers/66052.html
  2. mkdir -p /opt/Xilinx/Vivado/2015.4/KCU105/AR66052
  3. cp ~/Downloads/gig_ethernet_pcs_pma_1_serdes_1_to_10_ser8.v
    /opt/Xilinx/Vivado/2015.4/KCU105/AR66052/bd_0_pcs_pma_0_serdes_1_to_10_ser8.v
  4. sed -i 's/gig_ethernet_pcs_pma_1/bd_0_pcs_pma_0/g'
    /opt/Xilinx/Vivado/2015.4/KCU105/AR66052/bd_0_pcs_pma_0_serdes_1_to_10_ser8.v
Assets 2
Jul 20, 2016
axi_dacfifo: Optimize the AXI read logic
Save the valid AXI beats number of the last AXI transaction, and the valid
DMA beats number of the last AXI beat, so the read back logic can use this
data and prevent to feel up the CDC memory with invalid samples. Also in
this way the end of the read back cycle get a more robust control: no more
duplicated samples at the end of the buffer.
May 13, 2016
DAQ2 A10GX 10AX115S3F45E2SGE3 version

@Csomi Csomi released this Mar 18, 2016 · 2549 commits to master since this release

Change log:

  1. The supported tools version for this release are :
  2. Library changes :
    • AXI_JESD_GT core has changed to support per lane control to allow asymmetrical transmit and receive lane sharing.
    • ALL core parameter names made consistent and follow the new naming convention
    • Added DAC FIFO, this core allows to store custom DAC samples from memory, and play back at full rate
    • IPs for Altera have updated interfaces for easier connectivity in QSYS
    • AXI_DMAC auto-detects asynchronous clock configuration
  3. Project changes :
    • Added CPACK / UPACK to FMCOMMS1, FMCOMMS5, FMCOMMS6, MOTCON2_FMC projects
    • FMCOMMS2: ARRADIO added (replaces C5SOC)
    • DAQ2: Added DAC FIFO
  4. New projects :
    • PicozedSDR (ccfmc/ccbrk/ccpci)
    • DAQ2 for A10GX
    • DAQ2 KCU105 support
    • DAQ3 ZC706
  5. Unsupported or in development projects (do NOT use)
    • DAQ1 ZC706
    • FMCJESDADC1 A5SOC
    • USDRX1 A5GT and ZC706
    • USB-FX3 ZC706
    • CFTL_CIP and CFTL_STD
    • FMCOMMS2 ZC706 Partial Reconfiguration (zc706pr)
    • FMCADC5 VC707
Assets 2
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