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ad6676: Add support for external clock mode
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@dbogdan
dbogdan committed Dec 14, 2015
1 parent ec4bcce commit 26d1dbd
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Showing 5 changed files with 169 additions and 42 deletions.
66 changes: 29 additions & 37 deletions ad6676-ebz/ad6676_ebz.c
View file
Expand Up @@ -53,17 +53,29 @@
/******************************************************************************/
#ifdef _XPARAMETERS_PS_H_
#define SPI_DEVICE_ID XPAR_PS7_SPI_0_DEVICE_ID
#define GPIO_BASEADDR XPAR_PS7_GPIO_0_BASEADDR
#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
#define GPIO_OFFSET 54 + 32
#define ADC_DDR_BASEADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x800000
#else
#define SPI_DEVICE_ID XPAR_SPI_0_DEVICE_ID
#define GPIO_BASEADDR XPAR_GPIO_0_BASEADDR
#define GPIO_DEVICE_ID XPAR_GPIO_0_DEVICE_ID
#define GPIO_OFFSET 32
#define ADC_DDR_BASEADDR XPAR_AXI_DDR_CNTRL_BASEADDR + 0x800000
#endif
#define AD6676_CORE_BASEADDR XPAR_AXI_AD6676_CORE_BASEADDR
#define AD6676_DMA_BASEADDR XPAR_AXI_AD6676_DMA_BASEADDR
#define AD6676_JESD_BASEADDR XPAR_AXI_AD6676_JESD_BASEADDR
#define AD6676_GT_GT_BASEADDR XPAR_AXI_AD6676_GT_BASEADDR
#define GPIO_ADC_OEN GPIO_OFFSET + 9
#define GPIO_ADC_SELA GPIO_OFFSET + 8
#define GPIO_ADC_SELB GPIO_OFFSET + 7
#define GPIO_ADC_S0 GPIO_OFFSET + 6
#define GPIO_ADC_S1 GPIO_OFFSET + 5
#define GPIO_ADC_RESETB GPIO_OFFSET + 4
#define GPIO_ADC_AGC1 GPIO_OFFSET + 3
#define GPIO_ADC_AGC2 GPIO_OFFSET + 2
#define GPIO_ADC_AGC3 GPIO_OFFSET + 1
#define GPIO_ADC_AGC4 GPIO_OFFSET + 0

/******************************************************************************/
/************************ Variables Definitions *******************************/
Expand Down Expand Up @@ -91,39 +103,18 @@ ad6676_init_param default_init_param = {
16, // jesd_f_frames_per_multiframe
1, // shuffler_control
5, // shuffler_thresh
GPIO_ADC_OEN, // gpio_adc_oen
GPIO_ADC_SELA, // gpio_adc_sela
GPIO_ADC_SELB, // gpio_adc_selb
GPIO_ADC_S0, // gpio_adc_s0
GPIO_ADC_S1, // gpio_adc_s1
GPIO_ADC_RESETB, // gpio_adc_resetb
GPIO_ADC_AGC1, // gpio_adc_agc1
GPIO_ADC_AGC2, // gpio_adc_agc2
GPIO_ADC_AGC3, // gpio_adc_agc3
GPIO_ADC_AGC4, // gpio_adc_agc4
};

/***************************************************************************//**
* @brief ad6676_ebz_gpio_ctl
* gpios:
* adc_oen 9 - 0
* adc_sela 8 - 0
* adc_selb 7 - 1
* adc_s0 6 - 0
* adc_s1 5 - 1
* adc_resetb 4 - 1
* adc_agc1 3 - by default input - 0
* adc_agc2 2 - by default input - 0
* adc_agc3 1 - by default output
* adc_agc4 0 - by default output
*******************************************************************************/
void ad6676_ebz_gpio_ctl(uint32_t base_addr)
{
#ifdef _XPARAMETERS_PS_H_
Xil_Out32((base_addr + 0x02c4), 0x03ff); // direction (6-ctl, 5-status)
Xil_Out32((base_addr + 0x02c8), 0x03ff); // enable
Xil_Out32((base_addr + 0x0018), 0x0000); // mask
Xil_Out32((base_addr + 0x004c), 0x0000); // data
mdelay(10);

Xil_Out32((base_addr + 0x0018), 0x03ff); // mask
Xil_Out32((base_addr + 0x004c), 0x00b0); // data
#else
Xil_Out32((base_addr + 0x000c), 0x0003); // direction
Xil_Out32((base_addr + 0x0008), 0x00b0); // data
#endif
}

/***************************************************************************//**
* @brief main
*******************************************************************************/
Expand All @@ -132,9 +123,10 @@ int main(void)
jesd204b_gt_state jesd204b_gt_st;
jesd204b_state jesd204b_st;

ad6676_ebz_gpio_ctl(GPIO_BASEADDR);

ad6676_setup(SPI_DEVICE_ID, 0, &default_init_param);
ad6676_setup(SPI_DEVICE_ID,
GPIO_DEVICE_ID,
0,
&default_init_param);

jesd204b_gt_st.use_cpll = 1;
jesd204b_gt_st.rx_sys_clk_sel = 0;
Expand All @@ -151,7 +143,7 @@ int main(void)
jesd204b_st.subclass = 1;
jesd204b_setup(AD6676_JESD_BASEADDR, jesd204b_st);

jesd204b_gt_clk_enable(JESD204B_GT_RX);
jesd204b_gt_clk_enable(JESD204B_GT_RX, 0);

adc_setup(AD6676_CORE_BASEADDR, AD6676_DMA_BASEADDR, 2);

Expand Down
8 changes: 8 additions & 0 deletions common_drivers/xilinx_platform_drivers/platform_drivers.c
View file
Expand Up @@ -241,6 +241,14 @@ void gpio_data(uint8_t pin, uint8_t data)
#endif
}

/***************************************************************************//**
* @brief gpio_set_value
*******************************************************************************/
void gpio_set_value(uint8_t pin, uint8_t data)
{
gpio_data(pin, data);
}

/***************************************************************************//**
* @brief mdelay
*******************************************************************************/
Expand Down
3 changes: 3 additions & 0 deletions common_drivers/xilinx_platform_drivers/platform_drivers.h
View file
Expand Up @@ -56,6 +56,8 @@

#define GPIO_OUTPUT 1
#define GPIO_INPUT 0
#define GPIO_HIGH 1
#define GPIO_LOW 0

/******************************************************************************/
/************************ Functions Declarations ******************************/
Expand All @@ -68,6 +70,7 @@ int32_t spi_write_and_read(uint8_t ss, uint8_t *data,
void gpio_init(uint32_t device_id);
void gpio_direction(uint8_t pin, uint8_t direction);
void gpio_data(uint8_t pin, uint8_t data);
void gpio_set_value(uint8_t pin, uint8_t data);
void mdelay(uint32_t msecs);
uint64_t do_div(uint64_t* n, uint64_t base);
#endif
103 changes: 100 additions & 3 deletions drivers/ad6676/ad6676.c
View file
Expand Up @@ -341,6 +341,28 @@ static int32_t ad6676_set_clk_synth(uint32_t refin_Hz, uint32_t freq)
return 0;
}

/***************************************************************************//**
* @brief ad6676_jesd_setup
*******************************************************************************/
static int32_t ad6676_set_extclk_cntl(uint32_t freq)
{
int ret;

xil_printf("%s: frequency %u\n", __func__, freq);

ret = ad6676_spi_write(AD6676_CLKSYN_LOGEN, 0x5);
if (ret < 0)
return ret;

/* Enable EXT CLK and ADC clock */
ret = ad6676_spi_write(AD6676_CLKSYN_ENABLE, /* 2A0 */
EN_EXT_CK | EN_ADC_CK);
if (ret < 0)
return ret;

return 0;
}

/***************************************************************************//**
* @brief ad6676_jesd_setup
*******************************************************************************/
Expand Down Expand Up @@ -447,7 +469,10 @@ static int32_t ad6676_init(void)
if (ret < 0)
return ret;

ad6676_set_clk_synth(phy->ref_clk, phy->pdata->base.f_adc_hz);
if (!phy->pdata->base.use_extclk)
ad6676_set_clk_synth(phy->ref_clk, phy->pdata->base.f_adc_hz);
else
ad6676_set_extclk_cntl(phy->pdata->base.f_adc_hz);

ad6676_jesd_setup(&phy->pdata->jesd);

Expand Down Expand Up @@ -613,15 +638,73 @@ int32_t ad6676_get_attenuation(uint8_t *attenuation)
return 0;
}

/***************************************************************************//**
* @brief ad6676_gpio_config
*******************************************************************************/
int32_t ad6676_gpio_config(void)
{
gpio_direction(phy->pdata->gpio.adc_oen, GPIO_OUTPUT);
gpio_direction(phy->pdata->gpio.adc_sela, GPIO_OUTPUT);
gpio_direction(phy->pdata->gpio.adc_selb, GPIO_OUTPUT);
gpio_direction(phy->pdata->gpio.adc_s0, GPIO_OUTPUT);
gpio_direction(phy->pdata->gpio.adc_s1, GPIO_OUTPUT);
gpio_direction(phy->pdata->gpio.adc_resetb, GPIO_OUTPUT);
gpio_direction(phy->pdata->gpio.adc_agc1, GPIO_OUTPUT);
gpio_direction(phy->pdata->gpio.adc_agc2, GPIO_OUTPUT);
gpio_direction(phy->pdata->gpio.adc_agc3, GPIO_INPUT);
gpio_direction(phy->pdata->gpio.adc_agc4, GPIO_INPUT);

gpio_set_value(phy->pdata->gpio.adc_oen, GPIO_LOW);

switch (phy->pdata->base.decimation) {
case 12:
gpio_set_value(phy->pdata->gpio.adc_s0, GPIO_HIGH);
gpio_set_value(phy->pdata->gpio.adc_s1, GPIO_HIGH);
break;
case 16:
gpio_set_value(phy->pdata->gpio.adc_s0, GPIO_LOW);
gpio_set_value(phy->pdata->gpio.adc_s1, GPIO_HIGH);
break;
case 24:
gpio_set_value(phy->pdata->gpio.adc_s0, GPIO_LOW);
gpio_set_value(phy->pdata->gpio.adc_s1, GPIO_HIGH);
break;
case 32:
gpio_set_value(phy->pdata->gpio.adc_s0, GPIO_LOW);
gpio_set_value(phy->pdata->gpio.adc_s1, GPIO_LOW);
break;
default:
return -1;
}

if (phy->pdata->base.use_extclk) {
gpio_set_value(phy->pdata->gpio.adc_sela, GPIO_HIGH);
gpio_set_value(phy->pdata->gpio.adc_selb, GPIO_LOW);
} else {
gpio_set_value(phy->pdata->gpio.adc_sela, GPIO_LOW);
gpio_set_value(phy->pdata->gpio.adc_selb, GPIO_HIGH);
}

gpio_set_value(phy->pdata->gpio.adc_resetb, GPIO_HIGH);
gpio_set_value(phy->pdata->gpio.adc_agc1, GPIO_LOW);
gpio_set_value(phy->pdata->gpio.adc_agc2, GPIO_LOW);

return 0;
}

/***************************************************************************//**
* @brief ad6676_setup
*******************************************************************************/
int32_t ad6676_setup(uint32_t spi_device_id, uint8_t slave_select,
ad6676_init_param *init_param)
int32_t ad6676_setup(uint32_t spi_device_id,
uint32_t gpio_device_id,
uint8_t slave_select,
ad6676_init_param *init_param)
{
uint8_t reg_id;
uint8_t status;

gpio_init(gpio_device_id);

ad6676_slave_select = slave_select;
spi_init(spi_device_id, 0, 0);

Expand Down Expand Up @@ -665,8 +748,22 @@ int32_t ad6676_setup(uint32_t spi_device_id, uint8_t slave_select,
phy->pdata->shuffler.shuffle_ctrl = init_param->shuffler_control;
phy->pdata->shuffler.shuffle_thresh = init_param->shuffler_thresh;

/* GPIO */
phy->pdata->gpio.adc_oen = init_param->gpio_adc_oen;
phy->pdata->gpio.adc_sela = init_param->gpio_adc_sela;
phy->pdata->gpio.adc_selb = init_param->gpio_adc_selb;
phy->pdata->gpio.adc_s0 = init_param->gpio_adc_s0;
phy->pdata->gpio.adc_s1 = init_param->gpio_adc_s1;
phy->pdata->gpio.adc_resetb = init_param->gpio_adc_resetb;
phy->pdata->gpio.adc_agc1 = init_param->gpio_adc_agc1;
phy->pdata->gpio.adc_agc2 = init_param->gpio_adc_agc2;
phy->pdata->gpio.adc_agc3 = init_param->gpio_adc_agc3;
phy->pdata->gpio.adc_agc4 = init_param->gpio_adc_agc4;

phy->pdata->base.attenuation = 12;

ad6676_gpio_config();

ad6676_spi_read(AD6676_CHIP_ID0, &reg_id);
if (reg_id != CHIPID0_AD6676) {
xil_printf("Unrecognized CHIP_ID 0x%X\n", reg_id);
Expand Down
31 changes: 29 additions & 2 deletions drivers/ad6676/ad6676.h
View file
Expand Up @@ -323,10 +323,24 @@ struct ad6676_shuffler_conf {
uint8_t shuffle_thresh;
};

struct ad6676_gpio {
int32_t adc_oen;
int32_t adc_sela;
int32_t adc_selb;
int32_t adc_s0;
int32_t adc_s1;
int32_t adc_resetb;
int32_t adc_agc1;
int32_t adc_agc2;
int32_t adc_agc3;
int32_t adc_agc4;
};

struct ad6676_platform_data {
struct ad6676_base_conf base;
struct ad6676_jesd_conf jesd;
struct ad6676_shuffler_conf shuffler;
struct ad6676_gpio gpio;
uint8_t spi3wire;
};

Expand Down Expand Up @@ -363,15 +377,28 @@ typedef struct
/* Shuffler Configuration */
uint8_t shuffler_control;
uint8_t shuffler_thresh;
/* GPIOs */
int32_t gpio_adc_oen;
int32_t gpio_adc_sela;
int32_t gpio_adc_selb;
int32_t gpio_adc_s0;
int32_t gpio_adc_s1;
int32_t gpio_adc_resetb;
int32_t gpio_adc_agc1;
int32_t gpio_adc_agc2;
int32_t gpio_adc_agc3;
int32_t gpio_adc_agc4;
}ad6676_init_param;

/******************************************************************************/
/************************ Functions Declarations ******************************/
/******************************************************************************/
int32_t ad6676_spi_read(uint16_t reg_addr, uint8_t *reg_data);
int32_t ad6676_spi_write(uint16_t reg_addr, uint8_t reg_data);
int32_t ad6676_setup(uint32_t spi_device_id, uint8_t slave_select,
ad6676_init_param *init_param);
int32_t ad6676_setup(uint32_t spi_device_id,
uint32_t gpio_device_id,
uint8_t slave_select,
ad6676_init_param *init_param);
int32_t ad6676_set_if_frequency(uint32_t if_freq_hz);
int32_t ad6676_get_if_frequency(uint32_t *if_freq_hz);
int32_t ad6676_set_if_bandwidth(uint32_t if_bw_hz);
Expand Down

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