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Implementação, em VHDL, das instruções MIPS: ADDU, ADDIU, SUBU, ORI, LW, LUI, SLL, SRL, SLT, SW, JR, BEQ
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README
mips.vhd
testbench.vhd

README

Implementação, em VHDL, das instruções MIPS: ADDU, ADDIU, SUBU, ORI, LW, LUI, SLL, SRL, SLT, SW, JR, BEQ

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Trabalho de Arquitetura de Computadores, UNISC 2011/2
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