From 5f1748cfa0d8991ac013394295547343da12e4e7 Mon Sep 17 00:00:00 2001 From: andreil Date: Fri, 8 Jun 2018 22:14:45 +0300 Subject: [PATCH] =?UTF-8?q?=D0=9F=D0=B5=D1=80=D0=B2=D0=B8=D1=87=D0=BD?= =?UTF-8?q?=D0=B0=D1=8F=20=D0=BF=D1=80=D0=BE=D1=88=D0=B8=D0=B2=D0=BA=D0=B0?= =?UTF-8?q?=20CPLD.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Готова дешифрация вектора прерывания (не завершено) и выдача безвейтовых данных. --- .gitignore | 11 + fw_cpld/sim.vwf | 1202 +++++++++++++++++++++++++++++++++++++ fw_cpld/trig_inner.vhd | 67 +++ fw_cpld/usb_kbd.qsf | 81 ++- fw_cpld/usb_kbd.vhd | 126 ++-- fw_cpld/vector_decode.vhd | 55 ++ 6 files changed, 1495 insertions(+), 47 deletions(-) create mode 100644 fw_cpld/sim.vwf create mode 100644 fw_cpld/trig_inner.vhd create mode 100644 fw_cpld/vector_decode.vhd diff --git a/.gitignore b/.gitignore index f511195..11ea1ff 100644 --- a/.gitignore +++ b/.gitignore @@ -17,3 +17,14 @@ Listings *.hex *bak *.crf + +# Quartus files +*/incremental_db/* +*/db/* +.* +*/output_files/* +*/simulation/* +*.temp +*.rpt +*.ddb +*.qws diff --git a/fw_cpld/sim.vwf b/fw_cpld/sim.vwf new file mode 100644 index 0000000..df07e8e --- /dev/null +++ b/fw_cpld/sim.vwf @@ -0,0 +1,1202 @@ +/* Simulator = ModelSim */ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("iorqgen") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("vector") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 8; + LSB_INDEX = 0; + DIRECTION = BIDIR; + PARENT = ""; +} + +SIGNAL("vector[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vector"; +} + +SIGNAL("vector[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vector"; +} + +SIGNAL("vector[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vector"; +} + +SIGNAL("vector[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vector"; +} + +SIGNAL("vector[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vector"; +} + +SIGNAL("vector[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vector"; +} + +SIGNAL("vector[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vector"; +} + +SIGNAL("vector[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vector"; +} + +SIGNAL("zaddr") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 16; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("zaddr[15]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[14]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zaddr[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "zaddr"; +} + +SIGNAL("zdata") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 8; + LSB_INDEX = 0; + DIRECTION = BIDIR; + PARENT = ""; +} + +SIGNAL("zdata[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "zdata"; +} + +SIGNAL("zdata[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "zdata"; +} + +SIGNAL("zdata[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "zdata"; +} + +SIGNAL("zdata[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "zdata"; +} + +SIGNAL("zdata[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "zdata"; +} + +SIGNAL("zdata[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "zdata"; +} + +SIGNAL("zdata[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "zdata"; +} + +SIGNAL("zdata[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "zdata"; +} + +SIGNAL("ziorqn") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("zrdn") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("zwrn") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("zwaitn") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 100; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + } + } +} + +TRANSITION_LIST("iorqgen") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("vector[7]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("vector[6]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("vector[5]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("vector[4]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("vector[3]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("vector[2]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("vector[1]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("vector[0]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[15]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[14]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[13]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[12]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[11]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[10]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[9]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("zaddr[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("zdata[7]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("zdata[6]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("zdata[5]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("zdata[4]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("zdata[3]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("zdata[2]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("zdata[1]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("zdata[0]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("ziorqn") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zrdn") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("zwrn") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("zwaitn") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "iorqgen"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "vector"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 2; + TREE_LEVEL = 0; + CHILDREN = 3, 4, 5, 6, 7, 8, 9, 10; +} + +DISPLAY_LINE +{ + CHANNEL = "vector[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 2; +} + +DISPLAY_LINE +{ + CHANNEL = "vector[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 2; +} + +DISPLAY_LINE +{ + CHANNEL = "vector[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 2; +} + +DISPLAY_LINE +{ + CHANNEL = "vector[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 2; +} + +DISPLAY_LINE +{ + CHANNEL = "vector[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 2; +} + +DISPLAY_LINE +{ + CHANNEL = "vector[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 2; +} + +DISPLAY_LINE +{ + CHANNEL = "vector[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 2; +} + +DISPLAY_LINE +{ + CHANNEL = "vector[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 2; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr"; + EXPAND_STATUS = EXPANDED; + RADIX = Hexadecimal; + TREE_INDEX = 11; + TREE_LEVEL = 0; + CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[15]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[14]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 22; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 23; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 24; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 25; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 26; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zaddr[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 27; + TREE_LEVEL = 1; + PARENT = 11; +} + +DISPLAY_LINE +{ + CHANNEL = "zdata"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 28; + TREE_LEVEL = 0; + CHILDREN = 29, 30, 31, 32, 33, 34, 35, 36; +} + +DISPLAY_LINE +{ + CHANNEL = "zdata[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 29; + TREE_LEVEL = 1; + PARENT = 28; +} + +DISPLAY_LINE +{ + CHANNEL = "zdata[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 30; + TREE_LEVEL = 1; + PARENT = 28; +} + +DISPLAY_LINE +{ + CHANNEL = "zdata[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 31; + TREE_LEVEL = 1; + PARENT = 28; +} + +DISPLAY_LINE +{ + CHANNEL = "zdata[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 32; + TREE_LEVEL = 1; + PARENT = 28; +} + +DISPLAY_LINE +{ + CHANNEL = "zdata[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 33; + TREE_LEVEL = 1; + PARENT = 28; +} + +DISPLAY_LINE +{ + CHANNEL = "zdata[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 34; + TREE_LEVEL = 1; + PARENT = 28; +} + +DISPLAY_LINE +{ + CHANNEL = "zdata[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 35; + TREE_LEVEL = 1; + PARENT = 28; +} + +DISPLAY_LINE +{ + CHANNEL = "zdata[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 36; + TREE_LEVEL = 1; + PARENT = 28; +} + +DISPLAY_LINE +{ + CHANNEL = "ziorqn"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 37; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "zrdn"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 38; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "zwrn"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 39; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "zwaitn"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 40; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/fw_cpld/trig_inner.vhd b/fw_cpld/trig_inner.vhd new file mode 100644 index 0000000..fe069f2 --- /dev/null +++ b/fw_cpld/trig_inner.vhd @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity trig_inner is + port + ( + sig_to_tr : in std_logic; + a16 : in std_logic; + tin : in std_logic; + vector : in std_logic_vector(7 downto 0); + data : in std_logic_vector(7 downto 0); + odata : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture rtl of trig_inner is + +signal kjoy1 : std_logic_vector(4 downto 0); +signal kjoy2 : std_logic_vector(4 downto 0); +signal fjoy : std_logic_vector(4 downto 0); +signal zxkbd0 : std_logic_vector(4 downto 0); +signal zxkbd1 : std_logic_vector(4 downto 0); +signal zxkbd2 : std_logic_vector(4 downto 0); +signal zxkbd3 : std_logic_vector(4 downto 0); +signal zxkbd4 : std_logic_vector(4 downto 0); +signal zxkbd5 : std_logic_vector(4 downto 0); +signal zxkbd6 : std_logic_vector(4 downto 0); +signal zxkbd7 : std_logic_vector(4 downto 0); + +begin + +process (sig_to_tr) +begin + if (rising_edge(sig_to_tr)) then -- end of cycle + case (vector) is + when x"01" => kjoy1 <= data(4 downto 0); + when x"02" => fjoy <= data(4 downto 0); + when x"03" => kjoy2 <= data(4 downto 0); + when x"04" => zxkbd0 <= data(4 downto 0); + when x"05" => zxkbd1 <= data(4 downto 0); + when x"06" => zxkbd2 <= data(4 downto 0); + when x"07" => zxkbd3 <= data(4 downto 0); + when x"08" => zxkbd4 <= data(4 downto 0); + when x"09" => zxkbd5 <= data(4 downto 0); + when x"0a" => zxkbd6 <= data(4 downto 0); + when x"0b" => zxkbd7 <= data(4 downto 0); + when others => fjoy <= (others => 'Z'); + end case; + end if; +end process; + +odata <= "000" & kjoy1 when ((a16 = '1') and (vector = x"1f")) else + --fjoy(4) & "111" & fjoy(3 downto 0) when ((a16 = '1') and (vector = x"7f")) else + "000" & kjoy2 when ((a16 = '1') and (vector = x"df")) else + '0' & tin & '0' & zxkbd0 when (vector = x"04") else + '0' & tin & '0' & zxkbd1 when (vector = x"05") else + '0' & tin & '0' & zxkbd2 when (vector = x"06") else + '0' & tin & '0' & zxkbd3 when (vector = x"07") else + '0' & tin & '0' & zxkbd4 when (vector = x"7f") else + '0' & tin & '0' & zxkbd5 when (vector = x"bf") else + '0' & tin & '0' & zxkbd6 when (vector = x"df") else + '0' & tin & '0' & zxkbd7 when (vector = x"ef") else + x"30" when (vector = x"0f") else + (others => 'Z'); + +end rtl; diff --git a/fw_cpld/usb_kbd.qsf b/fw_cpld/usb_kbd.qsf index c9e0050..1ba20ed 100644 --- a/fw_cpld/usb_kbd.qsf +++ b/fw_cpld/usb_kbd.qsf @@ -51,7 +51,6 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name VHDL_FILE usb_kbd.vhd set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL" set_location_assignment PIN_90 -to clk -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk set_location_assignment PIN_27 -to da[0] set_location_assignment PIN_28 -to da[1] set_location_assignment PIN_29 -to da[2] @@ -79,10 +78,76 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to vector[2] set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to vector[1] set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to vector[0] set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sintn -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to da[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to da[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to da[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to da[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to da[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to da[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to da[1] \ No newline at end of file +set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to da[7] +set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to da[6] +set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to da[5] +set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to da[4] +set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to da[3] +set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to da[2] +set_instance_assignment -name IO_STANDARD "3.3-V PCI" -to da[1] +set_global_assignment -name VHDL_FILE vector_decode.vhd +set_global_assignment -name VHDL_FILE trig_inner.vhd +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED +set_global_assignment -name AUTO_PARALLEL_EXPANDERS ON +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name STATE_MACHINE_PROCESSING AUTO +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name ENABLE_DRC_SETTINGS ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name VECTOR_WAVEFORM_FILE sim.vwf +set_global_assignment -name SIMULATION_MODE FUNCTIONAL +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation +set_location_assignment PIN_87 -to f14 +set_location_assignment PIN_1 -to zdata[0] +set_location_assignment PIN_2 -to zdata[1] +set_location_assignment PIN_5 -to zdata[2] +set_location_assignment PIN_6 -to zdata[3] +set_location_assignment PIN_7 -to zdata[4] +set_location_assignment PIN_8 -to zdata[5] +set_location_assignment PIN_9 -to zdata[6] +set_location_assignment PIN_10 -to zdata[7] +set_location_assignment PIN_100 -to zaddr[15] +set_location_assignment PIN_99 -to zaddr[14] +set_location_assignment PIN_98 -to zaddr[13] +set_location_assignment PIN_97 -to zaddr[12] +set_location_assignment PIN_96 -to zaddr[11] +set_location_assignment PIN_94 -to zaddr[10] +set_location_assignment PIN_93 -to zaddr[9] +set_location_assignment PIN_92 -to zaddr[8] +set_location_assignment PIN_89 -to zaddr[7] +set_location_assignment PIN_88 -to zaddr[6] +set_location_assignment PIN_85 -to zaddr[5] +set_location_assignment PIN_84 -to zaddr[4] +set_location_assignment PIN_83 -to zaddr[3] +set_location_assignment PIN_81 -to zaddr[2] +set_location_assignment PIN_80 -to zaddr[1] +set_location_assignment PIN_79 -to zaddr[0] +set_location_assignment PIN_77 -to zdosn +set_location_assignment PIN_76 -to ziorqn +set_location_assignment PIN_75 -to zm1n +set_location_assignment PIN_72 -to zmreqn +set_location_assignment PIN_71 -to zrdn +set_location_assignment PIN_70 -to zrstn +set_location_assignment PIN_69 -to zwaitn +set_location_assignment PIN_68 -to zwrn +set_location_assignment PIN_19 -to dfrstmn +set_location_assignment PIN_20 -to dasel +set_location_assignment PIN_21 -to extan +set_location_assignment PIN_67 -to iintu +set_location_assignment PIN_64 -to int0n +set_location_assignment PIN_63 -to iorqgen +set_location_assignment PIN_49 -to rdrn +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "d:/Projects/FPGA/orion/usb_keyb/fw_cpld/sim.vwf" +set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS ON +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS" +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH +set_global_assignment -name ECO_OPTIMIZE_TIMING ON +set_global_assignment -name ECO_REGENERATE_REPORT ON +set_global_assignment -name SLOW_SLEW_RATE ON \ No newline at end of file diff --git a/fw_cpld/usb_kbd.vhd b/fw_cpld/usb_kbd.vhd index d8b393e..46c4ca0 100644 --- a/fw_cpld/usb_kbd.vhd +++ b/fw_cpld/usb_kbd.vhd @@ -1,8 +1,8 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.numeric_std.all; entity usb_kbd is - port ( clk : in std_logic; @@ -22,6 +22,7 @@ entity usb_kbd is iintu : in std_logic; zrstn : out std_logic; + zwaitn : out std_logic; iorqgen : out std_logic; iodosn : out std_logic; int0n : out std_logic; @@ -33,59 +34,106 @@ entity usb_kbd is ula : out std_logic; da : inout std_logic_vector( 7 downto 0); - vector : out std_logic_vector(7 downto 0); - sintn : out std_logic + vector : inout std_logic_vector(7 downto 0); + sintn : out std_logic; -- сигнал для обработки прерывания + sintokn : in std_logic; -- обработка прерывания завершена + dfrstmn : in std_logic; -- данные для регистров в CPLD + + zaddr16 : out std_logic; + int_innero: out std_logic; + int_st : out std_logic; + ctrig : out std_logic ); end entity; architecture rtl of usb_kbd is -signal int_to_stm : std_logic; -signal int_vector : std_logic_vector(7 downto 0); + component vector_decode is + port + ( + zaddr : in std_logic_vector(16 downto 0); + vector : out std_logic_vector(7 downto 0); + int_to_stm : out std_logic; + int_inner : out std_logic + ); + end component; + + component trig_inner is + port + ( + sig_to_tr : in std_logic; + a16 : in std_logic; + tin : in std_logic; + vector : in std_logic_vector(7 downto 0); + data : in std_logic_vector(7 downto 0); + odata : out std_logic_vector(7 downto 0) + ); + end component; + +signal int_to_stm : std_logic; +signal int_inner : std_logic; +signal int_vector : std_logic_vector(7 downto 0); -signal zaddr_full : std_logic_vector(16 downto 0); +signal zaddr16i : std_logic; +signal zaddr16clk : std_logic; + +signal dfrstmn_in : std_logic; +signal odata : std_logic_vector(7 downto 0); begin -zaddr_full(15 downto 0) <= zaddr; +zaddr16clk <= zmreqn or zm1n; -process (clk) +process (zaddr16clk) begin - if (rising_edge(clk)) then - if (ziorqn = '1') then - int_vector <= (others => '0'); - int_to_stm <= '1'; - else - if (zaddr_full = "00000000011011111") then -- version ZXMC - int_vector <= "00000001"; - int_to_stm <= '0'; - elsif ((zaddr_full(16) = '1') and (zaddr_full(7 downto 0) = "00011111")) then --Kjoy - int_vector <= "00000010"; - int_to_stm <= '0'; - elsif (zaddr_full(7 downto 0) = "01010111") then --SD data - int_vector <= "00000011"; - int_to_stm <= '0'; - elsif (zaddr_full(7 downto 0) = "01110111") then --SD command - int_vector <= "00000100"; - int_to_stm <= '0'; - elsif ((zaddr_full(16) = '1') and (zaddr_full(7 downto 0) = "01111111")) then --Fjoy - int_vector <= "00000101"; - int_to_stm <= '0'; - elsif ((zaddr_full(16) = '1') and (zaddr_full(7 downto 0) = "11011111")) then --Kjoy - int_vector <= "00000110"; - int_to_stm <= '0'; - else - int_vector <= (others => '0'); - int_to_stm <= '1'; - end if; - end if; + if (rising_edge(zaddr16clk)) then + zaddr16i <= (not (zdata(2) or zdata(5))) and zdata(0) and zdata(1) and zdata(4) and zdata(6) and zdata(7); end if; end process; +dec: vector_decode + port map ( + zaddr => zaddr16i & zaddr, + vector => int_vector, + int_to_stm => int_to_stm, + int_inner => int_inner + ); + +dfrstmn_in <= '0' when ((dfrstmn = '0') and (ziorqn = '1')) + else '1'; +vector <= int_vector when (dfrstmn_in = '1') else (others => 'Z'); + +trig: trig_inner + port map ( + sig_to_tr => dfrstmn_in, + a16 => zaddr16i, + tin => tin, + vector => vector, + data => da, + odata => odata + ); + -- to outputs -sintn <= not int_to_stm; -iorqgen <= not int_to_stm; -vector <= int_vector; +process (int_to_stm, sintokn) +begin + if (sintokn = '0') then + zwaitn <= 'Z'; + elsif (falling_edge(int_to_stm)) then + zwaitn <= '0'; + end if; +end process; +--zwaitn <= int_to_stm and sintokn; +sintn <= int_to_stm; + +zdata <= odata when ((int_inner = '0') and (ziorqn = '0') and (zrdn = '0')) + else (others => 'Z'); + +iorqgen <= int_to_stm and int_inner; + +zaddr16 <= zaddr16i; +int_innero <= int_inner; +int_st <= int_to_stm; +ctrig <= zaddr16clk; end rtl; diff --git a/fw_cpld/vector_decode.vhd b/fw_cpld/vector_decode.vhd new file mode 100644 index 0000000..9b26469 --- /dev/null +++ b/fw_cpld/vector_decode.vhd @@ -0,0 +1,55 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vector_decode is + port + ( + zaddr : in std_logic_vector(16 downto 0); + vector : out std_logic_vector(7 downto 0); + int_to_stm : out std_logic; + int_inner : out std_logic + ); +end entity; + +architecture rtl of vector_decode is + +signal mux_lo : std_logic; +signal mux_hi : std_logic; +signal int_vector_l : std_logic_vector(3 downto 0); +signal int_vector_h : std_logic_vector(3 downto 0); +signal int_vector : std_logic_vector(7 downto 0); + +begin + +mux_lo <= (zaddr(15) and zaddr(3)); +int_vector_l <= zaddr(7 downto 4) when (mux_lo= '1') -- L + else zaddr(3 downto 0); -- l + +mux_hi <= (zaddr(15) and zaddr(3)) or zaddr(7); +int_vector_h <= zaddr(7 downto 4) when (mux_hi = '0') -- h + else zaddr(15 downto 12) when (mux_lo = '0') -- H + else zaddr(11 downto 8); -- L + + +int_vector <= int_vector_h & int_vector_l; + +int_to_stm <= '0' when (int_vector > x"00") else '1'; + +int_inner <= '0' when (((zaddr(16) = '1') and (int_vector = x"1f")) or -- Kjoy1 + ((zaddr(16) = '1') and (int_vector = x"7f")) or -- Fjoy + ((zaddr(16) = '1') and (int_vector = x"df")) or -- Kjoy2 + (int_vector = x"73") or -- K0 + (int_vector = x"b3") or -- K1 + (int_vector = x"d3") or -- K2 + (int_vector = x"e3") or -- K3 + (int_vector = x"7f") or -- K4 + (int_vector = x"bf") or -- K5 + (int_vector = x"df") or -- K6 + (int_vector = x"ef") or -- K7 + (int_vector = x"0f")) -- version + else '1'; + +vector <= int_vector; + +end rtl;