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  • 8 commits
  • 75 files changed
  • 0 commit comments
  • 4 contributors
Commits on Jan 29, 2013
Anthony Gutierrez cache: remove drainManager because it's not used
the cache drainManager is set but never cleared, this is because
the cache itself does not need to be drained and thus never
triggers a signalDrainDone(). because the drainManager variable
is not used properly and does not appear to be necessary it has
been removed with this patch.
af0f8b3
Commits on Jan 31, 2013
Andreas Hansson mem: Separate out the different cases for DRAM bus busy time
This patch changes how the data bus busy time is calculated such that
it is delayed to the actual scheduling time of the request as opposed
to being done as soon as possible.

This patch changes a bunch of statistics, and the stats update is
bundled together with the introruction of tFAW/tTAW and the named DRAM
configurations like DDR3 and LPDDR2.
b7153e2
Ani Udipi mem: Add tTAW and tFAW to the SimpleDRAM model
This patch adds two additional scheduling constraints to the DRAM
controller model, to constrain the activation rate. The two metrics
are determine the size of the activation window in terms of the number
of activates and the minimum time required for that number of
activates. This maps to current DDRx, LPDDRx and WIOx standards that
have either tFAW (4 activate window) or tTAW (2 activate window)
scheduling constraints.
eaa37e6
Andreas Hansson mem: Add DDR3 and LPDDR2 DRAM controller configurations
This patch moves the default DRAM parameters from the SimpleDRAM class
to two different subclasses, one for DDR3 and one for LPDDR2. More can
be added as we go forward.

The regressions that previously used the SimpleDRAM are now using
SimpleDDR3 as this is the most similar configuration.
c4898b1
Andreas Hansson stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
fce3433
Andreas Hansson mem: Add comments for the DRAM address decoding
This patch adds more verbose comments to explain the two different
address mapping schemes of the DRAM controller.
a4288da
Nilay Vaish ruby: correct computation of number of bits required for address
The number of bits required for an address was set to floorLog2(memory size).
This is correct under the assumption that the memory size is a power of 2,
which is not always true. Hence, floorLog2 is being replaced with ceilLog2.
6aed4d4
Commits on Feb 01, 2013
Nilay Vaish sim: remove unused struct priority_compare 87ea04a
Showing with 36,054 additions and 35,833 deletions.
  1. +14 −14 configs/common/FSConfig.py
  2. +93 −19 src/mem/SimpleDRAM.py
  3. +0 −3  src/mem/cache/base.cc
  4. +0 −3  src/mem/cache/base.hh
  5. +1 −1  src/mem/ruby/system/System.cc
  6. +81 −14 src/mem/simple_dram.cc
  7. +16 −0 src/mem/simple_dram.hh
  8. +0 −10 src/sim/eventq.hh
  9. +1 −1  tests/configs/inorder-timing.py
  10. +1 −1  tests/configs/o3-timing-checker.py
  11. +1 −1  tests/configs/o3-timing-mp.py
  12. +1 −1  tests/configs/o3-timing.py
  13. +1 −1  tests/configs/tgen-simple-dram.py
  14. +1,581 −1,581 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
  15. +840 −840 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
  16. +1,181 −1,201 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
  17. +893 −893 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
  18. +1,554 −1,554 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
  19. +882 −882 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
  20. +1,271 −1,274 tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
  21. +1,435 −1,453 tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
  22. +833 −833 tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
  23. +985 −985 tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
  24. +132 −132 tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
  25. +285 −285 tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
  26. +640 −640 tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
  27. +596 −596 tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
  28. +600 −600 tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
  29. +568 −568 tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
  30. +572 −572 tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
  31. +578 −579 tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
  32. +661 −661 tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
  33. +649 −650 tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
  34. +264 −264 tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
  35. +566 −566 tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
  36. +562 −562 tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
  37. +597 −581 tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
  38. +631 −630 tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
  39. +404 −404 tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
  40. +658 −658 tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
  41. +663 −663 tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
  42. +410 −410 tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
  43. +621 −621 tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
  44. +661 −660 tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
  45. +257 −257 tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
  46. +580 −579 tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
  47. +565 −561 tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
  48. +545 −545 tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
  49. +3 −3 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
  50. +67 −3 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
  51. +1,023 −1,023 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
  52. +567 −567 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
  53. +1 −1  tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
  54. +1 −1  tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
  55. +1,020 −1,020 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
  56. +507 −507 tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
  57. +1 −1  tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
  58. +20 −20 tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
  59. +743 −713 tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
  60. +290 −290 tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
  61. +222 −222 tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
  62. +498 −498 tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
  63. +453 −453 tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
  64. +339 −339 tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
  65. +339 −339 tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
  66. +183 −183 tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
  67. +516 −515 tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
  68. +450 −450 tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
  69. +190 −190 tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
  70. +444 −444 tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
  71. +649 −648 tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
  72. +195 −195 tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
  73. +391 −391 tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
  74. +1,955 −1,951 tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
  75. +57 −57 tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt
View
28 configs/common/FSConfig.py
@@ -73,7 +73,7 @@ class BaseTsunami(Tsunami):
# base address (including the PCI config space)
self.bridge = Bridge(delay='50ns',
ranges = [AddrRange(IO_address_space_base, Addr.max)])
- self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
+ self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
self.mem_ranges = [self.physmem.range]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
@@ -110,7 +110,7 @@ class BaseTsunami(Tsunami):
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
pci_func=0, pci_dev=0, pci_bus=0)
- physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
+ physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
self = LinuxAlphaSystem(physmem = physmem)
self.mem_ranges = [self.physmem.range]
if not mdesc:
@@ -180,10 +180,10 @@ def childImage(self, ci):
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)
- self.physmem = SimpleDRAM(range = AddrRange(Addr('1MB'), size = '64MB'),
- zero = True)
- self.physmem2 = SimpleDRAM(range = AddrRange(Addr('2GB'), size ='256MB'),
- zero = True)
+ self.physmem = SimpleDDR3(range = AddrRange(Addr('1MB'), size = '64MB'),
+ zero = True)
+ self.physmem2 = SimpleDDR3(range = AddrRange(Addr('2GB'), size ='256MB'),
+ zero = True)
self.mem_ranges = [self.physmem.range, self.physmem2.range]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
@@ -274,8 +274,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
if bare_metal:
# EOT character on UART will end the simulation
self.realview.uart.end_on_eot = True
- self.physmem = SimpleDRAM(range = AddrRange(Addr(mdesc.mem())),
- zero = True)
+ self.physmem = SimpleDDR3(range = AddrRange(Addr(mdesc.mem())),
+ zero = True)
self.mem_ranges = [self.physmem.range]
else:
self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
@@ -289,10 +289,10 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
- self.physmem = SimpleDRAM(range =
- AddrRange(self.realview.mem_start_addr,
- size = mdesc.mem()),
- conf_table_reported = True)
+ self.physmem = SimpleDDR3(range =
+ AddrRange(self.realview.mem_start_addr,
+ size = mdesc.mem()),
+ conf_table_reported = True)
self.mem_ranges = [self.physmem.range]
self.realview.setupBootLoader(self.membus, self, binary)
self.gic_cpu_addr = self.realview.gic.cpu_addr
@@ -328,7 +328,7 @@ class BaseMalta(Malta):
self.iobus = NoncoherentBus()
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
- self.physmem = SimpleDRAM(range = AddrRange('1GB'))
+ self.physmem = SimpleDDR3(range = AddrRange('1GB'))
self.mem_ranges = [self.physmem.range]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
@@ -434,7 +434,7 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False
self.mem_mode = mem_mode
# Physical memory
- self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
+ self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
self.mem_ranges = [self.physmem.range]
# Platform
View
112 src/mem/SimpleDRAM.py
@@ -63,11 +63,6 @@ class SimpleDRAM(AbstractMemory):
# bus in front of the controller for multiple ports
port = SlavePort("Slave port")
- # the physical organisation of the DRAM
- lines_per_rowbuffer = Param.Unsigned(64, "Row buffer size in cache lines")
- ranks_per_channel = Param.Unsigned(2, "Number of ranks per channel")
- banks_per_rank = Param.Unsigned(8, "Number of banks per rank")
-
# the basic configuration of the controller architecture
write_buffer_size = Param.Unsigned(32, "Number of read queue entries")
read_buffer_size = Param.Unsigned(32, "Number of write queue entries")
@@ -77,21 +72,26 @@ class SimpleDRAM(AbstractMemory):
write_thresh_perc = Param.Percent(70, "Threshold to trigger writes")
# scheduler, address map and page policy
- mem_sched_policy = Param.MemSched('fcfs', "Memory scheduling policy")
+ mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
addr_mapping = Param.AddrMap('openmap', "Address mapping policy")
page_policy = Param.PageManage('open', "Page closure management policy")
+ # the physical organisation of the DRAM
+ lines_per_rowbuffer = Param.Unsigned("Row buffer size in cache lines")
+ ranks_per_channel = Param.Unsigned("Number of ranks per channel")
+ banks_per_rank = Param.Unsigned("Number of banks per rank")
+
# timing behaviour and constraints - all in nanoseconds
# the amount of time in nanoseconds from issuing an activate command
# to the data being available in the row buffer for a read/write
- tRCD = Param.Latency("14ns", "RAS to CAS delay")
+ tRCD = Param.Latency("RAS to CAS delay")
# the time from issuing a read/write command to seeing the actual data
- tCL = Param.Latency("14ns", "CAS latency")
+ tCL = Param.Latency("CAS latency")
# minimum time between a precharge and subsequent activate
- tRP = Param.Latency("14ns", "Row precharge time")
+ tRP = Param.Latency("Row precharge time")
# time to complete a burst transfer, typically the burst length
# divided by two due to the DDR bus, but by making it a parameter
@@ -99,20 +99,24 @@ class SimpleDRAM(AbstractMemory):
# This parameter has to account for bus width and burst length.
# Adjustment also necessary if cache line size is greater than
# data size read/written by one full burst.
- tBURST = Param.Latency("4ns",
- "Burst duration (for DDR burst length / 2 cycles)")
+ tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
# time taken to complete one refresh cycle (N rows in all banks)
- tRFC = Param.Latency("300ns", "Refresh cycle time")
+ tRFC = Param.Latency("Refresh cycle time")
# refresh command interval, how often a "ref" command needs
# to be sent. It is 7.8 us for a 64ms refresh requirement
- tREFI = Param.Latency("7.8us", "Refresh command interval")
+ tREFI = Param.Latency("Refresh command interval")
# write-to-read turn around penalty, assumed same as read-to-write
- tWTR = Param.Latency("1ns", "Write to read switching time")
+ tWTR = Param.Latency("Write to read switching time")
+
+ # time window in which a maximum number of activates are allowed
+ # to take place, set to 0 to disable
+ tXAW = Param.Latency("X activation window")
+ activation_limit = Param.Unsigned("Max number of activates in window")
- # Currently unimplemented, unused, deduced or rolled into other params
+ # Currently rolled into other params
######################################################################
# the minimum amount of time between a row being activated, and
@@ -123,9 +127,79 @@ class SimpleDRAM(AbstractMemory):
# burst length for an access derived from peerBlockSize
- # @todo: Implement tFAW in the model
- # minimum time window in which a maximum of four activates are
- # allowed to take place
- # tFAW = Param.Latency("30ns", "Four activation window")
+# High-level model of a single DDR3 x64 interface (one command and
+# address bus), with default timings based on a DDR3-1600 4 Gbit part,
+# which would amount to 4 Gbyte of memory in 8x8 or 8 GByte in 16x4
+# configuration.
+class SimpleDDR3(SimpleDRAM):
+ # Assuming 64 byte cache lines, use a 2kbyte page size, this
+ # depends on the memory density
+ lines_per_rowbuffer = 32
+
+ # Use two ranks
+ ranks_per_channel = 2
+
+ # DDR3 has 8 banks in all configurations
+ banks_per_rank = 8
+
+ # DDR3-1600 11-11-11
+ tRCD = '13.75ns'
+ tCL = '13.75ns'
+ tRP = '13.75ns'
+
+ # Assuming 64 byte cache lines, across an x64 (8x8 or 16x4)
+ # interface, translates to BL8, 4 clocks @ 800 MHz
+ tBURST = '5ns'
+
+ # DDR3, 4 Gb has a tRFC of 240 CK and tCK = 1.25 ns
+ tRFC = '300ns'
+
+ # DDR3, <=85C, half for >85C
+ tREFI = '7.8us'
+
+ # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
+ tWTR = '7.5ns'
+
+ # With a 2kbyte page size, DDR3-1600 lands around 40 ns
+ tXAW = '40ns'
+ activation_limit = 4
+
+
+# High-level model of a single LPDDR2-S4 x64 interface (one
+# command/address bus), with default timings based on a LPDDR2-1066
+# 4Gbit part, which whould amount to 1 GByte of memory in 2x32 or
+# 2GByte in 4x16 configuration.
+class SimpleLPDDR2_S4(SimpleDRAM):
+ # Assuming 64 byte cache lines, use a 2kbyte page size, this
+ # depends on the memory density
+ lines_per_rowbuffer = 32
+
+ # Use two ranks
+ ranks_per_channel = 2
+
+ # LPDDR2-S4 has 8 banks in all configurations
+ banks_per_rank = 8
+
+ # Fixed at 15 ns
+ tRCD = '15ns'
+
+ # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
+ tCL = '15ns'
+
+ # Pre-charge one bank 15 ns and all banks 18 ns
+ tRP = '18ns'
+
+ # Assuming 64 byte cache lines, across a x64 interface (2x32 or
+ # 4x16), translates to BL8, 4 clocks @ 533 MHz
+ tBURST = '7.5ns'
+
+ # LPDDR2-S4, 4 Gb
+ tRFC = '130ns'
+ tREFI = '3.9us'
+ # Irrespective of speed grade, tWTR is 7.5 ns
+ tWTR = '7.5ns'
+ # Irrespective of size, tFAW is 50 ns
+ tXAW = '50ns'
+ activation_limit = 4
View
3  src/mem/cache/base.cc
@@ -77,7 +77,6 @@ BaseCache::BaseCache(const Params *p)
blocked(0),
noTargetMSHR(NULL),
missCount(p->max_miss_count),
- drainManager(NULL),
addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
system(p->system)
{
@@ -752,8 +751,6 @@ BaseCache::drain(DrainManager *dm)
// Set status
if (count != 0) {
- drainManager = dm;
-
setDrainState(Drainable::Draining);
DPRINTF(Drain, "Cache not drained\n");
return count;
View
3  src/mem/cache/base.hh
@@ -287,9 +287,6 @@ class BaseCache : public MemObject
/** The number of misses to trigger an exit event. */
Counter missCount;
- /** The drain event. */
- DrainManager *drainManager;
-
/**
* The address range to which the cache responds on the CPU side.
* Normally this is all possible memory addresses. */
View
2  src/mem/ruby/system/System.cc
@@ -69,7 +69,7 @@ RubySystem::RubySystem(const Params *p)
if (m_memory_size_bytes == 0) {
m_memory_size_bits = 0;
} else {
- m_memory_size_bits = floorLog2(m_memory_size_bytes);
+ m_memory_size_bits = ceilLog2(m_memory_size_bytes);
}
g_system_ptr = this;
View
95 src/mem/simple_dram.cc
@@ -51,7 +51,7 @@ SimpleDRAM::SimpleDRAM(const SimpleDRAMParams* p) :
AbstractMemory(p),
port(name() + ".port", *this),
retryRdReq(false), retryWrReq(false),
- rowHitFlag(false), stopReads(false),
+ rowHitFlag(false), stopReads(false), actTicks(p->activation_limit, 0),
writeEvent(this), respondEvent(this),
refreshEvent(this), nextReqEvent(this), drainManager(NULL),
bytesPerCacheLine(0),
@@ -64,6 +64,7 @@ SimpleDRAM::SimpleDRAM(const SimpleDRAMParams* p) :
tWTR(p->tWTR), tBURST(p->tBURST),
tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP),
tRFC(p->tRFC), tREFI(p->tREFI),
+ tXAW(p->tXAW), activationLimit(p->activation_limit),
memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
pageMgmt(p->page_policy),
busBusyUntil(0), prevdramaccess(0), writeStartTime(0),
@@ -165,6 +166,11 @@ SimpleDRAM::writeQueueFull() const
SimpleDRAM::DRAMPacket*
SimpleDRAM::decodeAddr(PacketPtr pkt)
{
+ // decode the address based on the address mapping scheme
+ //
+ // with R, C, B and K denoting rank, column, bank and rank,
+ // respectively, and going from MSB to LSB, the two schemes are
+ // RKBC (openmap) and RCKB (closedmap)
uint8_t rank;
uint16_t bank;
uint16_t row;
@@ -175,26 +181,46 @@ SimpleDRAM::decodeAddr(PacketPtr pkt)
// truncate the address to the access granularity
addr = addr / bytesPerCacheLine;
+ // we have removed the lowest order address bits that denote the
+ // position within the cache line, proceed and select the
+ // appropriate bits for bank, rank and row (no column address is
+ // needed)
if (addrMapping == Enums::openmap) {
+ // the lowest order bits denote the column to ensure that
+ // sequential cache lines occupy the same row
addr = addr / linesPerRowBuffer;
+ // after the column bits, we get the bank bits to interleave
+ // over the banks
bank = addr % banksPerRank;
addr = addr / banksPerRank;
+ // after the bank, we get the rank bits which thus interleaves
+ // over the ranks
rank = addr % ranksPerChannel;
addr = addr / ranksPerChannel;
+ // lastly, get the row bits
row = addr % rowsPerBank;
addr = addr / rowsPerBank;
} else if (addrMapping == Enums::closemap) {
+ // optimise for closed page mode and utilise maximum
+ // parallelism of the DRAM (at the cost of power)
+
+ // start with the bank bits, as this provides the maximum
+ // opportunity for parallelism between requests
bank = addr % banksPerRank;
addr = addr / banksPerRank;
+ // next get the rank bits
rank = addr % ranksPerChannel;
addr = addr / ranksPerChannel;
+ // next the column bits which we do not need to keep track of
+ // and simply skip past
addr = addr / linesPerRowBuffer;
+ // lastly, get the row bits
row = addr % rowsPerBank;
addr = addr / rowsPerBank;
} else
@@ -299,13 +325,19 @@ SimpleDRAM::processWriteEvent()
if (pageMgmt == Enums::open) {
bank.openRow = dram_pkt->row;
- bank.freeAt = schedTime + tBURST + accessLat;
+ bank.freeAt = schedTime + tBURST + std::max(accessLat, tCL);
+ busBusyUntil = bank.freeAt - tCL;
- if (!rowHitFlag)
+ if (!rowHitFlag) {
bank.tRASDoneAt = bank.freeAt + tRP;
-
+ recordActivate(bank.freeAt - tCL - tRCD);
+ busBusyUntil = bank.freeAt - tCL - tRCD;
+ }
} else if (pageMgmt == Enums::close) {
bank.freeAt = schedTime + tBURST + accessLat + tRP + tRP;
+ // Work backwards from bank.freeAt to determine activate time
+ recordActivate(bank.freeAt - tRP - tRP - tCL - tRCD);
+ busBusyUntil = bank.freeAt - tRP - tRP - tCL - tRCD;
DPRINTF(DRAMWR, "processWriteEvent::bank.freeAt for "
"banks_id %d is %lld\n",
dram_pkt->rank * banksPerRank + dram_pkt->bank,
@@ -313,13 +345,8 @@ SimpleDRAM::processWriteEvent()
} else
panic("Unknown page management policy chosen\n");
- // @todo: As of now, write goes on the databus asap, maybe
- // be held up at bank. May want to change it to delay the
- // schedTime itself.
- busBusyUntil = schedTime + tBURST;
DPRINTF(DRAMWR,"Done writing to address %lld\n",dram_pkt->addr);
-
DPRINTF(DRAMWR,"schedtime is %lld, tBURST is %lld, "
"busbusyuntil is %lld\n",
schedTime, tBURST, busBusyUntil);
@@ -781,7 +808,8 @@ SimpleDRAM::estimateLatency(DRAMPacket* dram_pkt, Tick inTime)
} else
panic("No page management policy chosen\n");
- DPRINTF(DRAM, "Returning %lld from estimateLatency()\n",accLat);
+ DPRINTF(DRAM, "Returning < %lld, %lld > from estimateLatency()\n",
+ bankLat, accLat);
return make_pair(bankLat, accLat);
}
@@ -793,6 +821,41 @@ SimpleDRAM::processNextReqEvent()
}
void
+SimpleDRAM::recordActivate(Tick act_tick)
+{
+ assert(actTicks.size() == activationLimit);
+
+ DPRINTF(DRAM, "Activate at tick %d\n", act_tick);
+
+ // sanity check
+ if (actTicks.back() && (act_tick - actTicks.back()) < tXAW) {
+ panic("Got %d activates in window %d (%d - %d) which is smaller "
+ "than %d\n", activationLimit, act_tick - actTicks.back(),
+ act_tick, actTicks.back(), tXAW);
+ }
+
+ // shift the times used for the book keeping, the last element
+ // (highest index) is the oldest one and hence the lowest value
+ actTicks.pop_back();
+
+ // record an new activation (in the future)
+ actTicks.push_front(act_tick);
+
+ // cannot activate more than X times in time window tXAW, push the
+ // next one (the X + 1'st activate) to be tXAW away from the
+ // oldest in our window of X
+ if (actTicks.back() && (act_tick - actTicks.back()) < tXAW) {
+ DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier "
+ "than %d\n", activationLimit, actTicks.back() + tXAW);
+ for(int i = 0; i < ranksPerChannel; i++)
+ for(int j = 0; j < banksPerRank; j++)
+ // next activate must not happen before end of window
+ banks[i][j].freeAt = std::max(banks[i][j].freeAt,
+ actTicks.back() + tXAW);
+ }
+}
+
+void
SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt)
{
@@ -822,14 +885,18 @@ SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt)
bank.openRow = dram_pkt->row;
bank.freeAt = curTick() + addDelay + accessLat;
// If you activated a new row do to this access, the next access
- // will have to respect tRAS for this bank. Assume tRAS ~= 3 * tRP
- if (!rowHitFlag)
+ // will have to respect tRAS for this bank. Assume tRAS ~= 3 * tRP.
+ // Also need to account for t_XAW
+ if (!rowHitFlag) {
bank.tRASDoneAt = bank.freeAt + tRP;
-
+ recordActivate(bank.freeAt - tCL - tRCD); //since this is open page,
+ //no tRP by default
+ }
} else if (pageMgmt == Enums::close) { // accounting for tRAS also
- // assuming that tRAS ~= 3 * tRP, and tRAS ~= 4 * tRP, as is common
+ // assuming that tRAS ~= 3 * tRP, and tRC ~= 4 * tRP, as is common
// (refer Jacob/Ng/Wang and Micron datasheets)
bank.freeAt = curTick() + addDelay + accessLat + tRP + tRP;
+ recordActivate(bank.freeAt - tRP - tRP - tCL - tRCD); //essentially (freeAt - tRC)
DPRINTF(DRAM,"doDRAMAccess::bank.freeAt is %lld\n",bank.freeAt);
} else
panic("No page management policy chosen\n");
View
16 src/mem/simple_dram.hh
@@ -46,6 +46,8 @@
#ifndef __MEM_SIMPLE_DRAM_HH__
#define __MEM_SIMPLE_DRAM_HH__
+#include <deque>
+
#include "base/statistics.hh"
#include "enums/AddrMap.hh"
#include "enums/MemSched.hh"
@@ -127,6 +129,9 @@ class SimpleDRAM : public AbstractMemory
*/
bool stopReads;
+ /** List to keep track of activate ticks */
+ std::deque<Tick> actTicks;
+
/**
* A basic class to track the bank state indirectly via
* times "freeAt" and "tRASDoneAt" and what page is currently open
@@ -323,6 +328,15 @@ class SimpleDRAM : public AbstractMemory
*/
Tick maxBankFreeAt() const;
+
+ /**
+ * Keep track of when row activations happen, in order to enforce
+ * the maximum number of activations in the activation window. The
+ * method updates the time that the banks become available based
+ * on the current limits.
+ */
+ void recordActivate(Tick act_tick);
+
void printParams() const;
void printQs() const;
@@ -381,6 +395,8 @@ class SimpleDRAM : public AbstractMemory
const Tick tRP;
const Tick tRFC;
const Tick tREFI;
+ const Tick tXAW;
+ const uint32_t activationLimit;
/**
* Memory controller configuration initialized based on parameter
View
10 src/sim/eventq.hh
@@ -296,16 +296,6 @@ class Event : public Serializable
Priority priority() const { return _priority; }
#ifndef SWIG
- struct priority_compare
- : public std::binary_function<Event *, Event *, bool>
- {
- bool
- operator()(const Event *l, const Event *r) const
- {
- return l->when() >= r->when() || l->priority() >= r->priority();
- }
- };
-
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
#endif
View
2  tests/configs/inorder-timing.py
@@ -39,7 +39,7 @@
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleDRAM(),
+ physmem = SimpleDDR3(),
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
View
2  tests/configs/o3-timing-checker.py
@@ -52,7 +52,7 @@
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleDRAM(),
+ physmem = SimpleDDR3(),
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
View
2  tests/configs/o3-timing-mp.py
@@ -36,7 +36,7 @@
# system simulated
system = System(cpu = cpus,
- physmem = SimpleDRAM(),
+ physmem = SimpleDDR3(),
membus = CoherentBus(),
mem_mode = "timing")
View
2  tests/configs/o3-timing.py
@@ -41,7 +41,7 @@
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleDRAM(),
+ physmem = SimpleDDR3(),
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
View
2  tests/configs/tgen-simple-dram.py
@@ -48,7 +48,7 @@
cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
# system simulated
-system = System(cpu = cpu, physmem = SimpleDRAM(),
+system = System(cpu = cpu, physmem = SimpleDDR3(),
membus = NoncoherentBus(clock="1GHz", width = 16))
# add a communication monitor
View
3,162 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
1,581 additions, 1,581 deletions not shown
View
1,680 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
840 additions, 840 deletions not shown
View
2,382 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
1,181 additions, 1,201 deletions not shown
View
1,786 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
893 additions, 893 deletions not shown
View
3,108 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
1,554 additions, 1,554 deletions not shown
View
1,764 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
882 additions, 882 deletions not shown
View
2,545 tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
1,271 additions, 1,274 deletions not shown
View
2,888 tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
1,435 additions, 1,453 deletions not shown
View
1,666 tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
833 additions, 833 deletions not shown
View
1,970 tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
985 additions, 985 deletions not shown
View
264 tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,80 +1,80 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.204982 # Number of seconds simulated
-sim_ticks 5204982293000 # Number of ticks simulated
-final_tick 5204982293000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.204983 # Number of seconds simulated
+sim_ticks 5204982530500 # Number of ticks simulated
+final_tick 5204982530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 233342 # Simulator instruction rate (inst/s)
-host_op_rate 447673 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 11247967547 # Simulator tick rate (ticks/s)
-host_mem_usage 849540 # Number of bytes of host memory used
-host_seconds 462.75 # Real time elapsed on the host
-sim_insts 107978732 # Number of instructions simulated
-sim_ops 207159910 # Number of ops (including micro ops) simulated
+host_inst_rate 181134 # Simulator instruction rate (inst/s)
+host_op_rate 347511 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8731335326 # Simulator tick rate (ticks/s)
+host_mem_usage 804468 # Number of bytes of host memory used
+host_seconds 596.13 # Real time elapsed on the host
+sim_insts 107979054 # Number of instructions simulated
+sim_ops 207160582 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35152 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 137616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 65352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 864448872 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 69078677 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 864449224 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 69078733 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 87568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 42392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 160958728 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 27339153 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1122193510 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 864448872 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 160958728 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1025407600 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 160961632 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 27339818 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1122197487 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 864449224 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 160961632 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1025410856 # Number of instructions bytes read from this memory
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 48342743 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 21309608 # Number of bytes written to this memory
-system.physmem.bytes_written::total 72643471 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 21309908 # Number of bytes written to this memory
+system.physmem.bytes_written::total 72643771 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 810 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 17202 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 8169 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 108056109 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 12053051 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 108056153 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 12053065 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 10946 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 5299 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 20119841 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 4057514 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 144328941 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 20120204 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 4057615 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 144329463 # Number of read requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 7125507 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 2934421 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 10106666 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 2934464 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 10106709 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 6754 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 26439 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 12556 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 166081040 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 13271645 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 166081100 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 13271655 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 16824 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 8145 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 30923972 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 5252497 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 215599871 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 166081040 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 30923972 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 197005012 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 30924529 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 5252624 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 215600625 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 166081100 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 30924529 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 197005629 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 574662 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 9287782 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 4094079 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 13956526 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 4094136 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 13956583 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 581415 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 26439 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 12559 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 166081040 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 22559427 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 166081100 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 22559437 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 16824 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 8145 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 30923972 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 9346576 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 229556397 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 30924529 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 9346761 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 229557208 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 810 # Total number of read requests seen
system.physmem.writeReqs 46736 # Total number of write requests seen
-system.physmem.cpureqs 47248 # Reqs generatd by CPU via cache - shady
+system.physmem.cpureqs 48918 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 51840 # Total number of bytes read from memory
system.physmem.bytesWritten 2991104 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 35152 # bytesRead derated as per pkt->getSize()
@@ -82,40 +82,40 @@ system.physmem.bytesConsumedWr 2991104 # by
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 298 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 48 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 298 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 96 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 64 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 144 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 2944 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 3168 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 3232 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 3264 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 3120 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 2992 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 2960 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 3096 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 2856 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 2768 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 2640 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 2736 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 2640 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 2560 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 2768 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 2992 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::14 96 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 48 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 2952 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 2848 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 3008 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 2928 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 2928 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 2944 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 3056 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 2944 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 2848 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 2912 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 2848 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 2704 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 2864 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 2864 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 3048 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 3040 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 63181906000 # Total gap between requests
+system.physmem.numWrRetry 1670 # Number of times wr buffer was full causing retry
+system.physmem.totGap 63182142000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@@ -131,7 +131,7 @@ system.physmem.writePktSize::2 0 # ca
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 46736 # categorize write packet sizes
+system.physmem.writePktSize::6 48406 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -176,15 +176,15 @@ system.physmem.rdQLenPdf::29 2 # Wh
system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2032 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2032 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 2032 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 2032 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 2032 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 2032 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 2032 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 2032 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1971 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1995 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 1995 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1996 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1996 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1999 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 1999 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see
@@ -199,37 +199,37 @@ system.physmem.wrQLenPdf::19 2032 # Wh
system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 67 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 61 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 34586744 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 44980744 # Sum of mem lat for all requests
-system.physmem.totBusLat 3240000 # Total cycles spent in databus access
-system.physmem.totBankLat 7154000 # Total cycles spent in bank access
-system.physmem.avgQLat 42699.68 # Average queueing delay per request
-system.physmem.avgBankLat 8832.10 # Average bank access latency per request
-system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 55531.78 # Average memory access latency
+system.physmem.totQLat 40946729 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 52545479 # Sum of mem lat for all requests
+system.physmem.totBusLat 4050000 # Total cycles spent in databus access
+system.physmem.totBankLat 7548750 # Total cycles spent in bank access
+system.physmem.avgQLat 50551.52 # Average queueing delay per request
+system.physmem.avgBankLat 9319.44 # Average bank access latency per request
+system.physmem.avgBusLat 5000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 64870.96 # Average memory access latency
system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.57 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.15 # Average write queue length over time
-system.physmem.readRowHits 716 # Number of row buffer hits during reads
-system.physmem.writeRowHits 45919 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 88.40 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 98.25 # Row buffer hit rate for writes
-system.physmem.avgGap 1328858.49 # Average gap between requests
+system.physmem.readRowHits 696 # Number of row buffer hits during reads
+system.physmem.writeRowHits 45224 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes
+system.physmem.avgGap 1328863.46 # Average gap between requests
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
@@ -290,50 +290,50 @@ system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0
system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
-system.cpu0.numCycles 10407785201 # number of cpu cycles simulated
+system.cpu0.numCycles 10407785676 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 92551705 # Number of instructions committed
-system.cpu0.committedOps 178518504 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 168457719 # Number of integer alu accesses
+system.cpu0.committedInsts 92551747 # Number of instructions committed
+system.cpu0.committedOps 178518572 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 168457773 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 0 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 16414006 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 168457719 # number of integer instructions
+system.cpu0.num_conditional_control_insts 16414014 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 168457773 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 415888508 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 210334532 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 415888554 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 210334552 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_mem_refs 20039545 # number of memory refs
-system.cpu0.num_load_insts 12899818 # Number of load instructions
+system.cpu0.num_mem_refs 20039559 # number of memory refs
+system.cpu0.num_load_insts 12899832 # Number of load instructions
system.cpu0.num_store_insts 7139727 # Number of store instructions
-system.cpu0.num_idle_cycles 9669886063.125444 # Number of idle cycles
-system.cpu0.num_busy_cycles 737899137.874556 # Number of busy cycles
+system.cpu0.num_idle_cycles 9669887298.959074 # Number of idle cycles
+system.cpu0.num_busy_cycles 737898377.040926 # Number of busy cycles
system.cpu0.not_idle_fraction 0.070899 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.929101 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.numCycles 10409964586 # number of cpu cycles simulated
+system.cpu1.numCycles 10409965061 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 15427027 # Number of instructions committed
-system.cpu1.committedOps 28641406 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 28123113 # Number of integer alu accesses
+system.cpu1.committedInsts 15427307 # Number of instructions committed
+system.cpu1.committedOps 28642010 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 28123688 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 0 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1978272 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 28123113 # number of integer instructions
+system.cpu1.num_conditional_control_insts 1978312 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 28123688 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 73027794 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 31865306 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 73029248 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 31865943 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_mem_refs 7025055 # number of memory refs
-system.cpu1.num_load_insts 4066664 # Number of load instructions
-system.cpu1.num_store_insts 2958391 # Number of store instructions
-system.cpu1.num_idle_cycles 10280021112.934025 # Number of idle cycles
-system.cpu1.num_busy_cycles 129943473.065975 # Number of busy cycles
+system.cpu1.num_mem_refs 7025199 # number of memory refs
+system.cpu1.num_load_insts 4066765 # Number of load instructions
+system.cpu1.num_store_insts 2958434 # Number of store instructions
+system.cpu1.num_idle_cycles 10280018133.934025 # Number of idle cycles
+system.cpu1.num_busy_cycles 129946927.065975 # Number of busy cycles
system.cpu1.not_idle_fraction 0.012483 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.987517 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
View
570 tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.269661 # Number of seconds simulated
-sim_ticks 269661304500 # Number of ticks simulated
-final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.269672 # Number of seconds simulated
+sim_ticks 269671683500 # Number of ticks simulated
+final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 98682 # Simulator instruction rate (inst/s)
-host_op_rate 98682 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44214559 # Simulator tick rate (ticks/s)
-host_mem_usage 273520 # Number of bytes of host memory used
-host_seconds 6098.93 # Real time elapsed on the host
+host_inst_rate 125294 # Simulator instruction rate (inst/s)
+host_op_rate 125294 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56139844 # Simulator tick rate (ticks/s)
+host_mem_usage 224468 # Number of bytes of host memory used
+host_seconds 4803.57 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
@@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu
system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 199599 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 6040882 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6240480 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 199599 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 199599 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 240657 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 240657 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 240657 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 199599 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 6040882 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6481138 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 199591 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 6040649 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6240240 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 199591 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 199591 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 240648 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 240648 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 240648 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 199591 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 6040649 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6480888 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 26294 # Total number of read requests seen
system.physmem.writeReqs 1014 # Total number of write requests seen
system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady
@@ -43,41 +43,41 @@ system.physmem.bytesConsumedRd 1682816 # by
system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1718 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1732 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1568 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1581 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1708 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1632 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1673 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1665 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1558 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1618 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1600 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1550 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1652 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1697 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1675 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 76 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 60 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 81 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 53 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 58 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 74 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 1624 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1652 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1676 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1610 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1558 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1549 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1582 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1650 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1645 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1640 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1713 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1657 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1668 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1672 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 59 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 66 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 51 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 49 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 58 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 74 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 59 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 70 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 269661252500 # Total gap between requests
+system.physmem.totGap 269671631500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 17608 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 6157 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 1642 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see
@@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 44 # Wh
system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
@@ -171,56 +171,56 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 364261179 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1024159179 # Sum of mem lat for all requests
-system.physmem.totBusLat 105120000 # Total cycles spent in databus access
-system.physmem.totBankLat 554778000 # Total cycles spent in bank access
-system.physmem.avgQLat 13860.78 # Average queueing delay per request
-system.physmem.avgBankLat 21110.27 # Average bank access latency per request
-system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 38971.05 # Average memory access latency
+system.physmem.totQLat 384531397 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1096635147 # Sum of mem lat for all requests
+system.physmem.totBusLat 131400000 # Total cycles spent in databus access
+system.physmem.totBankLat 580703750 # Total cycles spent in bank access
+system.physmem.avgQLat 14632.09 # Average queueing delay per request
+system.physmem.avgBankLat 22096.79 # Average bank access latency per request
+system.physmem.avgBusLat 5000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 41728.89 # Average memory access latency
system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.04 # Data bus utilization in percentage
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 12.19 # Average write queue length over time
-system.physmem.readRowHits 17406 # Number of row buffer hits during reads
-system.physmem.writeRowHits 51 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes
-system.physmem.avgGap 9874807.84 # Average gap between requests
-system.cpu.branchPred.lookups 86405274 # Number of BP lookups
-system.cpu.branchPred.condPredicted 81476244 # Number of conditional branches predicted
+system.physmem.readRowHits 16315 # Number of row buffer hits during reads
+system.physmem.writeRowHits 296 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes
+system.physmem.avgGap 9875187.91 # Average gap between requests
+system.cpu.branchPred.lookups 86405403 # Number of BP lookups
+system.cpu.branchPred.condPredicted 81476373 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 36343014 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 44773910 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 44774039 # Number of BTB lookups
system.cpu.branchPred.BTBHits 34660000 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 77.411153 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 77.410930 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 114517568 # DTB read hits
+system.cpu.dtb.read_hits 114517881 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 114520199 # DTB read accesses
-system.cpu.dtb.write_hits 39453362 # DTB write hits
+system.cpu.dtb.read_accesses 114520512 # DTB read accesses
+system.cpu.dtb.write_hits 39453501 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 39455664 # DTB write accesses
-system.cpu.dtb.data_hits 153970930 # DTB hits
+system.cpu.dtb.write_accesses 39455803 # DTB write accesses
+system.cpu.dtb.data_hits 153971382 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 153975863 # DTB accesses
-system.cpu.itb.fetch_hits 24997854 # ITB hits
+system.cpu.dtb.data_accesses 153976315 # DTB accesses
+system.cpu.itb.fetch_hits 24997849 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 24997876 # ITB accesses
+system.cpu.itb.fetch_accesses 24997871 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -234,18 +234,18 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 539322610 # number of cpu cycles simulated
+system.cpu.numCycles 539343368 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedNotTaken 49180751 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 541064074 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 1004918560 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 1004918920 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 255160193 # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards 255159834 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 154928367 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken).
@@ -256,12 +256,12 @@ system.cpu.execution_unit.executions 412128439 # Nu
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 535759910 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 535764686 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 295987 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 50789311 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 488533299 # Number of cycles cpu stages are processed.
-system.cpu.activity 90.582759 # Percentage of cycles cpu is active
+system.cpu.timesIdled 296132 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 50809772 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 488533596 # Number of cycles cpu stages are processed.
+system.cpu.activity 90.579328 # Percentage of cycles cpu is active
system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed
@@ -273,77 +273,77 @@ system.cpu.committedInsts 601856964 # Nu
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
-system.cpu.cpi 0.896098 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 0.896132 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 0.896098 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.115950 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 0.896132 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.115907 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 1.115950 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 200593326 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 338729284 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 62.806431 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 228903212 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 310419398 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 57.557275 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 197757745 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 341564865 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 63.332198 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 427944093 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 111378517 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 20.651557 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 192521650 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 346800960 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 64.303063 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total 1.115907 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 200616262 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 338727106 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 62.803610 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 228924009 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 310419359 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 57.555053 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 197778592 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 341564776 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 63.329744 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 427964982 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 111378386 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 20.650738 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 192544683 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 346798685 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 64.300167 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 # number of replacements
-system.cpu.icache.tagsinuse 729.842734 # Cycle average of tags in use
-system.cpu.icache.total_refs 24996820 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 729.833784 # Cycle average of tags in use
+system.cpu.icache.total_refs 24996815 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 29236.046784 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 29236.040936 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 729.842734 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.356369 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.356369 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 24996820 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 24996820 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 24996820 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 24996820 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 24996820 # number of overall hits
-system.cpu.icache.overall_hits::total 24996820 # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst 729.833784 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 24996815 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 24996815 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 24996815 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 24996815 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 24996815 # number of overall hits
+system.cpu.icache.overall_hits::total 24996815 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses
system.cpu.icache.overall_misses::total 1034 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 53126500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 53126500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 53126500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 53126500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 53126500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 53126500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 24997854 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 24997854 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 24997854 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 24997854 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 24997854 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 24997854 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 55838000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 55838000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 55838000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 55838000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 55838000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 55838000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 24997849 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 24997849 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 24997849 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 24997849 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 24997849 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 24997849 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51379.593810 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 51379.593810 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 51379.593810 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 51379.593810 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54001.934236 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 54001.934236 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 54001.934236 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 54001.934236 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 66.500000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
@@ -359,38 +359,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 855
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43645500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 43645500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43645500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 43645500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43645500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 43645500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46086000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 46086000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46086000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 46086000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46086000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 46086000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51047.368421 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51047.368421 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency
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+system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.913059 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 61.333333 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.423968 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
system.cpu.dcache.writebacks::total 436887 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531770 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1531770 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1723952 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1723952 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1723952 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1723952 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191999 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 191999 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531810 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1531810 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1723809 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1723809 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1723809 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1723809 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
@@ -599,14 +599,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645576500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645576500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3734758000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3734758000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6380334500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6380334500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6380334500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6380334500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3783295500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3783295500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426949500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6426949500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426949500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6426949500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
@@ -615,14 +615,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.897611 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.897611 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14694.341820 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14694.341820 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14885.311788 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14885.311788 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
View
1,280 tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
640 additions, 640 deletions not shown
View
1,192 tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
596 additions, 596 deletions not shown
View
1,200 tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
600 additions, 600 deletions not shown
View
1,136 tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
568 additions, 568 deletions not shown
View
1,144 tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
572 additions, 572 deletions not shown
View
1,157 tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
578 additions, 579 deletions not shown
View
1,322 tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
661 additions, 661 deletions not shown
View
1,299 tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
649 additions, 650 deletions not shown
View
528 tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
<
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.139847 # Number of seconds simulated
-sim_ticks 139846906500 # Number of ticks simulated
-final_tick 139846906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.139855 # Number of seconds simulated
+sim_ticks 139855372500 # Number of ticks simulated
+final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 94955 # Simulator instruction rate (inst/s)
-host_op_rate 94955 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 33309069 # Simulator tick rate (ticks/s)
-host_mem_usage 278532 # Number of bytes of host memory used
-host_seconds 4198.46 # Real time elapsed on the host
+host_inst_rate 164436 # Simulator instruction rate (inst/s)
+host_op_rate 164436 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57685897 # Simulator tick rate (ticks/s)
+host_mem_usage 230388 # Number of bytes of host memory used
+host_seconds 2424.43 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu
system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1537224 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1816386 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3353610 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1537224 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1537224 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1537224 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1816386 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3353610 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1537131 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1816276 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3353407 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1537131 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1537131 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1537131 # Total bandwidth to/from this memory (bytes/s)