Code is shared with the ECL version where appropriate.
The package parameter is placed after the name to ensure proper sorting order in the index.
When constant-folding SSE functions or parsing (the ... constant), promote the leaf return type to the precise declared type, instead of using the generic sse-pack.
This information is needed by SSE VOPs to produce correct instructions.
ANG: Some places look like they should be protected by both #-sb-xc-host and #!+sb-sse-intrinsics
We've been using these for a while now, but I neglected to stash copies in the repository. Also instructions for updating them, since it isn't the most intuitive thing in the world.
Analogous to EINTR.
DEFCLASS FTYPE used to break SBCL, but package locks didn't catch it.
lp#902351 Mark %CHECK-BOUND as DX-SAFE, so that vectors of unknown size can be stack allocated.
Read data a word at a time for efficiency's sake. Could do even better with VOPs, but this already wins hugely on sparse vectors -- and works on all backends. (Tested on both little- and big-endian hosts.) This also makes constraint propagation in sparse universes a bit less sucky.
* Non-CONS objects on the control stack can cause... problems in scavenge(). Rewrite scavenge_control_stack() to contain the appropriate (simpler) scavenge code directly.
* Instead of having slightly-divergent copies of the control stack scavenging logic for both GENCGC and CHENEYGC, move the GENCGC version (which is a separate function) to gc-common.c, and alter CHENEYGC to use it instead of doing its own thing inline.
* We possibly should be testing to make sure that they /do/ cons, but we can live with not having an expected failure message for a situation that would take a lot of careful work on the compiler and GC to improve.
* Unless the control stack is conservatively scavenged, any unboxed data could lead the GC to either corrupt the stack, corrupt the heap, or just die screaming. * Thus, all unboxed data must be stored on the number stack on such systems. However, the number stack isn't scavenged for boxed data, so we can't store any object that contains both boxed and unboxed words if the unboxed words can appear to the GC as anything other than a FIXNUM (thus, aligned pointers are safe to store on the control stack). * All INSTANCE objects have a boxed slot, the LAYOUT slot. If an instance also has raw slots then it cannot go on either stack, and must be heap-allocated. * And none of this applies if the stack is conservatively scavenged, which means (and gencgc c-stack-is-control-stack). On such targets, we can dump whatever we want to the control stack, and the GC won't complain at all.
Thanks to Alastair Bridgewater who originally provided these changes (and the headline above). I adapted his work to fit into the prefix instruction infrastructure now available. Of his original comments the following three still apply: * Establish a SEG prefix for segment overrides similar to the X66 data-width prefix. * Have the SEG prefilter set an instruction property for the specific segment being used. * Alter PRINT-MEM-ACCESS to output a suitable prefix for memory addresses when the appropriate instruction property has been set. I have abstracted out the segment prefix printing into the new function MAYBE-PRINT-SEGMENT-OVERRIDE, called from PRINT-MEM-ACCESS, not to make the latter more lengthy. Here is an example to show the difference in disassembler output: Old: ; 0E6: 64 FS-SEGMENT-PREFIX ; 0E7: 8910 MOV [EAX], EDX ; 0E9: 64 FS-SEGMENT-PREFIX ; 0EA: 8B0528000000 MOV EAX, [#x28] New: ; 0E6: 648910 MOV FS:[EAX], EDX ; 0E9: 648B0528000000 MOV EAX, FS:[#x28]
Make LOCK, REP, REX and #x66 true prefix instructions on x86[-64]. This changes only the disassembler part of the instruction definitions; with respect to assembly LOCK already was a true prefix instruction and REP/REPE/REPNE remain instructions in their own right. Delete the scores of instruction formats and printer clauses that are made obsolete by this change. Two printer clauses are still needed for each of those SSE instructions that use the REX prefix in an infix position. An example of the changes in the disassembler output (on x86-64): Old: ; 5FFC: F0 LOCK ; 5FFD: 480FB171F9 CMPXCHG [RCX-7], RSI New: ; 4C: F0480FB171F9 LOCK CMPXCHG [RCX-7], RSI
The double shifts were wrongly matching the bit pattern of some CMOV variants. Corrected by using another instruction format on x86-64 and by adding a constraint on the WIDTH field on x86. This made it possible to enable the variant with an immediate shift count. On x86-64, changed the maximum immediate shift count from 31 to 63. Also, on x86-64, one of the printers for LEA was missing a WIDTH field restriction, thus wrongly matching a "MOV to segment register", too.
In the context of changing the treatment of prefix instructions in the disassembler I came across somewhat broken code to parametrize it. This might as well be repaired, so: Correct the calculation of the DSTATE's ARGUMENT-COLUMN which is intended to set a minimal field width for the opcode column. It needs to take *DISASSEM-INST-COLUMN-WIDTH* and a few more column separators into account. So as not to confuse users, restore the previous behaviour by setting *DISASSEM-OPCODE-COLUMN-WIDTH* to 0. Don't emit instruction bytes when *DISASSEM-INST-COLUMN-WIDTH* is 0. Whitespace correction in ALIGNMENT-HOOK. Playing with these two parameters allows to select different disassembly formats (example from x86-64): Current: ; E11: L7: 4881FB17001020 CMP RBX, 537919511 ; E18: 0F8480000000 JEQ L13 (setf SB-DISASSEM::*DISASSEM-INST-COLUMN-WIDTH* 0) ; E11: L7: CMP RBX, 537919511 ; E18: JEQ L13 (setf SB-DISASSEM:*DISASSEM-OPCODE-COLUMN-WIDTH* 8) ; E11: L7: CMP RBX, 537919511 ; E18: JEQ L13
Instructions having NIL as their printer are treated as prefixes, meaning that they are printed on the same line as the following instruction. If an instruction's PRINT-NAME is NIL, too, this prefix is not printed (but prefilters etc. are run). Any number of prefix instructions can occur in immediate succession before a non-prefix instruction. This commit only provides the infrastructure; its impact is currently limited as there aren't any instructions having NIL as their printer. The motivation for this change comes from x86[-64]: One goal is to make instructions using prefixes like LOCK and REP print nicer, the other to reduce the combinatorial explosion of instruction formats in the disassembler that is currently needed to deal with the possible combinations of the REX and the operand size override (#x66) prefixes and that would become unbearable once the aforementioned and the segment override prefixes are added. Extend the existing beginnings of support for prefix instructions in MAP-SEGMENT-INSTRUCTIONS to collect prefix names and to print them at the right time, which is at the next non-prefix instruction, when a non-decodable instruction is encountered or at the end of the segment. Change the semantics of DSTATE-INST-PROPERTIES: This list is now emptied only after a non-prefix instruction has been processed. Abstract out the filling of the column containing the instruction bytes into the new function PAD-INST-COLUMN and use it in several places. Clean up whitespace and improve line breaks.
* Constant lvars can now be references to assigned-to closure- converted lambda-vars, which don't have consets. Just always use lvar-value, at the cost of a slight potential slowdown due to more calls to find-constant. Reported by Eric Marsden on sbcl-devel. * Also, canonicalize whitespace in dynamic-extent tests. Fixes lp#903838.
Instead of binding *PACKAGE*, bind *READER-PACKAGE* which only affects the package READ-TOKEN interns into in the absence of a prefix. lp#902806