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REFACTOR: Configure layout rlc on cap - #6342

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Samuelopez-ansys merged 4 commits into
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refactor-rlc-to-ports
Jul 1, 2025
Merged

REFACTOR: Configure layout rlc on cap#6342
Samuelopez-ansys merged 4 commits into
mainfrom
refactor-rlc-to-ports

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@hui-zhou-a

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Use point terminals to form ports instead of padstack terminals. This is a workaround to support converting ports to RLC boundary in MCAD when ECAD is imported as a 3dlayout component.

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hui-zhou-a requested a review from a team as a code owner July 1, 2025 07:24
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Thanks for opening a Pull Request. If you want to perform a review write a comment saying:

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codecov Bot commented Jul 1, 2025

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Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 85.36%. Comparing base (d34e771) to head (40fa443).
Report is 3 commits behind head on main.

Additional details and impacted files
@@            Coverage Diff             @@
##             main    #6342      +/-   ##
==========================================
- Coverage   85.36%   85.36%   -0.01%     
==========================================
  Files         175      175              
  Lines       65797    65798       +1     
==========================================
  Hits        56169    56169              
- Misses       9628     9629       +1     
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Comment thread src/ansys/aedt/core/extensions/project/configure_layout.py
@Samuelopez-ansys
Samuelopez-ansys merged commit d60364b into main Jul 1, 2025
@Samuelopez-ansys
Samuelopez-ansys deleted the refactor-rlc-to-ports branch July 1, 2025 10:39
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3 participants