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Antmicro's fast, vendor-neutral DMA IP in Chisel
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project code release 0.1.0 Sep 11, 2019

Fast Versatile DMA

FastVDMA is a DMA controller designed with portability and customizability in mind.

Supported features

  • Interrupts
  • 2D transfers with configurable stride
  • External frame synchronization inputs

Supported busses

  • Data
    • AXI4
    • AXI-Stream
    • Wishbone
  • Control
    • AXI4-Lite
    • Wishbone


FastVDMA performance was tested in synthetic tests that consisted of transferring an NxM buffer with data where N represents the number of 32-bit words and M represents the number of N word rows to transfer.

FastVDMA was verified in the xc7z030fbg676-2 chip achieving an average throughput of 750MB/s, while being clocked at 250MHz, and average of 330MB/s at 100MHz under the same workload. Both the speeds were performed in a Memory-Stream-Memory configuration using two controllers configured with AXI4 and AXI-Stream buses. The first controller reads data from memory and sends it out via an AXI-Stream interface, while the second receives the stream and writes the data received to a second buffer in memory.

Wishbone and AXI4 busses were connected to a LiteDRAM controller providing access to DDR3 memory. Both busses used a 32-bit data bus to connect to the DDR3 controller.

In both cases the data transferred consisted of a 4MB block of randomly produced data which was subsequently verified for possible transmission errors after each transfer.

Resource usage

The AXI4=>AXI-Stream (MM2S) configuration utilized 425 slices on a xc7z030fbg676-2 chip which was used for tesing the design. AXI-Stream=>AXI4 (S2MM) requires 455 slices on the same chip. Both configurations were instantiated in the same design and connected in a back-to-back configuration that allowed memory-to-memory transfers while still using configurations equipped with AXI-Stream interfaces.


Because the controller is written in Chisel, it requires sbt, scala and java to be installed; additionally the tests require imagemagick.


FastVDMA can be simulated as a whole but certain components can be tested separately.

You can simulate the full design by running:

make test

To run all tests, including the full test mentioned above, execute:

make testall

Each testrun generates a .vcd file which can be opened using GTKWave or any other .vcd viewer. Output files are located in a separate subdirectories inside the test_run_dir directory.

The full test should generate an out.png file demonstrating a 2D transfer with configurable stride. The resulting image should look similar to:

Reference image


To generate a synthesizable verilog file, run:

make verilog

The generated file will be named DMATop.v

Customizing FastVDMA

Configuration for the DMA is located in the DMATop file. Most of the settings are defined in the DMATop companion object but to change which busses are used, the DMATop class must be modified to contain correct io bundles and *Frontend modules. After making changes to interfaces used in DMATop class make sure to verify that companion object is correctly configured.

Source code structure

  • src/main/scala/DMAController contains sources of the DMA controller
    • Bus contains definitions of various bus bundles
    • CSR contains code responsible for handling configuration registers
    • Frontend contains modules handling various bus types
    • Worker contains generic code supporting controlling the DMA behaviour
  • src/test/scala/DMAController contains tests
    • Bfm contains Bus models that are used in full configuration tests
    • Frontend contains tests used for generating timing diagrams for various bus types
    • Worker contains tests that generate timinig diagrams for the generic part of the DMA
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