From bc0ab4e1eeac37e6f2714426fb50971463cf3b5e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ob=C5=82onczek?= Date: Tue, 16 Apr 2024 19:29:44 +0200 Subject: [PATCH] Create simple SoC example with simulation, firmware and hello world example MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Internal-tag: [#57628] Signed-off-by: Krzysztof Obłonczek --- .github/scripts/ci.sh | 2 +- examples/soc/Makefile | 56 + examples/soc/README.md | 40 + examples/soc/expected-waveform.svg | 4 + examples/soc/helloworld.asm | 39 + examples/soc/project.yaml | 70 + examples/soc/sim.cpp | 39 + examples/soc/simple_soc.tcl | 71 + examples/soc/simple_soc.xdc | 36 + examples/soc/sources/VexRiscv.v | 5760 ++++++++++++++++++++++++ examples/soc/sources/crg.v | 24 + examples/soc/sources/mem.v | 73 + examples/soc/sources/wb_interconnect.v | 915 ++++ examples/soc/sources/wb_uart.v | 814 ++++ examples/soc/verilator.mk | 13 + 15 files changed, 7955 insertions(+), 1 deletion(-) create mode 100644 examples/soc/Makefile create mode 100644 examples/soc/README.md create mode 100644 examples/soc/expected-waveform.svg create mode 100644 examples/soc/helloworld.asm create mode 100644 examples/soc/project.yaml create mode 100644 examples/soc/sim.cpp create mode 100644 examples/soc/simple_soc.tcl create mode 100644 examples/soc/simple_soc.xdc create mode 100644 examples/soc/sources/VexRiscv.v create mode 100644 examples/soc/sources/crg.v create mode 100644 examples/soc/sources/mem.v create mode 100644 examples/soc/sources/wb_interconnect.v create mode 100644 examples/soc/sources/wb_uart.v create mode 100644 examples/soc/verilator.mk diff --git a/.github/scripts/ci.sh b/.github/scripts/ci.sh index 7b4ed2ce..9f6232c8 100755 --- a/.github/scripts/ci.sh +++ b/.github/scripts/ci.sh @@ -5,7 +5,7 @@ set -e ROOT_DIR=$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")"/../.. &>/dev/null && pwd) -EXAMPLES=(hdmi inout pwm) +EXAMPLES=(hdmi inout pwm soc) begin_command_group() { if [[ -n "${GITHUB_WORKFLOW:-}" ]]; then diff --git a/examples/soc/Makefile b/examples/soc/Makefile new file mode 100644 index 00000000..931310e2 --- /dev/null +++ b/examples/soc/Makefile @@ -0,0 +1,56 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +IPCORE_SOURCES = sources/mem.v sources/VexRiscv.v sources/crg.v sources/wb_uart.v sources/wb_interconnect.v +IPCORE_YAMLS = ipcores/gen_mem.yaml ipcores/gen_VexRiscv.yaml ipcores/gen_crg.yaml ipcores/gen_wb_uart.yaml ipcores/gen_wb_interconnect.yaml + +all: upload + +build: + mkdir build + +ipcores: + mkdir ipcores + +$(IPCORE_YAMLS) &: $(IPCORE_SOURCES) | ipcores + topwrap parse -d ipcores --iface-deduce $(IPCORE_SOURCES) + +build/simple_soc.v: $(IPCORE_YAMLS) project.yaml | build + topwrap build -b build --design project.yaml --sources sources + +build/helloworld.bin: helloworld.asm | build + riscv64-unknown-elf-as -mabi=ilp32 -march=rv32i -o $@ $< + +build/bios.bin: build/helloworld.bin | build + riscv64-unknown-elf-objcopy -O binary $< $@ + +build/bios.init: build/bios.bin | build + hexdump -v -e '1/4 "%08X\n"' $< > $@ + +build/simple_soc.bit: build/bios.init simple_soc.tcl $(IPCORE_SOURCES) build/simple_soc.v | build + vivado -mode batch -source simple_soc.tcl + + +generate: build/simple_soc.v + +build-sim: build/simple_soc.v + $(MAKE) -fverilator.mk + +sim: build-sim build/bios.init obj_dir/Vsimple_soc + obj_dir/Vsimple_soc + vcd2fst build/dump.vcd build/dump.fst + +bitstream: build/simple_soc.bit + +upload: build/simple_soc.bit + openFPGALoader --board antmicro_lpddr4_tester $< + +clean: + rm -rf ipcores + rm -rf build + rm -rf obj_dir + # vivado data + rm -rf .Xil simple_soc.hw simple_soc.cache simple_soc.ip_user_files simple_soc.xpr + rm -f vivado* usage_statistics_webtalk* + +.PHONY: all generate build-sim sim bitstream upload clean diff --git a/examples/soc/README.md b/examples/soc/README.md new file mode 100644 index 00000000..3df30af2 --- /dev/null +++ b/examples/soc/README.md @@ -0,0 +1,40 @@ +# Topwrap SoC example setup + +Copyright (c) 2024 [Antmicro](https://antmicro.com) + +This is an example on how to use [Topwrap](https://github.com/antmicro/topwrap) to build a synthesizable SoC design. +The SoC contains a VexRiscv core, data and instruction memory, UART and interconnect that ties all components together. + +## Install required dependencies + +``` +sudo apt install git make g++ ninja-build gcc-riscv64-unknown-elf bsdextrautils +``` + +To run the simulation you also need: +- verilator + +To create and load bitstream you also need: +- vivado (preferably version 2020.2) +- openFPGALoader ([this branch](https://github.com/antmicro/openFPGALoader/tree/antmicro-ddr-tester-boards)) + +## Generate HDL sources + + +``` +make generate +``` + +## Build and run simulation + +``` +make sim +``` + +Expected waveform generated by the simulation is shown in `expected-waveform.svg`. + +## Generate bitstream + +``` +make bitstream +``` diff --git a/examples/soc/expected-waveform.svg b/examples/soc/expected-waveform.svg new file mode 100644 index 00000000..aeacc99b --- /dev/null +++ b/examples/soc/expected-waveform.svg @@ -0,0 +1,4 @@ + + + +serial_txdecodedhelloworld\r\n \ No newline at end of file diff --git a/examples/soc/helloworld.asm b/examples/soc/helloworld.asm new file mode 100644 index 00000000..360fb21e --- /dev/null +++ b/examples/soc/helloworld.asm @@ -0,0 +1,39 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +loop: + li a0, 0x68 + jal x1, write_char + li a0, 0x65 + jal x1, write_char + li a0, 0x6C + jal x1, write_char + li a0, 0x6C + jal x1, write_char + li a0, 0x6F + jal x1, write_char + li a0, 0x20 + jal x1, write_char + li a0, 0x77 + jal x1, write_char + li a0, 0x6F + jal x1, write_char + li a0, 0x72 + jal x1, write_char + li a0, 0x6C + jal x1, write_char + li a0, 0x64 + jal x1, write_char + li a0, 0x0D + jal x1, write_char + li a0, 0x0A + jal x1, write_char + j loop + +write_char: + li t0, 0xF0000000 # base UART CSR address +wait: + lw t1, 0x4(t0) # load TX_FULL register + bne t1, x0, wait # check if TX fifo not full + sw a0, 0x0(t0) # store character + ret diff --git a/examples/soc/project.yaml b/examples/soc/project.yaml new file mode 100644 index 00000000..3da314f8 --- /dev/null +++ b/examples/soc/project.yaml @@ -0,0 +1,70 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +ips: + vexriscv: + file: ipcores/gen_VexRiscv.yaml + module: VexRiscv + wb_ram_data: + file: ipcores/gen_mem.yaml + module: mem + wb_ram_instr: + file: ipcores/gen_mem.yaml + module: mem + crg: + file: ipcores/gen_crg.yaml + module: crg + wb_uart: + file: ipcores/gen_wb_uart.yaml + module: wb_uart + interconnect: + file: ipcores/gen_wb_interconnect.yaml + module: wb_interconnect + +design: + name: simple_soc + parameters: + wb_ram_data: + depth: 0x1000 + wb_ram_instr: + depth: 0xA000 + memfile: "build/bios.init" + ports: + wb_ram_data: + sys_clk: clk100 + sys_rst: [crg, sys_rst] + wb_ram_instr: + sys_clk: clk100 + sys_rst: [crg, sys_rst] + crg: + clk100: clk100 + vexriscv: + clk: clk100 + reset: [crg, sys_rst] + softwareInterrupt: 0 + externalInterruptArray: 0 + timerInterrupt: 0 + externalResetVector: 0x00000000 + wb_uart: + sys_clk: clk100 + sys_rst: [crg, sys_rst] + serial1_tx: serial_tx + serial1_rx: serial_rx + interconnect: + clk: clk100 + rst: [crg, sys_rst] + interfaces: + interconnect: + wb_uart_csr_wishbone: [wb_uart, csr_wishbone] + wb_ram_instr_mem_bus: [wb_ram_instr, mem_bus] + wb_ram_data_mem_bus: [wb_ram_data, mem_bus] + vexriscv_iBusWishbone: [vexriscv, iBusWishbone] + vexriscv_dBusWishbone: [vexriscv, dBusWishbone] + +external: + ports: + in: + - clk100 + - serial_rx + out: + - serial_tx diff --git a/examples/soc/sim.cpp b/examples/soc/sim.cpp new file mode 100644 index 00000000..069938a7 --- /dev/null +++ b/examples/soc/sim.cpp @@ -0,0 +1,39 @@ +// Copyright (c) 2024 Antmicro +// SPDX-License-Identifier: Apache-2.0 + +#include + +#include +#include +#include +#include + +#include + +#include "Vsimple_soc.h" +#include "verilated_vcd_c.h" + +int main(int argc, char** argv) { + const std::unique_ptr contextp{new VerilatedContext}; + contextp->debug(0); + contextp->randReset(2); + contextp->traceEverOn(true); + contextp->commandArgs(argc, argv); + + const std::unique_ptr soc{new Vsimple_soc{contextp.get(), "simple_soc"}}; + const std::unique_ptr tfp{new VerilatedVcdC}; + soc->trace(tfp.get(), 99); + tfp->open("build/dump.vcd"); + + soc->clk100 = 0; + while (contextp->time() < 225000) { + contextp->timeInc(1); + soc->clk100 = !soc->clk100; + soc->eval(); + tfp->dump(contextp->time()); + } + + soc->final(); + tfp->close(); + return 0; +} diff --git a/examples/soc/simple_soc.tcl b/examples/soc/simple_soc.tcl new file mode 100644 index 00000000..f3e72215 --- /dev/null +++ b/examples/soc/simple_soc.tcl @@ -0,0 +1,71 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +# Create Project + +create_project -force -name simple_soc -part xc7k70tfbg484-3 +set_msg_config -id {Common 17-55} -new_severity {Warning} + +# Add Sources + +read_verilog {sources/crg.v} +read_verilog {sources/mem.v} +read_verilog {sources/VexRiscv.v} +read_verilog {sources/wb_interconnect.v} +read_verilog {sources/wb_uart.v} +read_verilog {build/simple_soc.v} + +# Add constraints + +read_xdc simple_soc.xdc +set_property PROCESSING_ORDER EARLY [get_files simple_soc.xdc] + +# Synthesis + +synth_design -directive default -top simple_soc -part xc7k70tfbg484-3 + +# Synthesis report + +report_timing_summary -file build/top_timing_synth.rpt +report_utilization -hierarchical -file build/top_utilization_hierarchical_synth.rpt +report_utilization -file build/top_utilization_synth.rpt + +# Optimize design + +opt_design -directive default + +# Placement + +place_design -directive default + +# Placement report + +report_utilization -hierarchical -file build/top_utilization_hierarchical_place.rpt +report_utilization -file build/top_utilization_place.rpt +report_io -file build/top_io.rpt +report_control_sets -verbose -file build/top_control_sets.rpt +report_clock_utilization -file build/top_clock_utilization.rpt + +# Routing + +route_design -directive default +phys_opt_design -directive default +write_checkpoint -force build/top_route.dcp + +# Routing report + +report_timing_summary -no_header -no_detailed_paths +report_route_status -file build/top_route_status.rpt +report_drc -file build/top_drc.rpt +report_timing_summary -datasheet -max_paths 10 -file build/top_timing.rpt +report_power -file build/top_power.rpt +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] + +# Bitstream generation + +write_bitstream -force build/simple_soc.bit +write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 build/simple_soc.bit" -file build/simple_soc.bin + +# End + +quit diff --git a/examples/soc/simple_soc.xdc b/examples/soc/simple_soc.xdc new file mode 100644 index 00000000..3a46a359 --- /dev/null +++ b/examples/soc/simple_soc.xdc @@ -0,0 +1,36 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +################################################################################ +# IO constraints +################################################################################ +# clk100:0 +set_property LOC L19 [get_ports {clk100}] +set_property IOSTANDARD LVCMOS33 [get_ports {clk100}] + +# serial:1.tx +set_property LOC AA20 [get_ports {serial_tx}] +set_property IOSTANDARD LVCMOS33 [get_ports {serial_tx}] + +# serial:1.rx +set_property LOC AB20 [get_ports {serial_rx}] +set_property IOSTANDARD LVCMOS33 [get_ports {serial_rx}] + +############################################################################### +# Clock constraints +################################################################################ +create_clock -name clk100 -period 10.0 [get_ports clk100] + +################################################################################ +# False path constraints +################################################################################ +set_false_path -quiet -to [get_cells -hierarchical -filter { mr_ff == TRUE }] + +set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] + +set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]] + +set_max_delay -quiet -through [get_pins -filter {REF_PIN_NAME == Q} -of_objects [get_cells -hierarchical -filter {slow_ff == TRUE}]] 250 + +set_max_delay -quiet -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {slow_in == TRUE}]] 250 + diff --git a/examples/soc/sources/VexRiscv.v b/examples/soc/sources/VexRiscv.v new file mode 100644 index 00000000..596468d9 --- /dev/null +++ b/examples/soc/sources/VexRiscv.v @@ -0,0 +1,5760 @@ +// Generator : SpinalHDL v1.3.5 git head : f0505d24810c8661a24530409359554b7cfa271a +// Date : 09/06/2019, 12:33:14 +// Component : VexRiscv + + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define EnvCtrlEnum_defaultEncoding_type [0:0] +`define EnvCtrlEnum_defaultEncoding_NONE 1'b0 +`define EnvCtrlEnum_defaultEncoding_XRET 1'b1 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input io_cpu_fetch_dataBypassValid, + input [31:0] io_cpu_fetch_dataBypass, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_exception, + input io_cpu_fetch_mmuBus_rsp_refilling, + output io_cpu_fetch_mmuBus_end, + input io_cpu_fetch_mmuBus_busy, + output [31:0] io_cpu_fetch_physicalAddress, + output io_cpu_fetch_haltIt, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [21:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire [0:0] _zz_14_; + wire [0:0] _zz_15_; + wire [21:0] _zz_16_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + reg [31:0] lineLoader_address; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + reg [2:0] lineLoader_wordIndex; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_4_; + wire [6:0] _zz_5_; + wire _zz_6_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_7_; + wire [9:0] _zz_8_; + wire _zz_9_; + wire [31:0] fetchStage_read_waysValues_0_data; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023]; + assign _zz_12_ = (! lineLoader_flushCounter[7]); + assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_14_ = _zz_7_[0 : 0]; + assign _zz_15_ = _zz_7_[1 : 1]; + assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; + end + end + + always @ (posedge clk) begin + if(_zz_6_) begin + _zz_10_ <= ways_0_tags[_zz_5_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_9_) begin + _zz_11_ <= ways_0_datas[_zz_8_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_12_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(lineLoader_fire)begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_4_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; + assign _zz_6_ = (! io_cpu_fetch_isStuck); + assign _zz_7_ = _zz_10_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; + assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; + assign _zz_9_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_11_; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; + assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; + assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = decodeStage_hit_error; + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_13_)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_12_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001)); + end + _zz_3_ <= lineLoader_flushCounter[7]; + if(_zz_13_)begin + lineLoader_flushCounter <= (8'b00000000); + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + input io_cpu_memory_isRemoved, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + output io_cpu_memory_mmuBus_cmd_isValid, + output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, + output io_cpu_memory_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, + input io_cpu_memory_mmuBus_rsp_isIoAccess, + input io_cpu_memory_mmuBus_rsp_allowRead, + input io_cpu_memory_mmuBus_rsp_allowWrite, + input io_cpu_memory_mmuBus_rsp_allowExecute, + input io_cpu_memory_mmuBus_rsp_exception, + input io_cpu_memory_mmuBus_rsp_refilling, + output io_cpu_memory_mmuBus_end, + input io_cpu_memory_mmuBus_busy, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output reg io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [21:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire _zz_14_; + wire _zz_15_; + wire _zz_16_; + wire _zz_17_; + wire [0:0] _zz_18_; + wire [0:0] _zz_19_; + wire [0:0] _zz_20_; + wire [2:0] _zz_21_; + wire [1:0] _zz_22_; + wire [21:0] _zz_23_; + reg _zz_1_; + reg _zz_2_; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3_; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4_; + wire _zz_5_; + wire [31:0] ways_0_dataReadRsp; + reg [3:0] _zz_6_; + wire [3:0] stage0_mask; + wire [0:0] stage0_colisions; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg [3:0] stageA_mask; + wire stageA_wayHits_0; + reg [0:0] stage0_colisions_regNextWhen; + wire [0:0] _zz_7_; + wire [0:0] stageA_colisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + wire [0:0] _zz_8_; + reg [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg [0:0] stageB_colisions; + reg stageB_loaderValid; + reg stageB_flusher_valid; + wire [31:0] stageB_requestDataBypass; + wire stageB_isAmo; + reg stageB_memCmdSent; + wire [0:0] _zz_9_; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_24_; + reg [7:0] _zz_25_; + reg [7:0] _zz_26_; + reg [7:0] _zz_27_; + assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); + assign _zz_15_ = (loader_valid && io_mem_rsp_valid); + assign _zz_16_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + assign _zz_17_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign _zz_18_ = _zz_4_[0 : 0]; + assign _zz_19_ = _zz_4_[1 : 1]; + assign _zz_20_ = loader_counter_willIncrement; + assign _zz_21_ = {2'd0, _zz_20_}; + assign _zz_22_ = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_23_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_23_; + end + end + + always @ (posedge clk) begin + if(_zz_3_) begin + _zz_10_ <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (*) begin + _zz_11_ = {_zz_27_, _zz_26_, _zz_25_, _zz_24_}; + end + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1_) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1_) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1_) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1_) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (posedge clk) begin + if(_zz_5_) begin + _zz_24_ <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_25_ <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_26_ <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_27_ <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2_ = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4_ = _zz_10_; + assign ways_0_tagsReadRsp_valid = _zz_18_[0]; + assign ways_0_tagsReadRsp_error = _zz_19_[0]; + assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2]; + assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRsp = _zz_11_; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12_)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = (7'bxxxxxxx); + if(_zz_12_)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12_)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = (10'bxxxxxxxxxx); + if(_zz_12_)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13_)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = (1'bx); + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = (1'b1); + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = (7'bxxxxxxx); + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx); + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + end + end + if(_zz_13_)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_15_)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = (1'bx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = (10'bxxxxxxxxxx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_data = stageB_requestDataBypass; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = (4'bxxxx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_mask = stageB_mask; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_mask = (4'b1111); + end + end + + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6_ = (4'b0001); + end + 2'b01 : begin + _zz_6_ = (4'b0011); + end + default : begin + _zz_6_ = (4'b1111); + end + endcase + end + + assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]); + assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); + assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; + assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; + assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); + assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign _zz_8_[0] = stageA_wayHits_0; + assign stageB_waysHit = (stageB_waysHits != (1'b0)); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(! _zz_14_) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + if(_zz_13_)begin + stageB_loaderValid = 1'b0; + end + end + + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_14_)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + if(_zz_13_)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(_zz_16_)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_requestDataBypass = stageB_request_data; + assign stageB_isAmo = 1'b0; + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + if((((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))))begin + io_cpu_redo = 1'b1; + end + end + end + end + if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin + io_cpu_redo = 1'b1; + end + if(loader_valid)begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_mmuRsp_isIoAccess)begin + io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); + end + end + + assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_valid = (! stageB_memCmdSent); + end else begin + if(_zz_14_)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! stageB_memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + if(_zz_13_)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)}; + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = (3'bxxx); + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_length = (3'b000); + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_length = (3'b000); + end else begin + io_mem_cmd_payload_length = (3'b111); + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_last = 1'bx; + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_last = 1'b1; + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_last = 1'b1; + end else begin + io_mem_cmd_payload_last = 1'b1; + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(! _zz_14_) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + always @ (*) begin + if(stageB_mmuRsp_isIoAccess)begin + io_cpu_writeBack_data = io_mem_rsp_payload_data; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9_[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_15_)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_21_); + if(loader_counter_willClear)begin + loader_counter_valueNext = (3'b000); + end + end + + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stage0_colisions_regNextWhen <= stage0_colisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + end + if(_zz_17_)begin + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHits <= _zz_8_; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_colisions <= stageA_colisions; + end + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("ERROR writeBack stuck by another plugin is not allowed"); + end + end + + always @ (posedge clk) begin + if(reset) begin + stageB_flusher_valid <= 1'b1; + stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000); + stageB_memCmdSent <= 1'b0; + loader_valid <= 1'b0; + loader_counter_value <= (3'b000); + loader_waysAllocator <= (1'b1); + loader_error <= 1'b0; + end else begin + if(_zz_17_)begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; + end + if(stageB_flusher_valid)begin + if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001)); + end else begin + stageB_flusher_valid <= 1'b0; + end + end + if(_zz_16_)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000); + stageB_flusher_valid <= 1'b1; + end + if(io_mem_cmd_ready)begin + stageB_memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_memCmdSent <= 1'b0; + end + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(_zz_15_)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_counter_willOverflow)begin + loader_valid <= 1'b0; + loader_waysAllocator <= _zz_22_[0:0]; + loader_error <= 1'b0; + end + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset); + wire _zz_221_; + wire _zz_222_; + wire _zz_223_; + wire _zz_224_; + wire _zz_225_; + wire [31:0] _zz_226_; + wire _zz_227_; + wire _zz_228_; + wire _zz_229_; + reg _zz_230_; + wire _zz_231_; + wire [31:0] _zz_232_; + wire _zz_233_; + wire [31:0] _zz_234_; + reg _zz_235_; + wire _zz_236_; + wire _zz_237_; + wire [31:0] _zz_238_; + wire _zz_239_; + wire _zz_240_; + reg [31:0] _zz_241_; + reg [31:0] _zz_242_; + reg [31:0] _zz_243_; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1__io_cpu_memory_isWrite; + wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; + wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + wire dataCache_1__io_cpu_memory_mmuBus_end; + wire dataCache_1__io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1__io_cpu_writeBack_data; + wire dataCache_1__io_cpu_writeBack_mmuException; + wire dataCache_1__io_cpu_writeBack_unalignedAccess; + wire dataCache_1__io_cpu_writeBack_accessError; + wire dataCache_1__io_cpu_writeBack_isWrite; + wire dataCache_1__io_cpu_flush_ready; + wire dataCache_1__io_cpu_redo; + wire dataCache_1__io_mem_cmd_valid; + wire dataCache_1__io_mem_cmd_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_payload_length; + wire dataCache_1__io_mem_cmd_payload_last; + wire _zz_244_; + wire _zz_245_; + wire _zz_246_; + wire _zz_247_; + wire _zz_248_; + wire _zz_249_; + wire _zz_250_; + wire _zz_251_; + wire _zz_252_; + wire _zz_253_; + wire _zz_254_; + wire _zz_255_; + wire _zz_256_; + wire _zz_257_; + wire [1:0] _zz_258_; + wire _zz_259_; + wire _zz_260_; + wire _zz_261_; + wire _zz_262_; + wire _zz_263_; + wire _zz_264_; + wire _zz_265_; + wire _zz_266_; + wire [1:0] _zz_267_; + wire _zz_268_; + wire _zz_269_; + wire _zz_270_; + wire _zz_271_; + wire _zz_272_; + wire _zz_273_; + wire _zz_274_; + wire [1:0] _zz_275_; + wire _zz_276_; + wire [1:0] _zz_277_; + wire [4:0] _zz_278_; + wire [2:0] _zz_279_; + wire [31:0] _zz_280_; + wire [11:0] _zz_281_; + wire [31:0] _zz_282_; + wire [19:0] _zz_283_; + wire [11:0] _zz_284_; + wire [31:0] _zz_285_; + wire [31:0] _zz_286_; + wire [19:0] _zz_287_; + wire [11:0] _zz_288_; + wire [2:0] _zz_289_; + wire [2:0] _zz_290_; + wire [0:0] _zz_291_; + wire [0:0] _zz_292_; + wire [0:0] _zz_293_; + wire [0:0] _zz_294_; + wire [0:0] _zz_295_; + wire [0:0] _zz_296_; + wire [0:0] _zz_297_; + wire [0:0] _zz_298_; + wire [0:0] _zz_299_; + wire [0:0] _zz_300_; + wire [0:0] _zz_301_; + wire [0:0] _zz_302_; + wire [0:0] _zz_303_; + wire [0:0] _zz_304_; + wire [0:0] _zz_305_; + wire [0:0] _zz_306_; + wire [0:0] _zz_307_; + wire [0:0] _zz_308_; + wire [2:0] _zz_309_; + wire [4:0] _zz_310_; + wire [11:0] _zz_311_; + wire [11:0] _zz_312_; + wire [31:0] _zz_313_; + wire [31:0] _zz_314_; + wire [31:0] _zz_315_; + wire [31:0] _zz_316_; + wire [31:0] _zz_317_; + wire [31:0] _zz_318_; + wire [31:0] _zz_319_; + wire [32:0] _zz_320_; + wire [31:0] _zz_321_; + wire [32:0] _zz_322_; + wire [11:0] _zz_323_; + wire [19:0] _zz_324_; + wire [11:0] _zz_325_; + wire [31:0] _zz_326_; + wire [31:0] _zz_327_; + wire [31:0] _zz_328_; + wire [11:0] _zz_329_; + wire [19:0] _zz_330_; + wire [11:0] _zz_331_; + wire [2:0] _zz_332_; + wire [1:0] _zz_333_; + wire [1:0] _zz_334_; + wire [51:0] _zz_335_; + wire [51:0] _zz_336_; + wire [51:0] _zz_337_; + wire [32:0] _zz_338_; + wire [51:0] _zz_339_; + wire [49:0] _zz_340_; + wire [51:0] _zz_341_; + wire [49:0] _zz_342_; + wire [51:0] _zz_343_; + wire [65:0] _zz_344_; + wire [65:0] _zz_345_; + wire [31:0] _zz_346_; + wire [31:0] _zz_347_; + wire [0:0] _zz_348_; + wire [5:0] _zz_349_; + wire [32:0] _zz_350_; + wire [32:0] _zz_351_; + wire [31:0] _zz_352_; + wire [31:0] _zz_353_; + wire [32:0] _zz_354_; + wire [32:0] _zz_355_; + wire [32:0] _zz_356_; + wire [0:0] _zz_357_; + wire [32:0] _zz_358_; + wire [0:0] _zz_359_; + wire [32:0] _zz_360_; + wire [0:0] _zz_361_; + wire [31:0] _zz_362_; + wire [0:0] _zz_363_; + wire [0:0] _zz_364_; + wire [0:0] _zz_365_; + wire [0:0] _zz_366_; + wire [0:0] _zz_367_; + wire [0:0] _zz_368_; + wire [26:0] _zz_369_; + wire _zz_370_; + wire _zz_371_; + wire [2:0] _zz_372_; + wire _zz_373_; + wire _zz_374_; + wire _zz_375_; + wire [31:0] _zz_376_; + wire [31:0] _zz_377_; + wire _zz_378_; + wire [0:0] _zz_379_; + wire [0:0] _zz_380_; + wire [31:0] _zz_381_; + wire [31:0] _zz_382_; + wire [0:0] _zz_383_; + wire [1:0] _zz_384_; + wire [0:0] _zz_385_; + wire [0:0] _zz_386_; + wire _zz_387_; + wire [0:0] _zz_388_; + wire [24:0] _zz_389_; + wire [31:0] _zz_390_; + wire [31:0] _zz_391_; + wire [31:0] _zz_392_; + wire [31:0] _zz_393_; + wire [31:0] _zz_394_; + wire [31:0] _zz_395_; + wire [31:0] _zz_396_; + wire _zz_397_; + wire _zz_398_; + wire [31:0] _zz_399_; + wire [31:0] _zz_400_; + wire [0:0] _zz_401_; + wire [0:0] _zz_402_; + wire [0:0] _zz_403_; + wire [0:0] _zz_404_; + wire _zz_405_; + wire [0:0] _zz_406_; + wire [22:0] _zz_407_; + wire [31:0] _zz_408_; + wire [31:0] _zz_409_; + wire [0:0] _zz_410_; + wire [3:0] _zz_411_; + wire [0:0] _zz_412_; + wire [0:0] _zz_413_; + wire [1:0] _zz_414_; + wire [1:0] _zz_415_; + wire _zz_416_; + wire [0:0] _zz_417_; + wire [19:0] _zz_418_; + wire [31:0] _zz_419_; + wire [31:0] _zz_420_; + wire [31:0] _zz_421_; + wire _zz_422_; + wire [0:0] _zz_423_; + wire [0:0] _zz_424_; + wire [31:0] _zz_425_; + wire [31:0] _zz_426_; + wire [31:0] _zz_427_; + wire [31:0] _zz_428_; + wire [31:0] _zz_429_; + wire [31:0] _zz_430_; + wire _zz_431_; + wire _zz_432_; + wire [0:0] _zz_433_; + wire [0:0] _zz_434_; + wire [2:0] _zz_435_; + wire [2:0] _zz_436_; + wire _zz_437_; + wire [0:0] _zz_438_; + wire [16:0] _zz_439_; + wire [31:0] _zz_440_; + wire [31:0] _zz_441_; + wire [31:0] _zz_442_; + wire [31:0] _zz_443_; + wire [31:0] _zz_444_; + wire [31:0] _zz_445_; + wire [31:0] _zz_446_; + wire [31:0] _zz_447_; + wire [31:0] _zz_448_; + wire [31:0] _zz_449_; + wire [31:0] _zz_450_; + wire _zz_451_; + wire [0:0] _zz_452_; + wire [0:0] _zz_453_; + wire [0:0] _zz_454_; + wire [0:0] _zz_455_; + wire [1:0] _zz_456_; + wire [1:0] _zz_457_; + wire _zz_458_; + wire [0:0] _zz_459_; + wire [14:0] _zz_460_; + wire [31:0] _zz_461_; + wire [31:0] _zz_462_; + wire [31:0] _zz_463_; + wire [31:0] _zz_464_; + wire [31:0] _zz_465_; + wire [31:0] _zz_466_; + wire [31:0] _zz_467_; + wire _zz_468_; + wire [0:0] _zz_469_; + wire [0:0] _zz_470_; + wire _zz_471_; + wire [0:0] _zz_472_; + wire [12:0] _zz_473_; + wire _zz_474_; + wire [0:0] _zz_475_; + wire [1:0] _zz_476_; + wire [31:0] _zz_477_; + wire [31:0] _zz_478_; + wire _zz_479_; + wire [0:0] _zz_480_; + wire [0:0] _zz_481_; + wire _zz_482_; + wire [0:0] _zz_483_; + wire [8:0] _zz_484_; + wire [31:0] _zz_485_; + wire [31:0] _zz_486_; + wire [31:0] _zz_487_; + wire [31:0] _zz_488_; + wire [31:0] _zz_489_; + wire [31:0] _zz_490_; + wire [31:0] _zz_491_; + wire [31:0] _zz_492_; + wire _zz_493_; + wire [0:0] _zz_494_; + wire [0:0] _zz_495_; + wire _zz_496_; + wire [0:0] _zz_497_; + wire [5:0] _zz_498_; + wire [31:0] _zz_499_; + wire [31:0] _zz_500_; + wire _zz_501_; + wire [0:0] _zz_502_; + wire [3:0] _zz_503_; + wire [0:0] _zz_504_; + wire [0:0] _zz_505_; + wire _zz_506_; + wire [0:0] _zz_507_; + wire [1:0] _zz_508_; + wire [31:0] _zz_509_; + wire _zz_510_; + wire [0:0] _zz_511_; + wire [0:0] _zz_512_; + wire [31:0] _zz_513_; + wire _zz_514_; + wire [0:0] _zz_515_; + wire [0:0] _zz_516_; + wire _zz_517_; + wire [0:0] _zz_518_; + wire [0:0] _zz_519_; + wire [0:0] _zz_520_; + wire [0:0] _zz_521_; + wire [31:0] _zz_522_; + wire [31:0] _zz_523_; + wire [31:0] _zz_524_; + wire [31:0] _zz_525_; + wire [31:0] _zz_526_; + wire [31:0] _zz_527_; + wire [31:0] _zz_528_; + wire [31:0] _zz_529_; + wire [31:0] _zz_530_; + wire _zz_531_; + wire [0:0] _zz_532_; + wire [11:0] _zz_533_; + wire [31:0] _zz_534_; + wire [31:0] _zz_535_; + wire [31:0] _zz_536_; + wire _zz_537_; + wire [0:0] _zz_538_; + wire [5:0] _zz_539_; + wire [31:0] _zz_540_; + wire [31:0] _zz_541_; + wire [31:0] _zz_542_; + wire _zz_543_; + wire _zz_544_; + wire _zz_545_; + wire _zz_546_; + wire _zz_547_; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_1_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_2_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_3_; + wire decode_MEMORY_MANAGMENT; + wire decode_CSR_READ_OPCODE; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_4_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_5_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_6_; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC2_FORCE_ZERO; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10_; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_11_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_12_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_13_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_14_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_15_; + wire decode_IS_DIV; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_16_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_17_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18_; + wire decode_IS_RS1_SIGNED; + wire decode_SRC_LESS_UNSIGNED; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_IS_RS2_SIGNED; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [51:0] memory_MUL_LOW; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_19_; + wire `AluCtrlEnum_defaultEncoding_type _zz_20_; + wire `AluCtrlEnum_defaultEncoding_type _zz_21_; + wire [31:0] execute_BRANCH_CALC; + wire [31:0] execute_MUL_LL; + wire decode_IS_CSR; + wire [31:0] memory_PC; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_24_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_25_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_26_; + wire [33:0] execute_MUL_LH; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire [51:0] _zz_27_; + wire [33:0] _zz_28_; + wire [33:0] _zz_29_; + wire [33:0] _zz_30_; + wire [31:0] _zz_31_; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_32_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33_; + wire _zz_34_; + wire _zz_35_; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_36_; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] _zz_37_; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + wire _zz_38_; + wire [31:0] execute_RS1; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_39_; + wire _zz_40_; + wire _zz_41_; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_42_; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_43_; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_44_; + wire [31:0] _zz_45_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_46_; + wire _zz_47_; + wire [31:0] _zz_48_; + wire [31:0] _zz_49_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_50_; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_51_; + wire [31:0] _zz_52_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_53_; + wire [31:0] _zz_54_; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire _zz_55_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_56_; + wire [31:0] _zz_57_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_; + wire [31:0] _zz_59_; + wire _zz_60_; + reg _zz_61_; + wire [31:0] _zz_62_; + wire [31:0] _zz_63_; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire decode_INSTRUCTION_READY; + wire _zz_64_; + wire _zz_65_; + wire _zz_66_; + wire _zz_67_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_68_; + wire _zz_69_; + wire _zz_70_; + wire _zz_71_; + wire _zz_72_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_73_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_74_; + wire _zz_75_; + wire _zz_76_; + wire _zz_77_; + wire _zz_78_; + wire _zz_79_; + wire _zz_80_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_81_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_82_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_83_; + wire _zz_84_; + wire _zz_85_; + wire _zz_86_; + wire `AluCtrlEnum_defaultEncoding_type _zz_87_; + wire _zz_88_; + reg [31:0] _zz_89_; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire [1:0] _zz_90_; + wire execute_MEMORY_MANAGMENT; + wire [31:0] execute_RS2; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected; + reg _zz_91_; + reg _zz_92_; + reg _zz_93_; + wire [31:0] _zz_94_; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_95_; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_96_; + reg [31:0] _zz_97_; + wire [31:0] decode_PC; + wire [31:0] _zz_98_; + wire [31:0] _zz_99_; + wire [31:0] _zz_100_; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushAll; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushAll; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushAll; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushAll; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + wire IBusCachedPlugin_fetcherflushIt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_pcs_4 /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + wire IBusCachedPlugin_redoBranch_valid; + wire [31:0] IBusCachedPlugin_redoBranch_payload; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_isValid; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [4:0] _zz_101_; + wire [4:0] _zz_102_; + wire _zz_103_; + wire _zz_104_; + wire _zz_105_; + wire _zz_106_; + wire IBusCachedPlugin_fetchPc_preOutput_valid; + wire IBusCachedPlugin_fetchPc_preOutput_ready; + wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload; + wire _zz_107_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_inc; + reg IBusCachedPlugin_fetchPc_propagatePc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + reg IBusCachedPlugin_fetchPc_samplePcNext; + reg _zz_108_; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; + wire _zz_109_; + wire _zz_110_; + wire _zz_111_; + wire _zz_112_; + wire _zz_113_; + reg _zz_114_; + wire _zz_115_; + reg _zz_116_; + reg [31:0] _zz_117_; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_decodeInput_valid; + wire IBusCachedPlugin_iBusRsp_decodeInput_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + reg IBusCachedPlugin_injector_decodeRemoved; + wire _zz_118_; + reg [18:0] _zz_119_; + wire _zz_120_; + reg [10:0] _zz_121_; + wire _zz_122_; + reg [18:0] _zz_123_; + reg _zz_124_; + wire _zz_125_; + reg [10:0] _zz_126_; + wire _zz_127_; + reg [18:0] _zz_128_; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire dataCache_1__io_mem_cmd_s2mPipe_valid; + wire dataCache_1__io_mem_cmd_s2mPipe_ready; + wire dataCache_1__io_mem_cmd_s2mPipe_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1__io_mem_cmd_s2mPipe_payload_last; + reg _zz_129_; + reg _zz_130_; + reg [31:0] _zz_131_; + reg [31:0] _zz_132_; + reg [3:0] _zz_133_; + reg [2:0] _zz_134_; + reg _zz_135_; + wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg _zz_136_; + reg _zz_137_; + reg [31:0] _zz_138_; + reg [31:0] _zz_139_; + reg [3:0] _zz_140_; + reg [2:0] _zz_141_; + reg _zz_142_; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_143_; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_144_; + reg [31:0] _zz_145_; + wire _zz_146_; + reg [31:0] _zz_147_; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [30:0] _zz_148_; + wire _zz_149_; + wire _zz_150_; + wire _zz_151_; + wire _zz_152_; + wire `AluCtrlEnum_defaultEncoding_type _zz_153_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_154_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_155_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_156_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_157_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_158_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_159_; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_160_; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_161_; + reg [31:0] _zz_162_; + wire _zz_163_; + reg [19:0] _zz_164_; + wire _zz_165_; + reg [19:0] _zz_166_; + reg [31:0] _zz_167_; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_168_; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_169_; + reg _zz_170_; + reg _zz_171_; + wire _zz_172_; + reg _zz_173_; + reg [4:0] _zz_174_; + reg [31:0] _zz_175_; + wire _zz_176_; + wire _zz_177_; + wire _zz_178_; + wire _zz_179_; + wire _zz_180_; + wire _zz_181_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_182_; + reg _zz_183_; + reg _zz_184_; + wire _zz_185_; + reg [19:0] _zz_186_; + wire _zz_187_; + reg [10:0] _zz_188_; + wire _zz_189_; + reg [18:0] _zz_190_; + reg _zz_191_; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_192_; + reg [19:0] _zz_193_; + wire _zz_194_; + reg [10:0] _zz_195_; + wire _zz_196_; + reg [18:0] _zz_197_; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_198_; + wire _zz_199_; + wire _zz_200_; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_201_; + wire _zz_202_; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire execute_CsrPlugin_inWfi /* verilator public */ ; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_203_; + wire [32:0] _zz_204_; + wire [32:0] _zz_205_; + wire [31:0] _zz_206_; + wire _zz_207_; + wire _zz_208_; + reg [32:0] _zz_209_; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_210_; + wire [31:0] _zz_211_; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg [33:0] execute_to_memory_MUL_LH; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg decode_to_execute_IS_CSR; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg [31:0] execute_to_memory_MUL_LL; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_IS_RS1_SIGNED; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg [31:0] decode_to_execute_RS1; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg execute_to_memory_BRANCH_DO; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_MANAGMENT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg [2:0] _zz_212_; + reg _zz_213_; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_214_; + wire _zz_215_; + wire _zz_216_; + wire _zz_217_; + wire _zz_218_; + wire _zz_219_; + reg _zz_220_; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_1__string; + reg [95:0] _zz_2__string; + reg [95:0] _zz_3__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_4__string; + reg [39:0] _zz_5__string; + reg [39:0] _zz_6__string; + reg [31:0] _zz_7__string; + reg [31:0] _zz_8__string; + reg [31:0] _zz_9__string; + reg [31:0] _zz_10__string; + reg [31:0] decode_ENV_CTRL_string; + reg [31:0] _zz_11__string; + reg [31:0] _zz_12__string; + reg [31:0] _zz_13__string; + reg [31:0] _zz_14__string; + reg [31:0] _zz_15__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_16__string; + reg [23:0] _zz_17__string; + reg [23:0] _zz_18__string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_19__string; + reg [63:0] _zz_20__string; + reg [63:0] _zz_21__string; + reg [71:0] _zz_22__string; + reg [71:0] _zz_23__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_24__string; + reg [71:0] _zz_25__string; + reg [71:0] _zz_26__string; + reg [31:0] memory_ENV_CTRL_string; + reg [31:0] _zz_32__string; + reg [31:0] execute_ENV_CTRL_string; + reg [31:0] _zz_33__string; + reg [31:0] writeBack_ENV_CTRL_string; + reg [31:0] _zz_36__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_39__string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_44__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_46__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_51__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_53__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_56__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_58__string; + reg [31:0] _zz_68__string; + reg [71:0] _zz_73__string; + reg [23:0] _zz_74__string; + reg [39:0] _zz_81__string; + reg [31:0] _zz_82__string; + reg [95:0] _zz_83__string; + reg [63:0] _zz_87__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_95__string; + reg [63:0] _zz_153__string; + reg [95:0] _zz_154__string; + reg [31:0] _zz_155__string; + reg [39:0] _zz_156__string; + reg [23:0] _zz_157__string; + reg [71:0] _zz_158__string; + reg [31:0] _zz_159__string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [31:0] decode_to_execute_ENV_CTRL_string; + reg [31:0] execute_to_memory_ENV_CTRL_string; + reg [31:0] memory_to_writeBack_ENV_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_244_ = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_245_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_246_ = 1'b1; + assign _zz_247_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_248_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_249_ = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_250_ = ((_zz_227_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_91_)); + assign _zz_251_ = ((_zz_227_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_92_)); + assign _zz_252_ = ((_zz_227_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_93_)); + assign _zz_253_ = ((_zz_227_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); + assign _zz_254_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); + assign _zz_255_ = (! memory_DivPlugin_div_done); + assign _zz_256_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_257_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_258_ = writeBack_INSTRUCTION[29 : 28]; + assign _zz_259_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready); + assign _zz_260_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_261_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_262_ = (1'b0 || (! 1'b1)); + assign _zz_263_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_264_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_265_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_266_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_267_ = execute_INSTRUCTION[13 : 12]; + assign _zz_268_ = (! memory_arbitration_isStuck); + assign _zz_269_ = (iBus_cmd_valid || (_zz_212_ != (3'b000))); + assign _zz_270_ = (_zz_240_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready)); + assign _zz_271_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); + assign _zz_272_ = ((_zz_198_ && 1'b1) && (! 1'b0)); + assign _zz_273_ = ((_zz_199_ && 1'b1) && (! 1'b0)); + assign _zz_274_ = ((_zz_200_ && 1'b1) && (! 1'b0)); + assign _zz_275_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_276_ = execute_INSTRUCTION[13]; + assign _zz_277_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_278_ = (_zz_101_ - (5'b00001)); + assign _zz_279_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_280_ = {29'd0, _zz_279_}; + assign _zz_281_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_282_ = {{_zz_119_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_283_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_284_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_285_ = {{_zz_121_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_286_ = {{_zz_123_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_287_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_288_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_289_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); + assign _zz_290_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); + assign _zz_291_ = _zz_148_[2 : 2]; + assign _zz_292_ = _zz_148_[4 : 4]; + assign _zz_293_ = _zz_148_[5 : 5]; + assign _zz_294_ = _zz_148_[11 : 11]; + assign _zz_295_ = _zz_148_[12 : 12]; + assign _zz_296_ = _zz_148_[13 : 13]; + assign _zz_297_ = _zz_148_[14 : 14]; + assign _zz_298_ = _zz_148_[15 : 15]; + assign _zz_299_ = _zz_148_[16 : 16]; + assign _zz_300_ = _zz_148_[21 : 21]; + assign _zz_301_ = _zz_148_[22 : 22]; + assign _zz_302_ = _zz_148_[23 : 23]; + assign _zz_303_ = _zz_148_[24 : 24]; + assign _zz_304_ = _zz_148_[27 : 27]; + assign _zz_305_ = _zz_148_[28 : 28]; + assign _zz_306_ = _zz_148_[29 : 29]; + assign _zz_307_ = _zz_148_[30 : 30]; + assign _zz_308_ = execute_SRC_LESS; + assign _zz_309_ = (3'b100); + assign _zz_310_ = execute_INSTRUCTION[19 : 15]; + assign _zz_311_ = execute_INSTRUCTION[31 : 20]; + assign _zz_312_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_313_ = ($signed(_zz_314_) + $signed(_zz_317_)); + assign _zz_314_ = ($signed(_zz_315_) + $signed(_zz_316_)); + assign _zz_315_ = execute_SRC1; + assign _zz_316_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_317_ = (execute_SRC_USE_SUB_LESS ? _zz_318_ : _zz_319_); + assign _zz_318_ = (32'b00000000000000000000000000000001); + assign _zz_319_ = (32'b00000000000000000000000000000000); + assign _zz_320_ = ($signed(_zz_322_) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_321_ = _zz_320_[31 : 0]; + assign _zz_322_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_323_ = execute_INSTRUCTION[31 : 20]; + assign _zz_324_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_325_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_326_ = {_zz_186_,execute_INSTRUCTION[31 : 20]}; + assign _zz_327_ = {{_zz_188_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_328_ = {{_zz_190_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_329_ = execute_INSTRUCTION[31 : 20]; + assign _zz_330_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_331_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_332_ = (3'b100); + assign _zz_333_ = (_zz_201_ & (~ _zz_334_)); + assign _zz_334_ = (_zz_201_ - (2'b01)); + assign _zz_335_ = ($signed(_zz_336_) + $signed(_zz_341_)); + assign _zz_336_ = ($signed(_zz_337_) + $signed(_zz_339_)); + assign _zz_337_ = (52'b0000000000000000000000000000000000000000000000000000); + assign _zz_338_ = {1'b0,memory_MUL_LL}; + assign _zz_339_ = {{19{_zz_338_[32]}}, _zz_338_}; + assign _zz_340_ = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_341_ = {{2{_zz_340_[49]}}, _zz_340_}; + assign _zz_342_ = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_343_ = {{2{_zz_342_[49]}}, _zz_342_}; + assign _zz_344_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_345_ = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_346_ = writeBack_MUL_LOW[31 : 0]; + assign _zz_347_ = writeBack_MulPlugin_result[63 : 32]; + assign _zz_348_ = memory_DivPlugin_div_counter_willIncrement; + assign _zz_349_ = {5'd0, _zz_348_}; + assign _zz_350_ = {1'd0, memory_DivPlugin_rs2}; + assign _zz_351_ = {_zz_203_,(! _zz_205_[32])}; + assign _zz_352_ = _zz_205_[31:0]; + assign _zz_353_ = _zz_204_[31:0]; + assign _zz_354_ = _zz_355_; + assign _zz_355_ = _zz_356_; + assign _zz_356_ = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_206_) : _zz_206_)} + _zz_358_); + assign _zz_357_ = memory_DivPlugin_div_needRevert; + assign _zz_358_ = {32'd0, _zz_357_}; + assign _zz_359_ = _zz_208_; + assign _zz_360_ = {32'd0, _zz_359_}; + assign _zz_361_ = _zz_207_; + assign _zz_362_ = {31'd0, _zz_361_}; + assign _zz_363_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_364_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_365_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_366_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_367_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_368_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_369_ = (iBus_cmd_payload_address >>> 5); + assign _zz_370_ = 1'b1; + assign _zz_371_ = 1'b1; + assign _zz_372_ = {_zz_104_,{_zz_106_,_zz_105_}}; + assign _zz_373_ = decode_INSTRUCTION[31]; + assign _zz_374_ = decode_INSTRUCTION[31]; + assign _zz_375_ = decode_INSTRUCTION[7]; + assign _zz_376_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_377_ = (32'b00000000000000000000000000000000); + assign _zz_378_ = ((decode_INSTRUCTION & _zz_390_) == (32'b00000000000000000000000000000000)); + assign _zz_379_ = (_zz_391_ == _zz_392_); + assign _zz_380_ = (_zz_393_ == _zz_394_); + assign _zz_381_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_382_ = (32'b00000000000000000000000000000000); + assign _zz_383_ = (_zz_395_ == _zz_396_); + assign _zz_384_ = {_zz_397_,_zz_398_}; + assign _zz_385_ = (_zz_399_ == _zz_400_); + assign _zz_386_ = (1'b0); + assign _zz_387_ = ({_zz_401_,_zz_402_} != (2'b00)); + assign _zz_388_ = (_zz_403_ != _zz_404_); + assign _zz_389_ = {_zz_405_,{_zz_406_,_zz_407_}}; + assign _zz_390_ = (32'b00000000000000000000000000011000); + assign _zz_391_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); + assign _zz_392_ = (32'b00000000000000000010000000000000); + assign _zz_393_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); + assign _zz_394_ = (32'b00000000000000000001000000000000); + assign _zz_395_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_396_ = (32'b00000000000000000000000001000000); + assign _zz_397_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010100)) == (32'b00000000000000000010000000010000)); + assign _zz_398_ = ((decode_INSTRUCTION & (32'b01000000000000000000000000110100)) == (32'b01000000000000000000000000110000)); + assign _zz_399_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_400_ = (32'b00000000000000000000000000100100); + assign _zz_401_ = _zz_152_; + assign _zz_402_ = ((decode_INSTRUCTION & _zz_408_) == (32'b00000000000000000000000000000100)); + assign _zz_403_ = ((decode_INSTRUCTION & _zz_409_) == (32'b00000000000000000000000001000000)); + assign _zz_404_ = (1'b0); + assign _zz_405_ = ({_zz_152_,{_zz_410_,_zz_411_}} != (6'b000000)); + assign _zz_406_ = ({_zz_412_,_zz_413_} != (2'b00)); + assign _zz_407_ = {(_zz_414_ != _zz_415_),{_zz_416_,{_zz_417_,_zz_418_}}}; + assign _zz_408_ = (32'b00000000000000000000000000011100); + assign _zz_409_ = (32'b00000000000000000000000001011000); + assign _zz_410_ = ((decode_INSTRUCTION & _zz_419_) == (32'b00000000000000000001000000010000)); + assign _zz_411_ = {(_zz_420_ == _zz_421_),{_zz_422_,{_zz_423_,_zz_424_}}}; + assign _zz_412_ = ((decode_INSTRUCTION & _zz_425_) == (32'b00000000000000000010000000000000)); + assign _zz_413_ = ((decode_INSTRUCTION & _zz_426_) == (32'b00000000000000000001000000000000)); + assign _zz_414_ = {(_zz_427_ == _zz_428_),(_zz_429_ == _zz_430_)}; + assign _zz_415_ = (2'b00); + assign _zz_416_ = ({_zz_431_,_zz_432_} != (2'b00)); + assign _zz_417_ = ({_zz_433_,_zz_434_} != (2'b00)); + assign _zz_418_ = {(_zz_435_ != _zz_436_),{_zz_437_,{_zz_438_,_zz_439_}}}; + assign _zz_419_ = (32'b00000000000000000001000000010000); + assign _zz_420_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); + assign _zz_421_ = (32'b00000000000000000010000000010000); + assign _zz_422_ = ((decode_INSTRUCTION & _zz_440_) == (32'b00000000000000000000000000010000)); + assign _zz_423_ = (_zz_441_ == _zz_442_); + assign _zz_424_ = (_zz_443_ == _zz_444_); + assign _zz_425_ = (32'b00000000000000000010000000010000); + assign _zz_426_ = (32'b00000000000000000101000000000000); + assign _zz_427_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); + assign _zz_428_ = (32'b00000000000000000000000000100000); + assign _zz_429_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_430_ = (32'b00000000000000000000000000100000); + assign _zz_431_ = ((decode_INSTRUCTION & _zz_445_) == (32'b00000000000000000001000001010000)); + assign _zz_432_ = ((decode_INSTRUCTION & _zz_446_) == (32'b00000000000000000010000001010000)); + assign _zz_433_ = (_zz_447_ == _zz_448_); + assign _zz_434_ = (_zz_449_ == _zz_450_); + assign _zz_435_ = {_zz_451_,{_zz_452_,_zz_453_}}; + assign _zz_436_ = (3'b000); + assign _zz_437_ = ({_zz_454_,_zz_455_} != (2'b00)); + assign _zz_438_ = (_zz_456_ != _zz_457_); + assign _zz_439_ = {_zz_458_,{_zz_459_,_zz_460_}}; + assign _zz_440_ = (32'b00000000000000000000000001010000); + assign _zz_441_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100)); + assign _zz_442_ = (32'b00000000000000000000000000000100); + assign _zz_443_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); + assign _zz_444_ = (32'b00000000000000000000000000000000); + assign _zz_445_ = (32'b00000000000000000001000001010000); + assign _zz_446_ = (32'b00000000000000000010000001010000); + assign _zz_447_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); + assign _zz_448_ = (32'b00000000000000000101000000010000); + assign _zz_449_ = (decode_INSTRUCTION & (32'b00000010000000000111000001100100)); + assign _zz_450_ = (32'b00000000000000000101000000100000); + assign _zz_451_ = ((decode_INSTRUCTION & _zz_461_) == (32'b01000000000000000001000000010000)); + assign _zz_452_ = (_zz_462_ == _zz_463_); + assign _zz_453_ = (_zz_464_ == _zz_465_); + assign _zz_454_ = _zz_149_; + assign _zz_455_ = (_zz_466_ == _zz_467_); + assign _zz_456_ = {_zz_149_,_zz_468_}; + assign _zz_457_ = (2'b00); + assign _zz_458_ = (_zz_151_ != (1'b0)); + assign _zz_459_ = (_zz_469_ != _zz_470_); + assign _zz_460_ = {_zz_471_,{_zz_472_,_zz_473_}}; + assign _zz_461_ = (32'b01000000000000000011000001010100); + assign _zz_462_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); + assign _zz_463_ = (32'b00000000000000000001000000010000); + assign _zz_464_ = (decode_INSTRUCTION & (32'b00000010000000000111000001010100)); + assign _zz_465_ = (32'b00000000000000000001000000010000); + assign _zz_466_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); + assign _zz_467_ = (32'b00000000000000000000000000100000); + assign _zz_468_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); + assign _zz_469_ = _zz_151_; + assign _zz_470_ = (1'b0); + assign _zz_471_ = ({_zz_149_,{_zz_474_,{_zz_475_,_zz_476_}}} != (5'b00000)); + assign _zz_472_ = ((_zz_477_ == _zz_478_) != (1'b0)); + assign _zz_473_ = {(_zz_479_ != (1'b0)),{(_zz_480_ != _zz_481_),{_zz_482_,{_zz_483_,_zz_484_}}}}; + assign _zz_474_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000110000)) == (32'b00000000000000000010000000010000)); + assign _zz_475_ = ((decode_INSTRUCTION & _zz_485_) == (32'b00000000000000000000000000010000)); + assign _zz_476_ = {(_zz_486_ == _zz_487_),(_zz_488_ == _zz_489_)}; + assign _zz_477_ = (decode_INSTRUCTION & (32'b00000000000000000100000001001000)); + assign _zz_478_ = (32'b00000000000000000100000000001000); + assign _zz_479_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000)); + assign _zz_480_ = ((decode_INSTRUCTION & _zz_490_) == (32'b00000010000000000000000000110000)); + assign _zz_481_ = (1'b0); + assign _zz_482_ = ((_zz_491_ == _zz_492_) != (1'b0)); + assign _zz_483_ = (_zz_493_ != (1'b0)); + assign _zz_484_ = {(_zz_494_ != _zz_495_),{_zz_496_,{_zz_497_,_zz_498_}}}; + assign _zz_485_ = (32'b00000000000000000001000000110000); + assign _zz_486_ = (decode_INSTRUCTION & (32'b00000010000000000010000001100000)); + assign _zz_487_ = (32'b00000000000000000010000000100000); + assign _zz_488_ = (decode_INSTRUCTION & (32'b00000010000000000011000000100000)); + assign _zz_489_ = (32'b00000000000000000000000000100000); + assign _zz_490_ = (32'b00000010000000000100000001110100); + assign _zz_491_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); + assign _zz_492_ = (32'b00000000000000000001000000000000); + assign _zz_493_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); + assign _zz_494_ = ((decode_INSTRUCTION & (32'b00000000000000000011000001010000)) == (32'b00000000000000000000000001010000)); + assign _zz_495_ = (1'b0); + assign _zz_496_ = ({(_zz_499_ == _zz_500_),_zz_150_} != (2'b00)); + assign _zz_497_ = ({_zz_501_,_zz_150_} != (2'b00)); + assign _zz_498_ = {({_zz_502_,_zz_503_} != (5'b00000)),{(_zz_504_ != _zz_505_),{_zz_506_,{_zz_507_,_zz_508_}}}}; + assign _zz_499_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100)); + assign _zz_500_ = (32'b00000000000000000000000000000100); + assign _zz_501_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)); + assign _zz_502_ = ((decode_INSTRUCTION & _zz_509_) == (32'b00000000000000000000000001000000)); + assign _zz_503_ = {_zz_149_,{_zz_510_,{_zz_511_,_zz_512_}}}; + assign _zz_504_ = ((decode_INSTRUCTION & _zz_513_) == (32'b00000010000000000100000000100000)); + assign _zz_505_ = (1'b0); + assign _zz_506_ = ({_zz_514_,{_zz_515_,_zz_516_}} != (3'b000)); + assign _zz_507_ = (_zz_517_ != (1'b0)); + assign _zz_508_ = {(_zz_518_ != _zz_519_),(_zz_520_ != _zz_521_)}; + assign _zz_509_ = (32'b00000000000000000000000001000000); + assign _zz_510_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000100000)) == (32'b00000000000000000100000000100000)); + assign _zz_511_ = ((decode_INSTRUCTION & _zz_522_) == (32'b00000000000000000000000000010000)); + assign _zz_512_ = ((decode_INSTRUCTION & _zz_523_) == (32'b00000000000000000000000000100000)); + assign _zz_513_ = (32'b00000010000000000100000001100100); + assign _zz_514_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000001000000)); + assign _zz_515_ = ((decode_INSTRUCTION & _zz_524_) == (32'b00000000000000000000000001000000)); + assign _zz_516_ = ((decode_INSTRUCTION & _zz_525_) == (32'b00000000000000000000000000000000)); + assign _zz_517_ = ((decode_INSTRUCTION & (32'b00000000000000000101000001001000)) == (32'b00000000000000000001000000001000)); + assign _zz_518_ = ((decode_INSTRUCTION & _zz_526_) == (32'b00000000000000000100000000010000)); + assign _zz_519_ = (1'b0); + assign _zz_520_ = ((decode_INSTRUCTION & _zz_527_) == (32'b00000000000000000010000000010000)); + assign _zz_521_ = (1'b0); + assign _zz_522_ = (32'b00000000000000000000000000110000); + assign _zz_523_ = (32'b00000010000000000000000000100000); + assign _zz_524_ = (32'b00000000000000000011000001000000); + assign _zz_525_ = (32'b00000000000000000000000000111000); + assign _zz_526_ = (32'b00000000000000000100000000010100); + assign _zz_527_ = (32'b00000000000000000110000000010100); + assign _zz_528_ = (32'b00000000000000000001000001111111); + assign _zz_529_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); + assign _zz_530_ = (32'b00000000000000000010000001110011); + assign _zz_531_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); + assign _zz_532_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); + assign _zz_533_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_534_) == (32'b00000000000000000000000000000011)),{(_zz_535_ == _zz_536_),{_zz_537_,{_zz_538_,_zz_539_}}}}}}; + assign _zz_534_ = (32'b00000000000000000101000001011111); + assign _zz_535_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); + assign _zz_536_ = (32'b00000000000000000000000001100011); + assign _zz_537_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); + assign _zz_538_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_539_ = {((decode_INSTRUCTION & (32'b00000001111100000111000001111111)) == (32'b00000000000000000101000000001111)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_540_) == (32'b00000000000000000001000000010011)),{(_zz_541_ == _zz_542_),{_zz_543_,_zz_544_}}}}}; + assign _zz_540_ = (32'b11111100000000000011000001111111); + assign _zz_541_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); + assign _zz_542_ = (32'b00000000000000000101000000110011); + assign _zz_543_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_544_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); + assign _zz_545_ = execute_INSTRUCTION[31]; + assign _zz_546_ = execute_INSTRUCTION[31]; + assign _zz_547_ = execute_INSTRUCTION[7]; + always @ (posedge clk) begin + if(_zz_61_) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_370_) begin + _zz_241_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_371_) begin + _zz_242_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush(_zz_221_), + .io_cpu_prefetch_isValid(_zz_222_), + .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), + .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), + .io_cpu_fetch_isValid(_zz_223_), + .io_cpu_fetch_isStuck(_zz_224_), + .io_cpu_fetch_isRemoved(_zz_225_), + .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), + .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), + .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), + .io_cpu_fetch_dataBypass(_zz_226_), + .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), + .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), + .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), + .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), + .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), + .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), + .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), + .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), + .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), + .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), + .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), + .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), + .io_cpu_decode_isValid(_zz_227_), + .io_cpu_decode_isStuck(_zz_228_), + .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), + .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), + .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), + .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), + .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), + .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), + .io_cpu_decode_isUser(_zz_229_), + .io_cpu_fill_valid(_zz_230_), + .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), + .io_mem_cmd_ready(iBus_cmd_ready), + .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), + .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), + .io_mem_rsp_valid(iBus_rsp_valid), + .io_mem_rsp_payload_data(iBus_rsp_payload_data), + .io_mem_rsp_payload_error(iBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + DataCache dataCache_1_ ( + .io_cpu_execute_isValid(_zz_231_), + .io_cpu_execute_address(_zz_232_), + .io_cpu_execute_args_wr(execute_MEMORY_WR), + .io_cpu_execute_args_data(_zz_143_), + .io_cpu_execute_args_size(execute_DBusCachedPlugin_size), + .io_cpu_memory_isValid(_zz_233_), + .io_cpu_memory_isStuck(memory_arbitration_isStuck), + .io_cpu_memory_isRemoved(memory_arbitration_removeIt), + .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite), + .io_cpu_memory_address(_zz_234_), + .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid), + .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress), + .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation), + .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress), + .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_235_), + .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead), + .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite), + .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute), + .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception), + .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling), + .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end), + .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy), + .io_cpu_writeBack_isValid(_zz_236_), + .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck), + .io_cpu_writeBack_isUser(_zz_237_), + .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt), + .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite), + .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data), + .io_cpu_writeBack_address(_zz_238_), + .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException), + .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess), + .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError), + .io_cpu_redo(dataCache_1__io_cpu_redo), + .io_cpu_flush_valid(_zz_239_), + .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready), + .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid), + .io_mem_cmd_ready(_zz_240_), + .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr), + .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address), + .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data), + .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask), + .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length), + .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last), + .io_mem_rsp_valid(dBus_rsp_valid), + .io_mem_rsp_payload_data(dBus_rsp_payload_data), + .io_mem_rsp_payload_error(dBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_372_) + 3'b000 : begin + _zz_243_ = DBusCachedPlugin_redoBranch_payload; + end + 3'b001 : begin + _zz_243_ = CsrPlugin_jumpInterface_payload; + end + 3'b010 : begin + _zz_243_ = BranchPlugin_jumpInterface_payload; + end + 3'b011 : begin + _zz_243_ = IBusCachedPlugin_redoBranch_payload; + end + default : begin + _zz_243_ = IBusCachedPlugin_pcs_4; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_1_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_1__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_1__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_1__string = "URS1 "; + default : _zz_1__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_2_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_2__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_2__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_2__string = "URS1 "; + default : _zz_2__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_3_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_3__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_3__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_3__string = "URS1 "; + default : _zz_3__string = "????????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_4__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_4__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_4__string = "AND_1"; + default : _zz_4__string = "?????"; + endcase + end + always @(*) begin + case(_zz_5_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_5__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_5__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_5__string = "AND_1"; + default : _zz_5__string = "?????"; + endcase + end + always @(*) begin + case(_zz_6_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1"; + default : _zz_6__string = "?????"; + endcase + end + always @(*) begin + case(_zz_7_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET"; + default : _zz_7__string = "????"; + endcase + end + always @(*) begin + case(_zz_8_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8__string = "XRET"; + default : _zz_8__string = "????"; + endcase + end + always @(*) begin + case(_zz_9_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9__string = "XRET"; + default : _zz_9__string = "????"; + endcase + end + always @(*) begin + case(_zz_10_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET"; + default : _zz_10__string = "????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET"; + default : decode_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_11_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_11__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_11__string = "XRET"; + default : _zz_11__string = "????"; + endcase + end + always @(*) begin + case(_zz_12_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_12__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_12__string = "XRET"; + default : _zz_12__string = "????"; + endcase + end + always @(*) begin + case(_zz_13_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_13__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_13__string = "XRET"; + default : _zz_13__string = "????"; + endcase + end + always @(*) begin + case(_zz_14_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR"; + default : _zz_14__string = "????"; + endcase + end + always @(*) begin + case(_zz_15_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR"; + default : _zz_15__string = "????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_16_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_16__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_16__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_16__string = "PC "; + default : _zz_16__string = "???"; + endcase + end + always @(*) begin + case(_zz_17_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_17__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_17__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_17__string = "PC "; + default : _zz_17__string = "???"; + endcase + end + always @(*) begin + case(_zz_18_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18__string = "PC "; + default : _zz_18__string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_19_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE "; + default : _zz_19__string = "????????"; + endcase + end + always @(*) begin + case(_zz_20_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20__string = "BITWISE "; + default : _zz_20__string = "????????"; + endcase + end + always @(*) begin + case(_zz_21_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21__string = "BITWISE "; + default : _zz_21__string = "????????"; + endcase + end + always @(*) begin + case(_zz_22_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; + default : _zz_22__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_23_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_23__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_23__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_23__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_23__string = "SRA_1 "; + default : _zz_23__string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_24_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_24__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_24__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_24__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_24__string = "SRA_1 "; + default : _zz_24__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_25_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_25__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_25__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_25__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_25__string = "SRA_1 "; + default : _zz_25__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_26_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_26__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_26__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_26__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_26__string = "SRA_1 "; + default : _zz_26__string = "?????????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET"; + default : memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_32_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_32__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_32__string = "XRET"; + default : _zz_32__string = "????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET"; + default : execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_33_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33__string = "XRET"; + default : _zz_33__string = "????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET"; + default : writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_36_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_36__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_36__string = "XRET"; + default : _zz_36__string = "????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_39_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_39__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_39__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_39__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_39__string = "JALR"; + default : _zz_39__string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_44_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_44__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_44__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_44__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_44__string = "SRA_1 "; + default : _zz_44__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_46_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_46__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_46__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_46__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_46__string = "SRA_1 "; + default : _zz_46__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_51_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_51__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_51__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_51__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_51__string = "PC "; + default : _zz_51__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_53_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_53__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_53__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_53__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_53__string = "URS1 "; + default : _zz_53__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_56_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_56__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_56__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_56__string = "BITWISE "; + default : _zz_56__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_58_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1"; + default : _zz_58__string = "?????"; + endcase + end + always @(*) begin + case(_zz_68_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_68__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_68__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_68__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_68__string = "JALR"; + default : _zz_68__string = "????"; + endcase + end + always @(*) begin + case(_zz_73_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_73__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_73__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_73__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_73__string = "SRA_1 "; + default : _zz_73__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_74_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_74__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_74__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_74__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_74__string = "PC "; + default : _zz_74__string = "???"; + endcase + end + always @(*) begin + case(_zz_81_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_81__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_81__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_81__string = "AND_1"; + default : _zz_81__string = "?????"; + endcase + end + always @(*) begin + case(_zz_82_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_82__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_82__string = "XRET"; + default : _zz_82__string = "????"; + endcase + end + always @(*) begin + case(_zz_83_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_83__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_83__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_83__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_83__string = "URS1 "; + default : _zz_83__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_87_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_87__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_87__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_87__string = "BITWISE "; + default : _zz_87__string = "????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_95_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_95__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_95__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_95__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_95__string = "JALR"; + default : _zz_95__string = "????"; + endcase + end + always @(*) begin + case(_zz_153_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_153__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_153__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_153__string = "BITWISE "; + default : _zz_153__string = "????????"; + endcase + end + always @(*) begin + case(_zz_154_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_154__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_154__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_154__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_154__string = "URS1 "; + default : _zz_154__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_155_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_155__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_155__string = "XRET"; + default : _zz_155__string = "????"; + endcase + end + always @(*) begin + case(_zz_156_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_156__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_156__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_156__string = "AND_1"; + default : _zz_156__string = "?????"; + endcase + end + always @(*) begin + case(_zz_157_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_157__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_157__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_157__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_157__string = "PC "; + default : _zz_157__string = "???"; + endcase + end + always @(*) begin + case(_zz_158_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_158__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_158__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_158__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_158__string = "SRA_1 "; + default : _zz_158__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_159_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_159__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_159__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_159__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_159__string = "JALR"; + default : _zz_159__string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET"; + default : decode_to_execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET"; + default : execute_to_memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET"; + default : memory_to_writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + `endif + + assign decode_SRC1_CTRL = _zz_1_; + assign _zz_2_ = _zz_3_; + assign decode_MEMORY_MANAGMENT = _zz_78_; + assign decode_CSR_READ_OPCODE = _zz_34_; + assign decode_ALU_BITWISE_CTRL = _zz_4_; + assign _zz_5_ = _zz_6_; + assign decode_CSR_WRITE_OPCODE = _zz_35_; + assign decode_SRC2_FORCE_ZERO = _zz_55_; + assign execute_BRANCH_DO = _zz_38_; + assign execute_SHIFT_RIGHT = _zz_45_; + assign _zz_7_ = _zz_8_; + assign _zz_9_ = _zz_10_; + assign decode_ENV_CTRL = _zz_11_; + assign _zz_12_ = _zz_13_; + assign _zz_14_ = _zz_15_; + assign decode_IS_DIV = _zz_85_; + assign decode_SRC2_CTRL = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_IS_RS1_SIGNED = _zz_76_; + assign decode_SRC_LESS_UNSIGNED = _zz_70_; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_79_; + assign decode_PREDICTION_HAD_BRANCHED2 = _zz_41_; + assign decode_IS_RS2_SIGNED = _zz_75_; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = _zz_28_; + assign execute_MUL_HL = _zz_29_; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_77_; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_90_; + assign execute_REGFILE_WRITE_DATA = _zz_57_; + assign memory_MUL_LOW = _zz_27_; + assign decode_ALU_CTRL = _zz_19_; + assign _zz_20_ = _zz_21_; + assign execute_BRANCH_CALC = _zz_37_; + assign execute_MUL_LL = _zz_31_; + assign decode_IS_CSR = _zz_72_; + assign memory_PC = execute_to_memory_PC; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_84_; + assign _zz_22_ = _zz_23_; + assign decode_SHIFT_CTRL = _zz_24_; + assign _zz_25_ = _zz_26_; + assign execute_MUL_LH = _zz_30_; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_98_; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_80_; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_32_; + assign execute_ENV_CTRL = _zz_33_; + assign writeBack_ENV_CTRL = _zz_36_; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_40_; + assign execute_BRANCH_CTRL = _zz_39_; + assign decode_RS2_USE = _zz_71_; + assign decode_RS1_USE = _zz_64_; + always @ (*) begin + _zz_42_ = execute_REGFILE_WRITE_DATA; + if(_zz_244_)begin + _zz_42_ = execute_CsrPlugin_readData; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = _zz_62_; + if(_zz_173_)begin + if((_zz_174_ == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_175_; + end + end + if(_zz_245_)begin + if(_zz_246_)begin + if(_zz_177_)begin + decode_RS2 = _zz_89_; + end + end + end + if(_zz_247_)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_179_)begin + decode_RS2 = _zz_43_; + end + end + end + if(_zz_248_)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_181_)begin + decode_RS2 = _zz_42_; + end + end + end + end + + always @ (*) begin + decode_RS1 = _zz_63_; + if(_zz_173_)begin + if((_zz_174_ == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_175_; + end + end + if(_zz_245_)begin + if(_zz_246_)begin + if(_zz_176_)begin + decode_RS1 = _zz_89_; + end + end + end + if(_zz_247_)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_178_)begin + decode_RS1 = _zz_43_; + end + end + end + if(_zz_248_)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_180_)begin + decode_RS1 = _zz_42_; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_43_ = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_43_ = _zz_169_; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_43_ = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(_zz_249_)begin + _zz_43_ = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_44_; + assign execute_SHIFT_CTRL = _zz_46_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_50_ = execute_PC; + assign execute_SRC2_CTRL = _zz_51_; + assign execute_SRC1_CTRL = _zz_53_; + assign decode_SRC_USE_SUB_LESS = _zz_66_; + assign decode_SRC_ADD_ZERO = _zz_67_; + assign execute_SRC_ADD_SUB = _zz_49_; + assign execute_SRC_LESS = _zz_47_; + assign execute_ALU_CTRL = _zz_56_; + assign execute_SRC2 = _zz_52_; + assign execute_SRC1 = _zz_54_; + assign execute_ALU_BITWISE_CTRL = _zz_58_; + assign _zz_59_ = writeBack_INSTRUCTION; + assign _zz_60_ = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_61_ = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_61_ = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = _zz_94_; + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_69_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = _zz_88_; + assign decode_INSTRUCTION_READY = 1'b1; + always @ (*) begin + _zz_89_ = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_89_ = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_277_) + 2'b00 : begin + _zz_89_ = _zz_346_; + end + default : begin + _zz_89_ = _zz_347_; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = _zz_48_; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_65_; + assign decode_FLUSH_ALL = _zz_86_; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected = _zz_91_; + if(_zz_250_)begin + IBusCachedPlugin_rsp_issueDetected = 1'b1; + end + end + + always @ (*) begin + _zz_91_ = _zz_92_; + if(_zz_251_)begin + _zz_91_ = 1'b1; + end + end + + always @ (*) begin + _zz_92_ = _zz_93_; + if(_zz_252_)begin + _zz_92_ = 1'b1; + end + end + + always @ (*) begin + _zz_93_ = 1'b0; + if(_zz_253_)begin + _zz_93_ = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_95_; + assign decode_INSTRUCTION = _zz_99_; + always @ (*) begin + _zz_96_ = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_96_ = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_97_ = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_97_ = IBusCachedPlugin_pcs_4; + end + if(IBusCachedPlugin_redoBranch_valid)begin + _zz_97_ = IBusCachedPlugin_redoBranch_payload; + end + end + + assign decode_PC = _zz_100_; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_170_ || _zz_171_)))begin + decode_arbitration_haltByOther = 1'b1; + end + if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin + decode_arbitration_haltByOther = decode_arbitration_isValid; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_254_)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushAll = 1'b0; + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if((_zz_239_ && (! dataCache_1__io_cpu_flush_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_244_)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushAll = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + execute_arbitration_flushAll = 1'b1; + end + if(BranchPlugin_branchExceptionPort_valid)begin + execute_arbitration_flushAll = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(_zz_249_)begin + if(_zz_255_)begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushAll = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + memory_arbitration_flushAll = 1'b1; + end + if(_zz_256_)begin + memory_arbitration_flushAll = 1'b1; + end + if(_zz_257_)begin + memory_arbitration_flushAll = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1__io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushAll = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushAll = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode}}} != (4'b0000)))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_256_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_257_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + assign IBusCachedPlugin_fetcherflushIt = 1'b0; + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_256_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_257_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(_zz_256_)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + end + if(_zz_257_)begin + case(_zz_258_) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); + assign _zz_101_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; + assign _zz_102_ = (_zz_101_ & (~ _zz_278_)); + assign _zz_103_ = _zz_102_[3]; + assign _zz_104_ = _zz_102_[4]; + assign _zz_105_ = (_zz_102_[1] || _zz_103_); + assign _zz_106_ = (_zz_102_[2] || _zz_103_); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_243_; + assign _zz_107_ = (! IBusCachedPlugin_fetcherHalt); + assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_107_); + assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_107_); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload; + always @ (*) begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid && IBusCachedPlugin_iBusRsp_stages_1_input_ready))begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_280_); + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b0; + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + if(_zz_259_)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_108_; + assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc; + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_109_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_109_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_109_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_110_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_110_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_110_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + end + + assign _zz_111_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_111_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_111_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_112_; + assign _zz_112_ = ((1'b0 && (! _zz_113_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_113_ = _zz_114_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_113_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_115_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_115_ = _zz_116_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_115_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_117_; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); + assign _zz_100_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_99_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_98_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign _zz_118_ = _zz_281_[11]; + always @ (*) begin + _zz_119_[18] = _zz_118_; + _zz_119_[17] = _zz_118_; + _zz_119_[16] = _zz_118_; + _zz_119_[15] = _zz_118_; + _zz_119_[14] = _zz_118_; + _zz_119_[13] = _zz_118_; + _zz_119_[12] = _zz_118_; + _zz_119_[11] = _zz_118_; + _zz_119_[10] = _zz_118_; + _zz_119_[9] = _zz_118_; + _zz_119_[8] = _zz_118_; + _zz_119_[7] = _zz_118_; + _zz_119_[6] = _zz_118_; + _zz_119_[5] = _zz_118_; + _zz_119_[4] = _zz_118_; + _zz_119_[3] = _zz_118_; + _zz_119_[2] = _zz_118_; + _zz_119_[1] = _zz_118_; + _zz_119_[0] = _zz_118_; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_282_[31])); + if(_zz_124_)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_120_ = _zz_283_[19]; + always @ (*) begin + _zz_121_[10] = _zz_120_; + _zz_121_[9] = _zz_120_; + _zz_121_[8] = _zz_120_; + _zz_121_[7] = _zz_120_; + _zz_121_[6] = _zz_120_; + _zz_121_[5] = _zz_120_; + _zz_121_[4] = _zz_120_; + _zz_121_[3] = _zz_120_; + _zz_121_[2] = _zz_120_; + _zz_121_[1] = _zz_120_; + _zz_121_[0] = _zz_120_; + end + + assign _zz_122_ = _zz_284_[11]; + always @ (*) begin + _zz_123_[18] = _zz_122_; + _zz_123_[17] = _zz_122_; + _zz_123_[16] = _zz_122_; + _zz_123_[15] = _zz_122_; + _zz_123_[14] = _zz_122_; + _zz_123_[13] = _zz_122_; + _zz_123_[12] = _zz_122_; + _zz_123_[11] = _zz_122_; + _zz_123_[10] = _zz_122_; + _zz_123_[9] = _zz_122_; + _zz_123_[8] = _zz_122_; + _zz_123_[7] = _zz_122_; + _zz_123_[6] = _zz_122_; + _zz_123_[5] = _zz_122_; + _zz_123_[4] = _zz_122_; + _zz_123_[3] = _zz_122_; + _zz_123_[2] = _zz_122_; + _zz_123_[1] = _zz_122_; + _zz_123_[0] = _zz_122_; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_124_ = _zz_285_[1]; + end + default : begin + _zz_124_ = _zz_286_[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (IBusCachedPlugin_decodePrediction_cmd_hadBranch && decode_arbitration_isFiring); + assign _zz_125_ = _zz_287_[19]; + always @ (*) begin + _zz_126_[10] = _zz_125_; + _zz_126_[9] = _zz_125_; + _zz_126_[8] = _zz_125_; + _zz_126_[7] = _zz_125_; + _zz_126_[6] = _zz_125_; + _zz_126_[5] = _zz_125_; + _zz_126_[4] = _zz_125_; + _zz_126_[3] = _zz_125_; + _zz_126_[2] = _zz_125_; + _zz_126_[1] = _zz_125_; + _zz_126_[0] = _zz_125_; + end + + assign _zz_127_ = _zz_288_[11]; + always @ (*) begin + _zz_128_[18] = _zz_127_; + _zz_128_[17] = _zz_127_; + _zz_128_[16] = _zz_127_; + _zz_128_[15] = _zz_127_; + _zz_128_[14] = _zz_127_; + _zz_128_[13] = _zz_127_; + _zz_128_[12] = _zz_127_; + _zz_128_[11] = _zz_127_; + _zz_128_[10] = _zz_127_; + _zz_128_[9] = _zz_127_; + _zz_128_[8] = _zz_127_; + _zz_128_[7] = _zz_127_; + _zz_128_[6] = _zz_127_; + _zz_128_[5] = _zz_127_; + _zz_128_[4] = _zz_127_; + _zz_128_[3] = _zz_127_; + _zz_128_[2] = _zz_127_; + _zz_128_[1] = _zz_127_; + _zz_128_[0] = _zz_127_; + end + + assign IBusCachedPlugin_pcs_4 = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_126_,{{{_zz_373_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_128_,{{{_zz_374_,_zz_375_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_222_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_225_ = (IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt); + assign _zz_226_ = (32'b00000000000000000000000000000000); + assign _zz_223_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_224_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_227_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_228_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_229_ = (CsrPlugin_privilege == (2'b00)); + assign _zz_94_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_253_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_251_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + end + end + + always @ (*) begin + _zz_230_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_251_)begin + _zz_230_ = 1'b1; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + _zz_230_ = 1'b0; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_252_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_250_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(IBusCachedPlugin_fetcherHalt)begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); + if(_zz_252_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + end + if(_zz_250_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; + assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; + assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + assign _zz_221_ = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_129_); + assign _zz_240_ = (! _zz_129_); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_129_ ? _zz_130_ : dataCache_1__io_mem_cmd_payload_wr); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_129_ ? _zz_131_ : dataCache_1__io_mem_cmd_payload_address); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_129_ ? _zz_132_ : dataCache_1__io_mem_cmd_payload_data); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_129_ ? _zz_133_ : dataCache_1__io_mem_cmd_payload_mask); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_129_ ? _zz_134_ : dataCache_1__io_mem_cmd_payload_length); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_129_ ? _zz_135_ : dataCache_1__io_mem_cmd_payload_last); + assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_136_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_137_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_138_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_139_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_140_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_141_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_142_; + assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign _zz_231_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_232_ = execute_SRC_ADD; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_143_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_143_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_143_ = execute_RS2[31 : 0]; + end + endcase + end + + assign _zz_239_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_90_ = _zz_232_[1 : 0]; + assign _zz_233_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_234_ = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; + assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + always @ (*) begin + _zz_235_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1__io_cpu_memory_isWrite)))begin + _zz_235_ = 1'b1; + end + end + + assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; + assign _zz_236_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_237_ = (CsrPlugin_privilege == (2'b00)); + assign _zz_238_ = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_260_)begin + if(dataCache_1__io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_260_)begin + if(dataCache_1__io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); + if(_zz_260_)begin + if(dataCache_1__io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_289_}; + end + if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_290_}; + end + if(dataCache_1__io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_144_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_145_[31] = _zz_144_; + _zz_145_[30] = _zz_144_; + _zz_145_[29] = _zz_144_; + _zz_145_[28] = _zz_144_; + _zz_145_[27] = _zz_144_; + _zz_145_[26] = _zz_144_; + _zz_145_[25] = _zz_144_; + _zz_145_[24] = _zz_144_; + _zz_145_[23] = _zz_144_; + _zz_145_[22] = _zz_144_; + _zz_145_[21] = _zz_144_; + _zz_145_[20] = _zz_144_; + _zz_145_[19] = _zz_144_; + _zz_145_[18] = _zz_144_; + _zz_145_[17] = _zz_144_; + _zz_145_[16] = _zz_144_; + _zz_145_[15] = _zz_144_; + _zz_145_[14] = _zz_144_; + _zz_145_[13] = _zz_144_; + _zz_145_[12] = _zz_144_; + _zz_145_[11] = _zz_144_; + _zz_145_[10] = _zz_144_; + _zz_145_[9] = _zz_144_; + _zz_145_[8] = _zz_144_; + _zz_145_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_146_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_147_[31] = _zz_146_; + _zz_147_[30] = _zz_146_; + _zz_147_[29] = _zz_146_; + _zz_147_[28] = _zz_146_; + _zz_147_[27] = _zz_146_; + _zz_147_[26] = _zz_146_; + _zz_147_[25] = _zz_146_; + _zz_147_[24] = _zz_146_; + _zz_147_[23] = _zz_146_; + _zz_147_[22] = _zz_146_; + _zz_147_[21] = _zz_146_; + _zz_147_[20] = _zz_146_; + _zz_147_[19] = _zz_146_; + _zz_147_[18] = _zz_146_; + _zz_147_[17] = _zz_146_; + _zz_147_[16] = _zz_146_; + _zz_147_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_275_) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_145_; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_147_; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_149_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_150_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_151_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000000000000000000)); + assign _zz_152_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_148_ = {({(_zz_376_ == _zz_377_),{_zz_378_,{_zz_379_,_zz_380_}}} != (4'b0000)),{((_zz_381_ == _zz_382_) != (1'b0)),{({_zz_383_,_zz_384_} != (3'b000)),{(_zz_385_ != _zz_386_),{_zz_387_,{_zz_388_,_zz_389_}}}}}}; + assign _zz_88_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_528_) == (32'b00000000000000000001000001110011)),{(_zz_529_ == _zz_530_),{_zz_531_,{_zz_532_,_zz_533_}}}}}}} != (19'b0000000000000000000)); + assign _zz_153_ = _zz_148_[1 : 0]; + assign _zz_87_ = _zz_153_; + assign _zz_86_ = _zz_291_[0]; + assign _zz_85_ = _zz_292_[0]; + assign _zz_84_ = _zz_293_[0]; + assign _zz_154_ = _zz_148_[7 : 6]; + assign _zz_83_ = _zz_154_; + assign _zz_155_ = _zz_148_[8 : 8]; + assign _zz_82_ = _zz_155_; + assign _zz_156_ = _zz_148_[10 : 9]; + assign _zz_81_ = _zz_156_; + assign _zz_80_ = _zz_294_[0]; + assign _zz_79_ = _zz_295_[0]; + assign _zz_78_ = _zz_296_[0]; + assign _zz_77_ = _zz_297_[0]; + assign _zz_76_ = _zz_298_[0]; + assign _zz_75_ = _zz_299_[0]; + assign _zz_157_ = _zz_148_[18 : 17]; + assign _zz_74_ = _zz_157_; + assign _zz_158_ = _zz_148_[20 : 19]; + assign _zz_73_ = _zz_158_; + assign _zz_72_ = _zz_300_[0]; + assign _zz_71_ = _zz_301_[0]; + assign _zz_70_ = _zz_302_[0]; + assign _zz_69_ = _zz_303_[0]; + assign _zz_159_ = _zz_148_[26 : 25]; + assign _zz_68_ = _zz_159_; + assign _zz_67_ = _zz_304_[0]; + assign _zz_66_ = _zz_305_[0]; + assign _zz_65_ = _zz_306_[0]; + assign _zz_64_ = _zz_307_[0]; + assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = (4'b0010); + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_241_; + assign decode_RegFilePlugin_rs2Data = _zz_242_; + assign _zz_63_ = decode_RegFilePlugin_rs1Data; + assign _zz_62_ = decode_RegFilePlugin_rs2Data; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_60_ && writeBack_arbitration_isFiring); + if(_zz_160_)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + assign lastStageRegFileWrite_payload_address = _zz_59_[11 : 7]; + assign lastStageRegFileWrite_payload_data = _zz_89_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_161_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_161_ = {31'd0, _zz_308_}; + end + default : begin + _zz_161_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_57_ = _zz_161_; + assign _zz_55_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_162_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_162_ = {29'd0, _zz_309_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_162_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_162_ = {27'd0, _zz_310_}; + end + endcase + end + + assign _zz_54_ = _zz_162_; + assign _zz_163_ = _zz_311_[11]; + always @ (*) begin + _zz_164_[19] = _zz_163_; + _zz_164_[18] = _zz_163_; + _zz_164_[17] = _zz_163_; + _zz_164_[16] = _zz_163_; + _zz_164_[15] = _zz_163_; + _zz_164_[14] = _zz_163_; + _zz_164_[13] = _zz_163_; + _zz_164_[12] = _zz_163_; + _zz_164_[11] = _zz_163_; + _zz_164_[10] = _zz_163_; + _zz_164_[9] = _zz_163_; + _zz_164_[8] = _zz_163_; + _zz_164_[7] = _zz_163_; + _zz_164_[6] = _zz_163_; + _zz_164_[5] = _zz_163_; + _zz_164_[4] = _zz_163_; + _zz_164_[3] = _zz_163_; + _zz_164_[2] = _zz_163_; + _zz_164_[1] = _zz_163_; + _zz_164_[0] = _zz_163_; + end + + assign _zz_165_ = _zz_312_[11]; + always @ (*) begin + _zz_166_[19] = _zz_165_; + _zz_166_[18] = _zz_165_; + _zz_166_[17] = _zz_165_; + _zz_166_[16] = _zz_165_; + _zz_166_[15] = _zz_165_; + _zz_166_[14] = _zz_165_; + _zz_166_[13] = _zz_165_; + _zz_166_[12] = _zz_165_; + _zz_166_[11] = _zz_165_; + _zz_166_[10] = _zz_165_; + _zz_166_[9] = _zz_165_; + _zz_166_[8] = _zz_165_; + _zz_166_[7] = _zz_165_; + _zz_166_[6] = _zz_165_; + _zz_166_[5] = _zz_165_; + _zz_166_[4] = _zz_165_; + _zz_166_[3] = _zz_165_; + _zz_166_[2] = _zz_165_; + _zz_166_[1] = _zz_165_; + _zz_166_[0] = _zz_165_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_167_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_167_ = {_zz_164_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_167_ = {_zz_166_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_167_ = _zz_50_; + end + endcase + end + + assign _zz_52_ = _zz_167_; + always @ (*) begin + execute_SrcPlugin_addSub = _zz_313_; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_49_ = execute_SrcPlugin_addSub; + assign _zz_48_ = execute_SrcPlugin_addSub; + assign _zz_47_ = execute_SrcPlugin_less; + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_168_[0] = execute_SRC1[31]; + _zz_168_[1] = execute_SRC1[30]; + _zz_168_[2] = execute_SRC1[29]; + _zz_168_[3] = execute_SRC1[28]; + _zz_168_[4] = execute_SRC1[27]; + _zz_168_[5] = execute_SRC1[26]; + _zz_168_[6] = execute_SRC1[25]; + _zz_168_[7] = execute_SRC1[24]; + _zz_168_[8] = execute_SRC1[23]; + _zz_168_[9] = execute_SRC1[22]; + _zz_168_[10] = execute_SRC1[21]; + _zz_168_[11] = execute_SRC1[20]; + _zz_168_[12] = execute_SRC1[19]; + _zz_168_[13] = execute_SRC1[18]; + _zz_168_[14] = execute_SRC1[17]; + _zz_168_[15] = execute_SRC1[16]; + _zz_168_[16] = execute_SRC1[15]; + _zz_168_[17] = execute_SRC1[14]; + _zz_168_[18] = execute_SRC1[13]; + _zz_168_[19] = execute_SRC1[12]; + _zz_168_[20] = execute_SRC1[11]; + _zz_168_[21] = execute_SRC1[10]; + _zz_168_[22] = execute_SRC1[9]; + _zz_168_[23] = execute_SRC1[8]; + _zz_168_[24] = execute_SRC1[7]; + _zz_168_[25] = execute_SRC1[6]; + _zz_168_[26] = execute_SRC1[5]; + _zz_168_[27] = execute_SRC1[4]; + _zz_168_[28] = execute_SRC1[3]; + _zz_168_[29] = execute_SRC1[2]; + _zz_168_[30] = execute_SRC1[1]; + _zz_168_[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_168_ : execute_SRC1); + assign _zz_45_ = _zz_321_; + always @ (*) begin + _zz_169_[0] = memory_SHIFT_RIGHT[31]; + _zz_169_[1] = memory_SHIFT_RIGHT[30]; + _zz_169_[2] = memory_SHIFT_RIGHT[29]; + _zz_169_[3] = memory_SHIFT_RIGHT[28]; + _zz_169_[4] = memory_SHIFT_RIGHT[27]; + _zz_169_[5] = memory_SHIFT_RIGHT[26]; + _zz_169_[6] = memory_SHIFT_RIGHT[25]; + _zz_169_[7] = memory_SHIFT_RIGHT[24]; + _zz_169_[8] = memory_SHIFT_RIGHT[23]; + _zz_169_[9] = memory_SHIFT_RIGHT[22]; + _zz_169_[10] = memory_SHIFT_RIGHT[21]; + _zz_169_[11] = memory_SHIFT_RIGHT[20]; + _zz_169_[12] = memory_SHIFT_RIGHT[19]; + _zz_169_[13] = memory_SHIFT_RIGHT[18]; + _zz_169_[14] = memory_SHIFT_RIGHT[17]; + _zz_169_[15] = memory_SHIFT_RIGHT[16]; + _zz_169_[16] = memory_SHIFT_RIGHT[15]; + _zz_169_[17] = memory_SHIFT_RIGHT[14]; + _zz_169_[18] = memory_SHIFT_RIGHT[13]; + _zz_169_[19] = memory_SHIFT_RIGHT[12]; + _zz_169_[20] = memory_SHIFT_RIGHT[11]; + _zz_169_[21] = memory_SHIFT_RIGHT[10]; + _zz_169_[22] = memory_SHIFT_RIGHT[9]; + _zz_169_[23] = memory_SHIFT_RIGHT[8]; + _zz_169_[24] = memory_SHIFT_RIGHT[7]; + _zz_169_[25] = memory_SHIFT_RIGHT[6]; + _zz_169_[26] = memory_SHIFT_RIGHT[5]; + _zz_169_[27] = memory_SHIFT_RIGHT[4]; + _zz_169_[28] = memory_SHIFT_RIGHT[3]; + _zz_169_[29] = memory_SHIFT_RIGHT[2]; + _zz_169_[30] = memory_SHIFT_RIGHT[1]; + _zz_169_[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_170_ = 1'b0; + if(_zz_261_)begin + if(_zz_262_)begin + if(_zz_176_)begin + _zz_170_ = 1'b1; + end + end + end + if(_zz_263_)begin + if(_zz_264_)begin + if(_zz_178_)begin + _zz_170_ = 1'b1; + end + end + end + if(_zz_265_)begin + if(_zz_266_)begin + if(_zz_180_)begin + _zz_170_ = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_170_ = 1'b0; + end + end + + always @ (*) begin + _zz_171_ = 1'b0; + if(_zz_261_)begin + if(_zz_262_)begin + if(_zz_177_)begin + _zz_171_ = 1'b1; + end + end + end + if(_zz_263_)begin + if(_zz_264_)begin + if(_zz_179_)begin + _zz_171_ = 1'b1; + end + end + end + if(_zz_265_)begin + if(_zz_266_)begin + if(_zz_181_)begin + _zz_171_ = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_171_ = 1'b0; + end + end + + assign _zz_172_ = (_zz_60_ && writeBack_arbitration_isFiring); + assign _zz_176_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_177_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_178_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_179_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_180_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_181_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_41_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_182_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_182_ == (3'b000))) begin + _zz_183_ = execute_BranchPlugin_eq; + end else if((_zz_182_ == (3'b001))) begin + _zz_183_ = (! execute_BranchPlugin_eq); + end else if((((_zz_182_ & (3'b101)) == (3'b101)))) begin + _zz_183_ = (! execute_SRC_LESS); + end else begin + _zz_183_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_184_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_184_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_184_ = 1'b1; + end + default : begin + _zz_184_ = _zz_183_; + end + endcase + end + + assign _zz_40_ = _zz_184_; + assign _zz_185_ = _zz_323_[11]; + always @ (*) begin + _zz_186_[19] = _zz_185_; + _zz_186_[18] = _zz_185_; + _zz_186_[17] = _zz_185_; + _zz_186_[16] = _zz_185_; + _zz_186_[15] = _zz_185_; + _zz_186_[14] = _zz_185_; + _zz_186_[13] = _zz_185_; + _zz_186_[12] = _zz_185_; + _zz_186_[11] = _zz_185_; + _zz_186_[10] = _zz_185_; + _zz_186_[9] = _zz_185_; + _zz_186_[8] = _zz_185_; + _zz_186_[7] = _zz_185_; + _zz_186_[6] = _zz_185_; + _zz_186_[5] = _zz_185_; + _zz_186_[4] = _zz_185_; + _zz_186_[3] = _zz_185_; + _zz_186_[2] = _zz_185_; + _zz_186_[1] = _zz_185_; + _zz_186_[0] = _zz_185_; + end + + assign _zz_187_ = _zz_324_[19]; + always @ (*) begin + _zz_188_[10] = _zz_187_; + _zz_188_[9] = _zz_187_; + _zz_188_[8] = _zz_187_; + _zz_188_[7] = _zz_187_; + _zz_188_[6] = _zz_187_; + _zz_188_[5] = _zz_187_; + _zz_188_[4] = _zz_187_; + _zz_188_[3] = _zz_187_; + _zz_188_[2] = _zz_187_; + _zz_188_[1] = _zz_187_; + _zz_188_[0] = _zz_187_; + end + + assign _zz_189_ = _zz_325_[11]; + always @ (*) begin + _zz_190_[18] = _zz_189_; + _zz_190_[17] = _zz_189_; + _zz_190_[16] = _zz_189_; + _zz_190_[15] = _zz_189_; + _zz_190_[14] = _zz_189_; + _zz_190_[13] = _zz_189_; + _zz_190_[12] = _zz_189_; + _zz_190_[11] = _zz_189_; + _zz_190_[10] = _zz_189_; + _zz_190_[9] = _zz_189_; + _zz_190_[8] = _zz_189_; + _zz_190_[7] = _zz_189_; + _zz_190_[6] = _zz_189_; + _zz_190_[5] = _zz_189_; + _zz_190_[4] = _zz_189_; + _zz_190_[3] = _zz_189_; + _zz_190_[2] = _zz_189_; + _zz_190_[1] = _zz_189_; + _zz_190_[0] = _zz_189_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_191_ = (_zz_326_[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_191_ = _zz_327_[1]; + end + default : begin + _zz_191_ = _zz_328_[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_191_); + assign _zz_38_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_192_ = _zz_329_[11]; + always @ (*) begin + _zz_193_[19] = _zz_192_; + _zz_193_[18] = _zz_192_; + _zz_193_[17] = _zz_192_; + _zz_193_[16] = _zz_192_; + _zz_193_[15] = _zz_192_; + _zz_193_[14] = _zz_192_; + _zz_193_[13] = _zz_192_; + _zz_193_[12] = _zz_192_; + _zz_193_[11] = _zz_192_; + _zz_193_[10] = _zz_192_; + _zz_193_[9] = _zz_192_; + _zz_193_[8] = _zz_192_; + _zz_193_[7] = _zz_192_; + _zz_193_[6] = _zz_192_; + _zz_193_[5] = _zz_192_; + _zz_193_[4] = _zz_192_; + _zz_193_[3] = _zz_192_; + _zz_193_[2] = _zz_192_; + _zz_193_[1] = _zz_192_; + _zz_193_[0] = _zz_192_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_193_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_195_,{{{_zz_545_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_197_,{{{_zz_546_,_zz_547_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_332_}; + end + end + endcase + end + + assign _zz_194_ = _zz_330_[19]; + always @ (*) begin + _zz_195_[10] = _zz_194_; + _zz_195_[9] = _zz_194_; + _zz_195_[8] = _zz_194_; + _zz_195_[7] = _zz_194_; + _zz_195_[6] = _zz_194_; + _zz_195_[5] = _zz_194_; + _zz_195_[4] = _zz_194_; + _zz_195_[3] = _zz_194_; + _zz_195_[2] = _zz_194_; + _zz_195_[1] = _zz_194_; + _zz_195_[0] = _zz_194_; + end + + assign _zz_196_ = _zz_331_[11]; + always @ (*) begin + _zz_197_[18] = _zz_196_; + _zz_197_[17] = _zz_196_; + _zz_197_[16] = _zz_196_; + _zz_197_[15] = _zz_196_; + _zz_197_[14] = _zz_196_; + _zz_197_[13] = _zz_196_; + _zz_197_[12] = _zz_196_; + _zz_197_[11] = _zz_196_; + _zz_197_[10] = _zz_196_; + _zz_197_[9] = _zz_196_; + _zz_197_[8] = _zz_196_; + _zz_197_[7] = _zz_196_; + _zz_197_[6] = _zz_196_; + _zz_197_[5] = _zz_196_; + _zz_197_[4] = _zz_196_; + _zz_197_[3] = _zz_196_; + _zz_197_[2] = _zz_196_; + _zz_197_[1] = _zz_196_; + _zz_197_[0] = _zz_196_; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_37_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && (! memory_arbitration_isStuckByOthers)) && memory_BRANCH_DO); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @ (*) begin + CsrPlugin_privilege = (2'b11); + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = (2'b11); + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); + assign _zz_198_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_199_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_200_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_201_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_202_ = _zz_333_[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_254_)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = (2'bxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign _zz_35_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_34_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_inWfi = 1'b0; + assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b110011000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_readData[31 : 0] = _zz_210_; + end + 12'b001100000000 : begin + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b110011000000 : begin + execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000); + execute_CsrPlugin_readData[25 : 20] = (6'b100000); + end + 12'b001101000011 : begin + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + execute_CsrPlugin_readData[31 : 0] = _zz_211_; + end + 12'b001100000100 : begin + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + end + + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_276_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_MulPlugin_a = execute_SRC1; + assign execute_MulPlugin_b = execute_SRC2; + always @ (*) begin + case(_zz_267_) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_267_) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign _zz_31_ = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign _zz_30_ = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign _zz_29_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign _zz_28_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign _zz_27_ = ($signed(_zz_335_) + $signed(_zz_343_)); + assign writeBack_MulPlugin_result = ($signed(_zz_344_) + $signed(_zz_345_)); + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_249_)begin + if(_zz_255_)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_268_)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == (6'b100001)); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = (6'b000000); + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_349_); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = (6'b000000); + end + end + + assign _zz_203_ = memory_DivPlugin_rs1[31 : 0]; + assign _zz_204_ = {memory_DivPlugin_accumulator[31 : 0],_zz_203_[31]}; + assign _zz_205_ = (_zz_204_ - _zz_350_); + assign _zz_206_ = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_207_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_208_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_209_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_209_[31 : 0] = execute_RS1; + end + + assign _zz_211_ = (_zz_210_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_211_ != (32'b00000000000000000000000000000000)); + assign _zz_26_ = decode_SHIFT_CTRL; + assign _zz_23_ = execute_SHIFT_CTRL; + assign _zz_24_ = _zz_73_; + assign _zz_46_ = decode_to_execute_SHIFT_CTRL; + assign _zz_44_ = execute_to_memory_SHIFT_CTRL; + assign _zz_21_ = decode_ALU_CTRL; + assign _zz_19_ = _zz_87_; + assign _zz_56_ = decode_to_execute_ALU_CTRL; + assign _zz_18_ = decode_SRC2_CTRL; + assign _zz_16_ = _zz_74_; + assign _zz_51_ = decode_to_execute_SRC2_CTRL; + assign _zz_15_ = decode_BRANCH_CTRL; + assign _zz_95_ = _zz_68_; + assign _zz_39_ = decode_to_execute_BRANCH_CTRL; + assign _zz_13_ = decode_ENV_CTRL; + assign _zz_10_ = execute_ENV_CTRL; + assign _zz_8_ = memory_ENV_CTRL; + assign _zz_11_ = _zz_82_; + assign _zz_33_ = decode_to_execute_ENV_CTRL; + assign _zz_32_ = execute_to_memory_ENV_CTRL; + assign _zz_36_ = memory_to_writeBack_ENV_CTRL; + assign _zz_6_ = decode_ALU_BITWISE_CTRL; + assign _zz_4_ = _zz_81_; + assign _zz_58_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_3_ = decode_SRC1_CTRL; + assign _zz_1_ = _zz_83_; + assign _zz_53_ = decode_to_execute_SRC1_CTRL; + assign decode_arbitration_isFlushed = ({writeBack_arbitration_flushAll,{memory_arbitration_flushAll,{execute_arbitration_flushAll,decode_arbitration_flushAll}}} != (4'b0000)); + assign execute_arbitration_isFlushed = ({writeBack_arbitration_flushAll,{memory_arbitration_flushAll,execute_arbitration_flushAll}} != (3'b000)); + assign memory_arbitration_isFlushed = ({writeBack_arbitration_flushAll,memory_arbitration_flushAll} != (2'b00)); + assign writeBack_arbitration_isFlushed = (writeBack_arbitration_flushAll != (1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign iBusWishbone_ADR = {_zz_369_,_zz_212_}; + assign iBusWishbone_CTI = ((_zz_212_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_269_)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_269_)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_213_; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_219_ = (dBus_cmd_payload_length != (3'b000)); + assign _zz_215_ = dBus_cmd_valid; + assign _zz_217_ = dBus_cmd_payload_wr; + assign _zz_218_ = (_zz_214_ == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_216_ && (_zz_217_ || _zz_218_)); + assign dBusWishbone_ADR = ((_zz_219_ ? {{dBus_cmd_payload_address[31 : 5],_zz_214_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); + assign dBusWishbone_CTI = (_zz_219_ ? (_zz_218_ ? (3'b111) : (3'b010)) : (3'b000)); + assign dBusWishbone_BTE = (2'b00); + assign dBusWishbone_SEL = (_zz_217_ ? dBus_cmd_payload_mask : (4'b1111)); + assign dBusWishbone_WE = _zz_217_; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_216_ = (_zz_215_ && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_215_; + assign dBusWishbone_STB = _zz_215_; + assign dBus_rsp_valid = _zz_220_; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_108_ <= 1'b0; + _zz_114_ <= 1'b0; + _zz_116_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + _zz_129_ <= 1'b0; + _zz_136_ <= 1'b0; + _zz_160_ <= 1'b1; + _zz_173_ <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= (6'b000000); + _zz_210_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); + memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); + _zz_212_ <= (3'b000); + _zz_213_ <= 1'b0; + _zz_214_ <= (3'b000); + _zz_220_ <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(_zz_259_)begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_samplePcNext)begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + _zz_108_ <= 1'b1; + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + _zz_114_ <= 1'b0; + end + if(_zz_112_)begin + _zz_114_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_116_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + _zz_116_ <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + end + if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin + _zz_129_ <= 1'b0; + end + if(_zz_270_)begin + _zz_129_ <= dataCache_1__io_mem_cmd_valid; + end + if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin + _zz_136_ <= dataCache_1__io_mem_cmd_s2mPipe_valid; + end + _zz_160_ <= 1'b0; + _zz_173_ <= _zz_172_; + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_271_)begin + if(_zz_272_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_273_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_274_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_256_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_257_)begin + case(_zz_258_) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= ({_zz_200_,{_zz_199_,_zz_198_}} != (3'b000)); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_43_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_210_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_363_[0]; + CsrPlugin_mstatus_MIE <= _zz_364_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + end + 12'b110011000000 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_366_[0]; + CsrPlugin_mie_MTIE <= _zz_367_[0]; + CsrPlugin_mie_MSIE <= _zz_368_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(_zz_269_)begin + if(iBusWishbone_ACK)begin + _zz_212_ <= (_zz_212_ + (3'b001)); + end + end + _zz_213_ <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_215_ && _zz_216_))begin + _zz_214_ <= (_zz_214_ + (3'b001)); + if(_zz_218_)begin + _zz_214_ <= (3'b000); + end + end + _zz_220_ <= ((_zz_215_ && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_117_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_270_)begin + _zz_130_ <= dataCache_1__io_mem_cmd_payload_wr; + _zz_131_ <= dataCache_1__io_mem_cmd_payload_address; + _zz_132_ <= dataCache_1__io_mem_cmd_payload_data; + _zz_133_ <= dataCache_1__io_mem_cmd_payload_mask; + _zz_134_ <= dataCache_1__io_mem_cmd_payload_length; + _zz_135_ <= dataCache_1__io_mem_cmd_payload_last; + end + if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin + _zz_137_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr; + _zz_138_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address; + _zz_139_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data; + _zz_140_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask; + _zz_141_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length; + _zz_142_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last; + end + if(_zz_172_)begin + _zz_174_ <= _zz_59_[11 : 7]; + _zz_175_ <= _zz_89_; + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(_zz_254_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_202_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_202_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_271_)begin + if(_zz_272_)begin + CsrPlugin_interrupt_code <= (4'b0111); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_273_)begin + CsrPlugin_interrupt_code <= (4'b0011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_274_)begin + CsrPlugin_interrupt_code <= (4'b1011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + end + if(_zz_256_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if((memory_DivPlugin_div_counter_value == (6'b100000)))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_249_)begin + if(_zz_255_)begin + memory_DivPlugin_rs1[31 : 0] <= _zz_351_[31:0]; + memory_DivPlugin_accumulator[31 : 0] <= ((! _zz_205_[32]) ? _zz_352_ : _zz_353_); + if((memory_DivPlugin_div_counter_value == (6'b100000)))begin + memory_DivPlugin_div_result <= _zz_354_[31:0]; + end + end + end + if(_zz_268_)begin + memory_DivPlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); + memory_DivPlugin_rs1 <= ((_zz_208_ ? (~ _zz_209_) : _zz_209_) + _zz_360_); + memory_DivPlugin_rs2 <= ((_zz_207_ ? (~ execute_RS2) : execute_RS2) + _zz_362_); + memory_DivPlugin_div_needRevert <= ((_zz_208_ ^ (_zz_207_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_97_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_96_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_25_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_22_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_50_; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_20_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_42_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_17_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_14_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_12_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_9_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_7_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_5_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_2_; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_365_[0]; + end + end + 12'b110011000000 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + +endmodule + diff --git a/examples/soc/sources/crg.v b/examples/soc/sources/crg.v new file mode 100644 index 00000000..87166021 --- /dev/null +++ b/examples/soc/sources/crg.v @@ -0,0 +1,24 @@ +/* Machine-generated using Migen */ +module crg( + input clk100, + output sys_clk, + output sys_rst +); + +wire por_clk; +reg int_rst = 1'd1; + +// synthesis translate_off +reg dummy_s; +initial dummy_s <= 1'd0; +// synthesis translate_on + +assign sys_clk = clk100; +assign por_clk = clk100; +assign sys_rst = int_rst; + +always @(posedge por_clk) begin + int_rst <= 1'd0; +end + +endmodule diff --git a/examples/soc/sources/mem.v b/examples/soc/sources/mem.v new file mode 100644 index 00000000..e279f4d6 --- /dev/null +++ b/examples/soc/sources/mem.v @@ -0,0 +1,73 @@ +// Copyright (c) 2023-2024 Antmicro +// SPDX-License-Identifier: Apache-2.0 + +module mem #( + parameter depth = 256, + parameter memfile = "" +)( + input [29:0] mem_bus_adr, + input [31:0] mem_bus_dat_w, + output [31:0] mem_bus_dat_r, + input [3:0] mem_bus_sel, + input mem_bus_cyc, + input mem_bus_stb, + output reg mem_bus_ack, + input mem_bus_we, + input [2:0] mem_bus_cti, + input [1:0] mem_bus_bte, + input mem_bus_err, + input sys_clk, + input sys_rst +); + +localparam aw = $clog2(depth); + +reg adr_burst = 1'd0; +wire [aw-1:0] adr; +wire [31:0] dat_r; +reg [3:0] we; +wire [31:0] dat_w; + + +always @(*) begin + we <= 4'd0; + we[0] <= (((mem_bus_cyc & mem_bus_stb) & mem_bus_we) & mem_bus_sel[0]); + we[1] <= (((mem_bus_cyc & mem_bus_stb) & mem_bus_we) & mem_bus_sel[1]); + we[2] <= (((mem_bus_cyc & mem_bus_stb) & mem_bus_we) & mem_bus_sel[2]); + we[3] <= (((mem_bus_cyc & mem_bus_stb) & mem_bus_we) & mem_bus_sel[3]); +end +assign adr = mem_bus_adr[aw-1:0]; +assign mem_bus_dat_r = dat_r; +assign dat_w = mem_bus_dat_w; + +always @(posedge sys_clk) begin + mem_bus_ack <= 1'd0; + if (((mem_bus_cyc & mem_bus_stb) & ((~mem_bus_ack) | adr_burst))) begin + mem_bus_ack <= 1'd1; + end + if (sys_rst) begin + mem_bus_ack <= 1'd0; + end +end + +reg [31:0] mem[0:depth-1]; +reg [aw-1:0] memadr; +always @(posedge sys_clk) begin + if (we[0]) + mem[adr][7:0] <= dat_w[7:0]; + if (we[1]) + mem[adr][15:8] <= dat_w[15:8]; + if (we[2]) + mem[adr][23:16] <= dat_w[23:16]; + if (we[3]) + mem[adr][31:24] <= dat_w[31:24]; + memadr <= adr; +end + +assign dat_r = mem[memadr]; + +initial begin + $readmemh(memfile, mem); +end + +endmodule diff --git a/examples/soc/sources/wb_interconnect.v b/examples/soc/sources/wb_interconnect.v new file mode 100644 index 00000000..80671f87 --- /dev/null +++ b/examples/soc/sources/wb_interconnect.v @@ -0,0 +1,915 @@ +(* generator = "Amaranth" *) +module wb_interconnect (rst, wb_ram_instr_mem_bus_dat_w, wb_ram_instr_mem_bus_bte, wb_ram_instr_mem_bus_sel, wb_ram_instr_mem_bus_cyc, wb_ram_instr_mem_bus_cti, wb_ram_instr_mem_bus_adr, wb_ram_instr_mem_bus_stb, wb_ram_instr_mem_bus_we, wb_ram_instr_mem_bus_dat_r, wb_ram_instr_mem_bus_ack, wb_ram_data_mem_bus_dat_w, wb_ram_data_mem_bus_bte, wb_ram_data_mem_bus_sel, wb_ram_data_mem_bus_cyc, wb_ram_data_mem_bus_cti, wb_ram_data_mem_bus_adr, wb_ram_data_mem_bus_stb, wb_ram_data_mem_bus_we, wb_ram_data_mem_bus_dat_r, wb_ram_data_mem_bus_ack +, wb_uart_csr_wishbone_dat_w, wb_uart_csr_wishbone_bte, wb_uart_csr_wishbone_sel, wb_uart_csr_wishbone_cyc, wb_uart_csr_wishbone_cti, wb_uart_csr_wishbone_adr, wb_uart_csr_wishbone_stb, wb_uart_csr_wishbone_we, wb_uart_csr_wishbone_dat_r, wb_uart_csr_wishbone_ack, vexriscv_iBusWishbone_dat_r, vexriscv_iBusWishbone_ack, vexriscv_iBusWishbone_err, vexriscv_iBusWishbone_dat_w, vexriscv_iBusWishbone_bte, vexriscv_iBusWishbone_sel, vexriscv_iBusWishbone_cyc, vexriscv_iBusWishbone_cti, vexriscv_iBusWishbone_adr, vexriscv_iBusWishbone_stb, vexriscv_iBusWishbone_we +, vexriscv_dBusWishbone_dat_r, vexriscv_dBusWishbone_ack, vexriscv_dBusWishbone_err, vexriscv_dBusWishbone_dat_w, vexriscv_dBusWishbone_bte, vexriscv_dBusWishbone_sel, vexriscv_dBusWishbone_cyc, vexriscv_dBusWishbone_cti, vexriscv_dBusWishbone_adr, vexriscv_dBusWishbone_stb, vexriscv_dBusWishbone_we, clk); + wire \U$$0_interconnect0_clk ; + wire \U$$0_interconnect0_rst ; + wire \U$$0_vexriscv_dBusWishbone__ack ; + wire [29:0] \U$$0_vexriscv_dBusWishbone__adr ; + wire [1:0] \U$$0_vexriscv_dBusWishbone__bte ; + wire [2:0] \U$$0_vexriscv_dBusWishbone__cti ; + wire \U$$0_vexriscv_dBusWishbone__cyc ; + wire [31:0] \U$$0_vexriscv_dBusWishbone__dat_r ; + wire [31:0] \U$$0_vexriscv_dBusWishbone__dat_w ; + wire \U$$0_vexriscv_dBusWishbone__err ; + wire [3:0] \U$$0_vexriscv_dBusWishbone__sel ; + wire \U$$0_vexriscv_dBusWishbone__stb ; + wire \U$$0_vexriscv_dBusWishbone__we ; + wire \U$$0_vexriscv_iBusWishbone__ack ; + wire [29:0] \U$$0_vexriscv_iBusWishbone__adr ; + wire [1:0] \U$$0_vexriscv_iBusWishbone__bte ; + wire [2:0] \U$$0_vexriscv_iBusWishbone__cti ; + wire \U$$0_vexriscv_iBusWishbone__cyc ; + wire [31:0] \U$$0_vexriscv_iBusWishbone__dat_r ; + wire [31:0] \U$$0_vexriscv_iBusWishbone__dat_w ; + wire \U$$0_vexriscv_iBusWishbone__err ; + wire [3:0] \U$$0_vexriscv_iBusWishbone__sel ; + wire \U$$0_vexriscv_iBusWishbone__stb ; + wire \U$$0_vexriscv_iBusWishbone__we ; + wire \U$$0_wb_ram_data_mem_bus__ack ; + wire [11:0] \U$$0_wb_ram_data_mem_bus__adr ; + wire [1:0] \U$$0_wb_ram_data_mem_bus__bte ; + wire [2:0] \U$$0_wb_ram_data_mem_bus__cti ; + wire \U$$0_wb_ram_data_mem_bus__cyc ; + wire [31:0] \U$$0_wb_ram_data_mem_bus__dat_r ; + wire [31:0] \U$$0_wb_ram_data_mem_bus__dat_w ; + wire \U$$0_wb_ram_data_mem_bus__err ; + wire [3:0] \U$$0_wb_ram_data_mem_bus__sel ; + wire \U$$0_wb_ram_data_mem_bus__stb ; + wire \U$$0_wb_ram_data_mem_bus__we ; + wire \U$$0_wb_ram_instr_mem_bus__ack ; + wire [15:0] \U$$0_wb_ram_instr_mem_bus__adr ; + wire [1:0] \U$$0_wb_ram_instr_mem_bus__bte ; + wire [2:0] \U$$0_wb_ram_instr_mem_bus__cti ; + wire \U$$0_wb_ram_instr_mem_bus__cyc ; + wire [31:0] \U$$0_wb_ram_instr_mem_bus__dat_r ; + wire [31:0] \U$$0_wb_ram_instr_mem_bus__dat_w ; + wire \U$$0_wb_ram_instr_mem_bus__err ; + wire [3:0] \U$$0_wb_ram_instr_mem_bus__sel ; + wire \U$$0_wb_ram_instr_mem_bus__stb ; + wire \U$$0_wb_ram_instr_mem_bus__we ; + wire \U$$0_wb_uart_csr_wishbone__ack ; + wire [11:0] \U$$0_wb_uart_csr_wishbone__adr ; + wire [1:0] \U$$0_wb_uart_csr_wishbone__bte ; + wire [2:0] \U$$0_wb_uart_csr_wishbone__cti ; + wire \U$$0_wb_uart_csr_wishbone__cyc ; + wire [31:0] \U$$0_wb_uart_csr_wishbone__dat_r ; + wire [31:0] \U$$0_wb_uart_csr_wishbone__dat_w ; + wire \U$$0_wb_uart_csr_wishbone__err ; + wire [3:0] \U$$0_wb_uart_csr_wishbone__sel ; + wire \U$$0_wb_uart_csr_wishbone__stb ; + wire \U$$0_wb_uart_csr_wishbone__we ; + input clk; + wire clk; + input rst; + wire rst; + output vexriscv_dBusWishbone_ack; + wire vexriscv_dBusWishbone_ack; + input [29:0] vexriscv_dBusWishbone_adr; + wire [29:0] vexriscv_dBusWishbone_adr; + input [1:0] vexriscv_dBusWishbone_bte; + wire [1:0] vexriscv_dBusWishbone_bte; + input [2:0] vexriscv_dBusWishbone_cti; + wire [2:0] vexriscv_dBusWishbone_cti; + input vexriscv_dBusWishbone_cyc; + wire vexriscv_dBusWishbone_cyc; + output [31:0] vexriscv_dBusWishbone_dat_r; + wire [31:0] vexriscv_dBusWishbone_dat_r; + input [31:0] vexriscv_dBusWishbone_dat_w; + wire [31:0] vexriscv_dBusWishbone_dat_w; + output vexriscv_dBusWishbone_err; + wire vexriscv_dBusWishbone_err; + input [3:0] vexriscv_dBusWishbone_sel; + wire [3:0] vexriscv_dBusWishbone_sel; + input vexriscv_dBusWishbone_stb; + wire vexriscv_dBusWishbone_stb; + input vexriscv_dBusWishbone_we; + wire vexriscv_dBusWishbone_we; + output vexriscv_iBusWishbone_ack; + wire vexriscv_iBusWishbone_ack; + input [29:0] vexriscv_iBusWishbone_adr; + wire [29:0] vexriscv_iBusWishbone_adr; + input [1:0] vexriscv_iBusWishbone_bte; + wire [1:0] vexriscv_iBusWishbone_bte; + input [2:0] vexriscv_iBusWishbone_cti; + wire [2:0] vexriscv_iBusWishbone_cti; + input vexriscv_iBusWishbone_cyc; + wire vexriscv_iBusWishbone_cyc; + output [31:0] vexriscv_iBusWishbone_dat_r; + wire [31:0] vexriscv_iBusWishbone_dat_r; + input [31:0] vexriscv_iBusWishbone_dat_w; + wire [31:0] vexriscv_iBusWishbone_dat_w; + output vexriscv_iBusWishbone_err; + wire vexriscv_iBusWishbone_err; + input [3:0] vexriscv_iBusWishbone_sel; + wire [3:0] vexriscv_iBusWishbone_sel; + input vexriscv_iBusWishbone_stb; + wire vexriscv_iBusWishbone_stb; + input vexriscv_iBusWishbone_we; + wire vexriscv_iBusWishbone_we; + input wb_ram_data_mem_bus_ack; + wire wb_ram_data_mem_bus_ack; + output [11:0] wb_ram_data_mem_bus_adr; + wire [11:0] wb_ram_data_mem_bus_adr; + output [1:0] wb_ram_data_mem_bus_bte; + wire [1:0] wb_ram_data_mem_bus_bte; + output [2:0] wb_ram_data_mem_bus_cti; + wire [2:0] wb_ram_data_mem_bus_cti; + output wb_ram_data_mem_bus_cyc; + wire wb_ram_data_mem_bus_cyc; + input [31:0] wb_ram_data_mem_bus_dat_r; + wire [31:0] wb_ram_data_mem_bus_dat_r; + output [31:0] wb_ram_data_mem_bus_dat_w; + wire [31:0] wb_ram_data_mem_bus_dat_w; + wire wb_ram_data_mem_bus_err; + output [3:0] wb_ram_data_mem_bus_sel; + wire [3:0] wb_ram_data_mem_bus_sel; + output wb_ram_data_mem_bus_stb; + wire wb_ram_data_mem_bus_stb; + output wb_ram_data_mem_bus_we; + wire wb_ram_data_mem_bus_we; + input wb_ram_instr_mem_bus_ack; + wire wb_ram_instr_mem_bus_ack; + output [15:0] wb_ram_instr_mem_bus_adr; + wire [15:0] wb_ram_instr_mem_bus_adr; + output [1:0] wb_ram_instr_mem_bus_bte; + wire [1:0] wb_ram_instr_mem_bus_bte; + output [2:0] wb_ram_instr_mem_bus_cti; + wire [2:0] wb_ram_instr_mem_bus_cti; + output wb_ram_instr_mem_bus_cyc; + wire wb_ram_instr_mem_bus_cyc; + input [31:0] wb_ram_instr_mem_bus_dat_r; + wire [31:0] wb_ram_instr_mem_bus_dat_r; + output [31:0] wb_ram_instr_mem_bus_dat_w; + wire [31:0] wb_ram_instr_mem_bus_dat_w; + wire wb_ram_instr_mem_bus_err; + output [3:0] wb_ram_instr_mem_bus_sel; + wire [3:0] wb_ram_instr_mem_bus_sel; + output wb_ram_instr_mem_bus_stb; + wire wb_ram_instr_mem_bus_stb; + output wb_ram_instr_mem_bus_we; + wire wb_ram_instr_mem_bus_we; + input wb_uart_csr_wishbone_ack; + wire wb_uart_csr_wishbone_ack; + output [11:0] wb_uart_csr_wishbone_adr; + wire [11:0] wb_uart_csr_wishbone_adr; + output [1:0] wb_uart_csr_wishbone_bte; + wire [1:0] wb_uart_csr_wishbone_bte; + output [2:0] wb_uart_csr_wishbone_cti; + wire [2:0] wb_uart_csr_wishbone_cti; + output wb_uart_csr_wishbone_cyc; + wire wb_uart_csr_wishbone_cyc; + input [31:0] wb_uart_csr_wishbone_dat_r; + wire [31:0] wb_uart_csr_wishbone_dat_r; + output [31:0] wb_uart_csr_wishbone_dat_w; + wire [31:0] wb_uart_csr_wishbone_dat_w; + wire wb_uart_csr_wishbone_err; + output [3:0] wb_uart_csr_wishbone_sel; + wire [3:0] wb_uart_csr_wishbone_sel; + output wb_uart_csr_wishbone_stb; + wire wb_uart_csr_wishbone_stb; + output wb_uart_csr_wishbone_we; + wire wb_uart_csr_wishbone_we; + \simple_soc.interconnect0.U$$0 \U$$0 ( + .interconnect0_clk(\U$$0_interconnect0_clk ), + .interconnect0_rst(\U$$0_interconnect0_rst ), + .vexriscv_dBusWishbone__ack(\U$$0_vexriscv_dBusWishbone__ack ), + .vexriscv_dBusWishbone__adr(\U$$0_vexriscv_dBusWishbone__adr ), + .vexriscv_dBusWishbone__bte(\U$$0_vexriscv_dBusWishbone__bte ), + .vexriscv_dBusWishbone__cti(\U$$0_vexriscv_dBusWishbone__cti ), + .vexriscv_dBusWishbone__cyc(\U$$0_vexriscv_dBusWishbone__cyc ), + .vexriscv_dBusWishbone__dat_r(\U$$0_vexriscv_dBusWishbone__dat_r ), + .vexriscv_dBusWishbone__dat_w(\U$$0_vexriscv_dBusWishbone__dat_w ), + .vexriscv_dBusWishbone__err(\U$$0_vexriscv_dBusWishbone__err ), + .vexriscv_dBusWishbone__sel(\U$$0_vexriscv_dBusWishbone__sel ), + .vexriscv_dBusWishbone__stb(\U$$0_vexriscv_dBusWishbone__stb ), + .vexriscv_dBusWishbone__we(\U$$0_vexriscv_dBusWishbone__we ), + .vexriscv_iBusWishbone__ack(\U$$0_vexriscv_iBusWishbone__ack ), + .vexriscv_iBusWishbone__adr(\U$$0_vexriscv_iBusWishbone__adr ), + .vexriscv_iBusWishbone__bte(\U$$0_vexriscv_iBusWishbone__bte ), + .vexriscv_iBusWishbone__cti(\U$$0_vexriscv_iBusWishbone__cti ), + .vexriscv_iBusWishbone__cyc(\U$$0_vexriscv_iBusWishbone__cyc ), + .vexriscv_iBusWishbone__dat_r(\U$$0_vexriscv_iBusWishbone__dat_r ), + .vexriscv_iBusWishbone__dat_w(\U$$0_vexriscv_iBusWishbone__dat_w ), + .vexriscv_iBusWishbone__err(\U$$0_vexriscv_iBusWishbone__err ), + .vexriscv_iBusWishbone__sel(\U$$0_vexriscv_iBusWishbone__sel ), + .vexriscv_iBusWishbone__stb(\U$$0_vexriscv_iBusWishbone__stb ), + .vexriscv_iBusWishbone__we(\U$$0_vexriscv_iBusWishbone__we ), + .wb_ram_data_mem_bus__ack(\U$$0_wb_ram_data_mem_bus__ack ), + .wb_ram_data_mem_bus__adr(\U$$0_wb_ram_data_mem_bus__adr ), + .wb_ram_data_mem_bus__bte(\U$$0_wb_ram_data_mem_bus__bte ), + .wb_ram_data_mem_bus__cti(\U$$0_wb_ram_data_mem_bus__cti ), + .wb_ram_data_mem_bus__cyc(\U$$0_wb_ram_data_mem_bus__cyc ), + .wb_ram_data_mem_bus__dat_r(\U$$0_wb_ram_data_mem_bus__dat_r ), + .wb_ram_data_mem_bus__dat_w(\U$$0_wb_ram_data_mem_bus__dat_w ), + .wb_ram_data_mem_bus__err(1'h0), + .wb_ram_data_mem_bus__sel(\U$$0_wb_ram_data_mem_bus__sel ), + .wb_ram_data_mem_bus__stb(\U$$0_wb_ram_data_mem_bus__stb ), + .wb_ram_data_mem_bus__we(\U$$0_wb_ram_data_mem_bus__we ), + .wb_ram_instr_mem_bus__ack(\U$$0_wb_ram_instr_mem_bus__ack ), + .wb_ram_instr_mem_bus__adr(\U$$0_wb_ram_instr_mem_bus__adr ), + .wb_ram_instr_mem_bus__bte(\U$$0_wb_ram_instr_mem_bus__bte ), + .wb_ram_instr_mem_bus__cti(\U$$0_wb_ram_instr_mem_bus__cti ), + .wb_ram_instr_mem_bus__cyc(\U$$0_wb_ram_instr_mem_bus__cyc ), + .wb_ram_instr_mem_bus__dat_r(\U$$0_wb_ram_instr_mem_bus__dat_r ), + .wb_ram_instr_mem_bus__dat_w(\U$$0_wb_ram_instr_mem_bus__dat_w ), + .wb_ram_instr_mem_bus__err(1'h0), + .wb_ram_instr_mem_bus__sel(\U$$0_wb_ram_instr_mem_bus__sel ), + .wb_ram_instr_mem_bus__stb(\U$$0_wb_ram_instr_mem_bus__stb ), + .wb_ram_instr_mem_bus__we(\U$$0_wb_ram_instr_mem_bus__we ), + .wb_uart_csr_wishbone__ack(\U$$0_wb_uart_csr_wishbone__ack ), + .wb_uart_csr_wishbone__adr(\U$$0_wb_uart_csr_wishbone__adr ), + .wb_uart_csr_wishbone__bte(\U$$0_wb_uart_csr_wishbone__bte ), + .wb_uart_csr_wishbone__cti(\U$$0_wb_uart_csr_wishbone__cti ), + .wb_uart_csr_wishbone__cyc(\U$$0_wb_uart_csr_wishbone__cyc ), + .wb_uart_csr_wishbone__dat_r(\U$$0_wb_uart_csr_wishbone__dat_r ), + .wb_uart_csr_wishbone__dat_w(\U$$0_wb_uart_csr_wishbone__dat_w ), + .wb_uart_csr_wishbone__err(1'h0), + .wb_uart_csr_wishbone__sel(\U$$0_wb_uart_csr_wishbone__sel ), + .wb_uart_csr_wishbone__stb(\U$$0_wb_uart_csr_wishbone__stb ), + .wb_uart_csr_wishbone__we(\U$$0_wb_uart_csr_wishbone__we ) + ); + assign wb_ram_instr_mem_bus_err = 1'h0; + assign wb_ram_data_mem_bus_err = 1'h0; + assign wb_uart_csr_wishbone_err = 1'h0; + assign \U$$0_vexriscv_dBusWishbone__bte = vexriscv_dBusWishbone_bte; + assign \U$$0_vexriscv_dBusWishbone__cti = vexriscv_dBusWishbone_cti; + assign vexriscv_dBusWishbone_err = \U$$0_vexriscv_dBusWishbone__err ; + assign vexriscv_dBusWishbone_ack = \U$$0_vexriscv_dBusWishbone__ack ; + assign \U$$0_vexriscv_dBusWishbone__we = vexriscv_dBusWishbone_we; + assign \U$$0_vexriscv_dBusWishbone__stb = vexriscv_dBusWishbone_stb; + assign \U$$0_vexriscv_dBusWishbone__cyc = vexriscv_dBusWishbone_cyc; + assign \U$$0_vexriscv_dBusWishbone__sel = vexriscv_dBusWishbone_sel; + assign vexriscv_dBusWishbone_dat_r = \U$$0_vexriscv_dBusWishbone__dat_r ; + assign \U$$0_vexriscv_dBusWishbone__dat_w = vexriscv_dBusWishbone_dat_w; + assign \U$$0_vexriscv_dBusWishbone__adr = vexriscv_dBusWishbone_adr; + assign \U$$0_vexriscv_iBusWishbone__bte = vexriscv_iBusWishbone_bte; + assign \U$$0_vexriscv_iBusWishbone__cti = vexriscv_iBusWishbone_cti; + assign vexriscv_iBusWishbone_err = \U$$0_vexriscv_iBusWishbone__err ; + assign vexriscv_iBusWishbone_ack = \U$$0_vexriscv_iBusWishbone__ack ; + assign \U$$0_vexriscv_iBusWishbone__we = vexriscv_iBusWishbone_we; + assign \U$$0_vexriscv_iBusWishbone__stb = vexriscv_iBusWishbone_stb; + assign \U$$0_vexriscv_iBusWishbone__cyc = vexriscv_iBusWishbone_cyc; + assign \U$$0_vexriscv_iBusWishbone__sel = vexriscv_iBusWishbone_sel; + assign vexriscv_iBusWishbone_dat_r = \U$$0_vexriscv_iBusWishbone__dat_r ; + assign \U$$0_vexriscv_iBusWishbone__dat_w = vexriscv_iBusWishbone_dat_w; + assign \U$$0_vexriscv_iBusWishbone__adr = vexriscv_iBusWishbone_adr; + assign wb_uart_csr_wishbone_bte = \U$$0_wb_uart_csr_wishbone__bte ; + assign wb_uart_csr_wishbone_cti = \U$$0_wb_uart_csr_wishbone__cti ; + assign \U$$0_wb_uart_csr_wishbone__err = 1'h0; + assign \U$$0_wb_uart_csr_wishbone__ack = wb_uart_csr_wishbone_ack; + assign wb_uart_csr_wishbone_we = \U$$0_wb_uart_csr_wishbone__we ; + assign wb_uart_csr_wishbone_stb = \U$$0_wb_uart_csr_wishbone__stb ; + assign wb_uart_csr_wishbone_cyc = \U$$0_wb_uart_csr_wishbone__cyc ; + assign wb_uart_csr_wishbone_sel = \U$$0_wb_uart_csr_wishbone__sel ; + assign \U$$0_wb_uart_csr_wishbone__dat_r = wb_uart_csr_wishbone_dat_r; + assign wb_uart_csr_wishbone_dat_w = \U$$0_wb_uart_csr_wishbone__dat_w ; + assign wb_uart_csr_wishbone_adr = \U$$0_wb_uart_csr_wishbone__adr ; + assign wb_ram_data_mem_bus_bte = \U$$0_wb_ram_data_mem_bus__bte ; + assign wb_ram_data_mem_bus_cti = \U$$0_wb_ram_data_mem_bus__cti ; + assign \U$$0_wb_ram_data_mem_bus__err = 1'h0; + assign \U$$0_wb_ram_data_mem_bus__ack = wb_ram_data_mem_bus_ack; + assign wb_ram_data_mem_bus_we = \U$$0_wb_ram_data_mem_bus__we ; + assign wb_ram_data_mem_bus_stb = \U$$0_wb_ram_data_mem_bus__stb ; + assign wb_ram_data_mem_bus_cyc = \U$$0_wb_ram_data_mem_bus__cyc ; + assign wb_ram_data_mem_bus_sel = \U$$0_wb_ram_data_mem_bus__sel ; + assign \U$$0_wb_ram_data_mem_bus__dat_r = wb_ram_data_mem_bus_dat_r; + assign wb_ram_data_mem_bus_dat_w = \U$$0_wb_ram_data_mem_bus__dat_w ; + assign wb_ram_data_mem_bus_adr = \U$$0_wb_ram_data_mem_bus__adr ; + assign wb_ram_instr_mem_bus_bte = \U$$0_wb_ram_instr_mem_bus__bte ; + assign wb_ram_instr_mem_bus_cti = \U$$0_wb_ram_instr_mem_bus__cti ; + assign \U$$0_wb_ram_instr_mem_bus__err = 1'h0; + assign \U$$0_wb_ram_instr_mem_bus__ack = wb_ram_instr_mem_bus_ack; + assign wb_ram_instr_mem_bus_we = \U$$0_wb_ram_instr_mem_bus__we ; + assign wb_ram_instr_mem_bus_stb = \U$$0_wb_ram_instr_mem_bus__stb ; + assign wb_ram_instr_mem_bus_cyc = \U$$0_wb_ram_instr_mem_bus__cyc ; + assign wb_ram_instr_mem_bus_sel = \U$$0_wb_ram_instr_mem_bus__sel ; + assign \U$$0_wb_ram_instr_mem_bus__dat_r = wb_ram_instr_mem_bus_dat_r; + assign wb_ram_instr_mem_bus_dat_w = \U$$0_wb_ram_instr_mem_bus__dat_w ; + assign wb_ram_instr_mem_bus_adr = \U$$0_wb_ram_instr_mem_bus__adr ; + assign \U$$0_interconnect0_rst = rst; + assign \U$$0_interconnect0_clk = clk; +endmodule +module \simple_soc.interconnect0.U$$0 (interconnect0_rst, wb_ram_instr_mem_bus__adr, wb_ram_instr_mem_bus__dat_w, wb_ram_instr_mem_bus__dat_r, wb_ram_instr_mem_bus__sel, wb_ram_instr_mem_bus__cyc, wb_ram_instr_mem_bus__stb, wb_ram_instr_mem_bus__we, wb_ram_instr_mem_bus__ack, wb_ram_instr_mem_bus__err, wb_ram_instr_mem_bus__cti, wb_ram_instr_mem_bus__bte, wb_ram_data_mem_bus__adr, wb_ram_data_mem_bus__dat_w, wb_ram_data_mem_bus__dat_r, wb_ram_data_mem_bus__sel, wb_ram_data_mem_bus__cyc, wb_ram_data_mem_bus__stb, wb_ram_data_mem_bus__we, wb_ram_data_mem_bus__ack, wb_ram_data_mem_bus__err +, wb_ram_data_mem_bus__cti, wb_ram_data_mem_bus__bte, wb_uart_csr_wishbone__adr, wb_uart_csr_wishbone__dat_w, wb_uart_csr_wishbone__dat_r, wb_uart_csr_wishbone__sel, wb_uart_csr_wishbone__cyc, wb_uart_csr_wishbone__stb, wb_uart_csr_wishbone__we, wb_uart_csr_wishbone__ack, wb_uart_csr_wishbone__err, wb_uart_csr_wishbone__cti, wb_uart_csr_wishbone__bte, vexriscv_iBusWishbone__adr, vexriscv_iBusWishbone__dat_w, vexriscv_iBusWishbone__dat_r, vexriscv_iBusWishbone__sel, vexriscv_iBusWishbone__cyc, vexriscv_iBusWishbone__stb, vexriscv_iBusWishbone__we, vexriscv_iBusWishbone__ack +, vexriscv_iBusWishbone__err, vexriscv_iBusWishbone__cti, vexriscv_iBusWishbone__bte, vexriscv_dBusWishbone__adr, vexriscv_dBusWishbone__dat_w, vexriscv_dBusWishbone__dat_r, vexriscv_dBusWishbone__sel, vexriscv_dBusWishbone__cyc, vexriscv_dBusWishbone__stb, vexriscv_dBusWishbone__we, vexriscv_dBusWishbone__ack, vexriscv_dBusWishbone__err, vexriscv_dBusWishbone__cti, vexriscv_dBusWishbone__bte, interconnect0_clk); + wire arbiter_bus__ack; + wire [29:0] arbiter_bus__adr; + wire [1:0] arbiter_bus__bte; + wire [2:0] arbiter_bus__cti; + wire arbiter_bus__cyc; + wire [31:0] arbiter_bus__dat_r; + wire [31:0] arbiter_bus__dat_w; + wire arbiter_bus__err; + wire [3:0] arbiter_bus__sel; + wire arbiter_bus__stb; + wire arbiter_bus__we; + wire decoder_bus__ack; + wire [29:0] decoder_bus__adr; + wire [1:0] decoder_bus__bte; + wire [2:0] decoder_bus__cti; + wire decoder_bus__cyc; + wire [31:0] decoder_bus__dat_r; + wire [31:0] decoder_bus__dat_w; + wire decoder_bus__err; + wire [3:0] decoder_bus__sel; + wire decoder_bus__stb; + wire decoder_bus__we; + input interconnect0_clk; + wire interconnect0_clk; + input interconnect0_rst; + wire interconnect0_rst; + output vexriscv_dBusWishbone__ack; + wire vexriscv_dBusWishbone__ack; + input [29:0] vexriscv_dBusWishbone__adr; + wire [29:0] vexriscv_dBusWishbone__adr; + input [1:0] vexriscv_dBusWishbone__bte; + wire [1:0] vexriscv_dBusWishbone__bte; + input [2:0] vexriscv_dBusWishbone__cti; + wire [2:0] vexriscv_dBusWishbone__cti; + input vexriscv_dBusWishbone__cyc; + wire vexriscv_dBusWishbone__cyc; + output [31:0] vexriscv_dBusWishbone__dat_r; + wire [31:0] vexriscv_dBusWishbone__dat_r; + input [31:0] vexriscv_dBusWishbone__dat_w; + wire [31:0] vexriscv_dBusWishbone__dat_w; + output vexriscv_dBusWishbone__err; + wire vexriscv_dBusWishbone__err; + input [3:0] vexriscv_dBusWishbone__sel; + wire [3:0] vexriscv_dBusWishbone__sel; + input vexriscv_dBusWishbone__stb; + wire vexriscv_dBusWishbone__stb; + input vexriscv_dBusWishbone__we; + wire vexriscv_dBusWishbone__we; + output vexriscv_iBusWishbone__ack; + wire vexriscv_iBusWishbone__ack; + input [29:0] vexriscv_iBusWishbone__adr; + wire [29:0] vexriscv_iBusWishbone__adr; + input [1:0] vexriscv_iBusWishbone__bte; + wire [1:0] vexriscv_iBusWishbone__bte; + input [2:0] vexriscv_iBusWishbone__cti; + wire [2:0] vexriscv_iBusWishbone__cti; + input vexriscv_iBusWishbone__cyc; + wire vexriscv_iBusWishbone__cyc; + output [31:0] vexriscv_iBusWishbone__dat_r; + wire [31:0] vexriscv_iBusWishbone__dat_r; + input [31:0] vexriscv_iBusWishbone__dat_w; + wire [31:0] vexriscv_iBusWishbone__dat_w; + output vexriscv_iBusWishbone__err; + wire vexriscv_iBusWishbone__err; + input [3:0] vexriscv_iBusWishbone__sel; + wire [3:0] vexriscv_iBusWishbone__sel; + input vexriscv_iBusWishbone__stb; + wire vexriscv_iBusWishbone__stb; + input vexriscv_iBusWishbone__we; + wire vexriscv_iBusWishbone__we; + input wb_ram_data_mem_bus__ack; + wire wb_ram_data_mem_bus__ack; + output [11:0] wb_ram_data_mem_bus__adr; + wire [11:0] wb_ram_data_mem_bus__adr; + output [1:0] wb_ram_data_mem_bus__bte; + wire [1:0] wb_ram_data_mem_bus__bte; + output [2:0] wb_ram_data_mem_bus__cti; + wire [2:0] wb_ram_data_mem_bus__cti; + output wb_ram_data_mem_bus__cyc; + wire wb_ram_data_mem_bus__cyc; + input [31:0] wb_ram_data_mem_bus__dat_r; + wire [31:0] wb_ram_data_mem_bus__dat_r; + output [31:0] wb_ram_data_mem_bus__dat_w; + wire [31:0] wb_ram_data_mem_bus__dat_w; + input wb_ram_data_mem_bus__err; + wire wb_ram_data_mem_bus__err; + output [3:0] wb_ram_data_mem_bus__sel; + wire [3:0] wb_ram_data_mem_bus__sel; + output wb_ram_data_mem_bus__stb; + wire wb_ram_data_mem_bus__stb; + output wb_ram_data_mem_bus__we; + wire wb_ram_data_mem_bus__we; + input wb_ram_instr_mem_bus__ack; + wire wb_ram_instr_mem_bus__ack; + output [15:0] wb_ram_instr_mem_bus__adr; + wire [15:0] wb_ram_instr_mem_bus__adr; + output [1:0] wb_ram_instr_mem_bus__bte; + wire [1:0] wb_ram_instr_mem_bus__bte; + output [2:0] wb_ram_instr_mem_bus__cti; + wire [2:0] wb_ram_instr_mem_bus__cti; + output wb_ram_instr_mem_bus__cyc; + wire wb_ram_instr_mem_bus__cyc; + input [31:0] wb_ram_instr_mem_bus__dat_r; + wire [31:0] wb_ram_instr_mem_bus__dat_r; + output [31:0] wb_ram_instr_mem_bus__dat_w; + wire [31:0] wb_ram_instr_mem_bus__dat_w; + input wb_ram_instr_mem_bus__err; + wire wb_ram_instr_mem_bus__err; + output [3:0] wb_ram_instr_mem_bus__sel; + wire [3:0] wb_ram_instr_mem_bus__sel; + output wb_ram_instr_mem_bus__stb; + wire wb_ram_instr_mem_bus__stb; + output wb_ram_instr_mem_bus__we; + wire wb_ram_instr_mem_bus__we; + input wb_uart_csr_wishbone__ack; + wire wb_uart_csr_wishbone__ack; + output [11:0] wb_uart_csr_wishbone__adr; + wire [11:0] wb_uart_csr_wishbone__adr; + output [1:0] wb_uart_csr_wishbone__bte; + wire [1:0] wb_uart_csr_wishbone__bte; + output [2:0] wb_uart_csr_wishbone__cti; + wire [2:0] wb_uart_csr_wishbone__cti; + output wb_uart_csr_wishbone__cyc; + wire wb_uart_csr_wishbone__cyc; + input [31:0] wb_uart_csr_wishbone__dat_r; + wire [31:0] wb_uart_csr_wishbone__dat_r; + output [31:0] wb_uart_csr_wishbone__dat_w; + wire [31:0] wb_uart_csr_wishbone__dat_w; + input wb_uart_csr_wishbone__err; + wire wb_uart_csr_wishbone__err; + output [3:0] wb_uart_csr_wishbone__sel; + wire [3:0] wb_uart_csr_wishbone__sel; + output wb_uart_csr_wishbone__stb; + wire wb_uart_csr_wishbone__stb; + output wb_uart_csr_wishbone__we; + wire wb_uart_csr_wishbone__we; + \simple_soc.interconnect0.U$$0.arbiter arbiter ( + .bus__ack(arbiter_bus__ack), + .bus__adr(arbiter_bus__adr), + .bus__bte(arbiter_bus__bte), + .bus__cti(arbiter_bus__cti), + .bus__cyc(arbiter_bus__cyc), + .bus__dat_r(arbiter_bus__dat_r), + .bus__dat_w(arbiter_bus__dat_w), + .bus__err(arbiter_bus__err), + .bus__sel(arbiter_bus__sel), + .bus__stb(arbiter_bus__stb), + .bus__we(arbiter_bus__we), + .interconnect0_clk(interconnect0_clk), + .interconnect0_rst(interconnect0_rst), + .vexriscv_dBusWishbone__ack(vexriscv_dBusWishbone__ack), + .vexriscv_dBusWishbone__adr(vexriscv_dBusWishbone__adr), + .vexriscv_dBusWishbone__bte(vexriscv_dBusWishbone__bte), + .vexriscv_dBusWishbone__cti(vexriscv_dBusWishbone__cti), + .vexriscv_dBusWishbone__cyc(vexriscv_dBusWishbone__cyc), + .vexriscv_dBusWishbone__dat_r(vexriscv_dBusWishbone__dat_r), + .vexriscv_dBusWishbone__dat_w(vexriscv_dBusWishbone__dat_w), + .vexriscv_dBusWishbone__err(vexriscv_dBusWishbone__err), + .vexriscv_dBusWishbone__sel(vexriscv_dBusWishbone__sel), + .vexriscv_dBusWishbone__stb(vexriscv_dBusWishbone__stb), + .vexriscv_dBusWishbone__we(vexriscv_dBusWishbone__we), + .vexriscv_iBusWishbone__ack(vexriscv_iBusWishbone__ack), + .vexriscv_iBusWishbone__adr(vexriscv_iBusWishbone__adr), + .vexriscv_iBusWishbone__bte(vexriscv_iBusWishbone__bte), + .vexriscv_iBusWishbone__cti(vexriscv_iBusWishbone__cti), + .vexriscv_iBusWishbone__cyc(vexriscv_iBusWishbone__cyc), + .vexriscv_iBusWishbone__dat_r(vexriscv_iBusWishbone__dat_r), + .vexriscv_iBusWishbone__dat_w(vexriscv_iBusWishbone__dat_w), + .vexriscv_iBusWishbone__err(vexriscv_iBusWishbone__err), + .vexriscv_iBusWishbone__sel(vexriscv_iBusWishbone__sel), + .vexriscv_iBusWishbone__stb(vexriscv_iBusWishbone__stb), + .vexriscv_iBusWishbone__we(vexriscv_iBusWishbone__we) + ); + \simple_soc.interconnect0.U$$0.decoder decoder ( + .bus__ack(decoder_bus__ack), + .bus__adr(decoder_bus__adr), + .bus__bte(decoder_bus__bte), + .bus__cti(decoder_bus__cti), + .bus__cyc(decoder_bus__cyc), + .bus__dat_r(decoder_bus__dat_r), + .bus__dat_w(decoder_bus__dat_w), + .bus__err(decoder_bus__err), + .bus__sel(decoder_bus__sel), + .bus__stb(decoder_bus__stb), + .bus__we(decoder_bus__we), + .wb_ram_data_mem_bus__ack(wb_ram_data_mem_bus__ack), + .wb_ram_data_mem_bus__adr(wb_ram_data_mem_bus__adr), + .wb_ram_data_mem_bus__bte(wb_ram_data_mem_bus__bte), + .wb_ram_data_mem_bus__cti(wb_ram_data_mem_bus__cti), + .wb_ram_data_mem_bus__cyc(wb_ram_data_mem_bus__cyc), + .wb_ram_data_mem_bus__dat_r(wb_ram_data_mem_bus__dat_r), + .wb_ram_data_mem_bus__dat_w(wb_ram_data_mem_bus__dat_w), + .wb_ram_data_mem_bus__err(wb_ram_data_mem_bus__err), + .wb_ram_data_mem_bus__sel(wb_ram_data_mem_bus__sel), + .wb_ram_data_mem_bus__stb(wb_ram_data_mem_bus__stb), + .wb_ram_data_mem_bus__we(wb_ram_data_mem_bus__we), + .wb_ram_instr_mem_bus__ack(wb_ram_instr_mem_bus__ack), + .wb_ram_instr_mem_bus__adr(wb_ram_instr_mem_bus__adr), + .wb_ram_instr_mem_bus__bte(wb_ram_instr_mem_bus__bte), + .wb_ram_instr_mem_bus__cti(wb_ram_instr_mem_bus__cti), + .wb_ram_instr_mem_bus__cyc(wb_ram_instr_mem_bus__cyc), + .wb_ram_instr_mem_bus__dat_r(wb_ram_instr_mem_bus__dat_r), + .wb_ram_instr_mem_bus__dat_w(wb_ram_instr_mem_bus__dat_w), + .wb_ram_instr_mem_bus__err(wb_ram_instr_mem_bus__err), + .wb_ram_instr_mem_bus__sel(wb_ram_instr_mem_bus__sel), + .wb_ram_instr_mem_bus__stb(wb_ram_instr_mem_bus__stb), + .wb_ram_instr_mem_bus__we(wb_ram_instr_mem_bus__we), + .wb_uart_csr_wishbone__ack(wb_uart_csr_wishbone__ack), + .wb_uart_csr_wishbone__adr(wb_uart_csr_wishbone__adr), + .wb_uart_csr_wishbone__bte(wb_uart_csr_wishbone__bte), + .wb_uart_csr_wishbone__cti(wb_uart_csr_wishbone__cti), + .wb_uart_csr_wishbone__cyc(wb_uart_csr_wishbone__cyc), + .wb_uart_csr_wishbone__dat_r(wb_uart_csr_wishbone__dat_r), + .wb_uart_csr_wishbone__dat_w(wb_uart_csr_wishbone__dat_w), + .wb_uart_csr_wishbone__err(wb_uart_csr_wishbone__err), + .wb_uart_csr_wishbone__sel(wb_uart_csr_wishbone__sel), + .wb_uart_csr_wishbone__stb(wb_uart_csr_wishbone__stb), + .wb_uart_csr_wishbone__we(wb_uart_csr_wishbone__we) + ); + assign decoder_bus__we = arbiter_bus__we; + assign decoder_bus__stb = arbiter_bus__stb; + assign decoder_bus__sel = arbiter_bus__sel; + assign arbiter_bus__err = decoder_bus__err; + assign decoder_bus__dat_w = arbiter_bus__dat_w; + assign arbiter_bus__dat_r = decoder_bus__dat_r; + assign decoder_bus__cyc = arbiter_bus__cyc; + assign decoder_bus__cti = arbiter_bus__cti; + assign decoder_bus__bte = arbiter_bus__bte; + assign decoder_bus__adr = arbiter_bus__adr; + assign arbiter_bus__ack = decoder_bus__ack; +endmodule +module \simple_soc.interconnect0.U$$0.arbiter (interconnect0_rst, vexriscv_iBusWishbone__adr, vexriscv_iBusWishbone__dat_w, vexriscv_iBusWishbone__dat_r, vexriscv_iBusWishbone__sel, vexriscv_iBusWishbone__cyc, vexriscv_iBusWishbone__stb, vexriscv_iBusWishbone__we, vexriscv_iBusWishbone__ack, vexriscv_iBusWishbone__err, vexriscv_iBusWishbone__cti, vexriscv_iBusWishbone__bte, vexriscv_dBusWishbone__adr, vexriscv_dBusWishbone__dat_w, vexriscv_dBusWishbone__dat_r, vexriscv_dBusWishbone__sel, vexriscv_dBusWishbone__cyc, vexriscv_dBusWishbone__stb, vexriscv_dBusWishbone__we, vexriscv_dBusWishbone__ack, vexriscv_dBusWishbone__err +, vexriscv_dBusWishbone__cti, vexriscv_dBusWishbone__bte, bus__ack, bus__adr, bus__bte, bus__cti, bus__cyc, bus__dat_r, bus__dat_w, bus__err, bus__sel, bus__stb, bus__we, interconnect0_clk); + reg \$auto$verilog_backend.cc:2253:dump_module$1 = 0; + wire \$1 ; + input bus__ack; + wire bus__ack; + output [29:0] bus__adr; + reg [29:0] bus__adr; + output [1:0] bus__bte; + reg [1:0] bus__bte; + output [2:0] bus__cti; + reg [2:0] bus__cti; + output bus__cyc; + reg bus__cyc; + input [31:0] bus__dat_r; + wire [31:0] bus__dat_r; + output [31:0] bus__dat_w; + reg [31:0] bus__dat_w; + input bus__err; + wire bus__err; + output [3:0] bus__sel; + reg [3:0] bus__sel; + output bus__stb; + reg bus__stb; + output bus__we; + reg bus__we; + reg grant = 1'h0; + reg \grant$next ; + input interconnect0_clk; + wire interconnect0_clk; + input interconnect0_rst; + wire interconnect0_rst; + wire [1:0] requests; + output vexriscv_dBusWishbone__ack; + reg vexriscv_dBusWishbone__ack; + input [29:0] vexriscv_dBusWishbone__adr; + wire [29:0] vexriscv_dBusWishbone__adr; + input [1:0] vexriscv_dBusWishbone__bte; + wire [1:0] vexriscv_dBusWishbone__bte; + input [2:0] vexriscv_dBusWishbone__cti; + wire [2:0] vexriscv_dBusWishbone__cti; + input vexriscv_dBusWishbone__cyc; + wire vexriscv_dBusWishbone__cyc; + output [31:0] vexriscv_dBusWishbone__dat_r; + wire [31:0] vexriscv_dBusWishbone__dat_r; + input [31:0] vexriscv_dBusWishbone__dat_w; + wire [31:0] vexriscv_dBusWishbone__dat_w; + output vexriscv_dBusWishbone__err; + reg vexriscv_dBusWishbone__err; + input [3:0] vexriscv_dBusWishbone__sel; + wire [3:0] vexriscv_dBusWishbone__sel; + input vexriscv_dBusWishbone__stb; + wire vexriscv_dBusWishbone__stb; + input vexriscv_dBusWishbone__we; + wire vexriscv_dBusWishbone__we; + output vexriscv_iBusWishbone__ack; + reg vexriscv_iBusWishbone__ack; + input [29:0] vexriscv_iBusWishbone__adr; + wire [29:0] vexriscv_iBusWishbone__adr; + input [1:0] vexriscv_iBusWishbone__bte; + wire [1:0] vexriscv_iBusWishbone__bte; + input [2:0] vexriscv_iBusWishbone__cti; + wire [2:0] vexriscv_iBusWishbone__cti; + input vexriscv_iBusWishbone__cyc; + wire vexriscv_iBusWishbone__cyc; + output [31:0] vexriscv_iBusWishbone__dat_r; + wire [31:0] vexriscv_iBusWishbone__dat_r; + input [31:0] vexriscv_iBusWishbone__dat_w; + wire [31:0] vexriscv_iBusWishbone__dat_w; + output vexriscv_iBusWishbone__err; + reg vexriscv_iBusWishbone__err; + input [3:0] vexriscv_iBusWishbone__sel; + wire [3:0] vexriscv_iBusWishbone__sel; + input vexriscv_iBusWishbone__stb; + wire vexriscv_iBusWishbone__stb; + input vexriscv_iBusWishbone__we; + wire vexriscv_iBusWishbone__we; + assign \$1 = ~bus__cyc; + always @(posedge interconnect0_clk) + grant <= \grant$next ; + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + \grant$next = grant; + if (\$1 ) + casez (grant) + 1'h0: + if (requests[1]) + \grant$next = 1'h1; + 1'h1: + if (requests[0]) + \grant$next = 1'h0; + endcase + if (interconnect0_rst) + \grant$next = 1'h0; + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + casez (grant) + 1'h0: + bus__cti = vexriscv_iBusWishbone__cti; + 1'h1: + bus__cti = vexriscv_dBusWishbone__cti; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + casez (grant) + 1'h0: + bus__bte = vexriscv_iBusWishbone__bte; + 1'h1: + bus__bte = vexriscv_dBusWishbone__bte; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + vexriscv_iBusWishbone__ack = 1'h0; + casez (grant) + 1'h0: + vexriscv_iBusWishbone__ack = bus__ack; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + vexriscv_iBusWishbone__err = 1'h0; + casez (grant) + 1'h0: + vexriscv_iBusWishbone__err = bus__err; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + vexriscv_dBusWishbone__ack = 1'h0; + casez (grant) + 1'h0: + /* empty */; + 1'h1: + vexriscv_dBusWishbone__ack = bus__ack; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + vexriscv_dBusWishbone__err = 1'h0; + casez (grant) + 1'h0: + /* empty */; + 1'h1: + vexriscv_dBusWishbone__err = bus__err; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + casez (grant) + 1'h0: + bus__adr = vexriscv_iBusWishbone__adr; + 1'h1: + bus__adr = vexriscv_dBusWishbone__adr; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + casez (grant) + 1'h0: + bus__dat_w = vexriscv_iBusWishbone__dat_w; + 1'h1: + bus__dat_w = vexriscv_dBusWishbone__dat_w; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + casez (grant) + 1'h0: + bus__sel = vexriscv_iBusWishbone__sel; + 1'h1: + bus__sel = vexriscv_dBusWishbone__sel; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + casez (grant) + 1'h0: + bus__we = vexriscv_iBusWishbone__we; + 1'h1: + bus__we = vexriscv_dBusWishbone__we; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + casez (grant) + 1'h0: + bus__stb = vexriscv_iBusWishbone__stb; + 1'h1: + bus__stb = vexriscv_dBusWishbone__stb; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$1 ) begin end + casez (grant) + 1'h0: + bus__cyc = vexriscv_iBusWishbone__cyc; + 1'h1: + bus__cyc = vexriscv_dBusWishbone__cyc; + endcase + end + assign vexriscv_dBusWishbone__dat_r = bus__dat_r; + assign vexriscv_iBusWishbone__dat_r = bus__dat_r; + assign requests = { vexriscv_dBusWishbone__cyc, vexriscv_iBusWishbone__cyc }; +endmodule +module \simple_soc.interconnect0.U$$0.decoder (wb_ram_instr_mem_bus__dat_w, wb_ram_instr_mem_bus__dat_r, wb_ram_instr_mem_bus__sel, wb_ram_instr_mem_bus__cyc, wb_ram_instr_mem_bus__stb, wb_ram_instr_mem_bus__we, wb_ram_instr_mem_bus__ack, wb_ram_instr_mem_bus__err, wb_ram_instr_mem_bus__cti, wb_ram_instr_mem_bus__bte, wb_ram_data_mem_bus__adr, wb_ram_data_mem_bus__dat_w, wb_ram_data_mem_bus__dat_r, wb_ram_data_mem_bus__sel, wb_ram_data_mem_bus__cyc, wb_ram_data_mem_bus__stb, wb_ram_data_mem_bus__we, wb_ram_data_mem_bus__ack, wb_ram_data_mem_bus__err, wb_ram_data_mem_bus__cti, wb_ram_data_mem_bus__bte +, wb_uart_csr_wishbone__adr, wb_uart_csr_wishbone__dat_w, wb_uart_csr_wishbone__dat_r, wb_uart_csr_wishbone__sel, wb_uart_csr_wishbone__cyc, wb_uart_csr_wishbone__stb, wb_uart_csr_wishbone__we, wb_uart_csr_wishbone__ack, wb_uart_csr_wishbone__err, wb_uart_csr_wishbone__cti, wb_uart_csr_wishbone__bte, bus__ack, bus__adr, bus__bte, bus__cti, bus__cyc, bus__dat_r, bus__dat_w, bus__err, bus__sel, bus__stb +, bus__we, wb_ram_instr_mem_bus__adr); + reg \$auto$verilog_backend.cc:2253:dump_module$2 = 0; + wire [30:0] \$1 ; + wire \$10 ; + wire \$12 ; + wire \$14 ; + wire \$16 ; + wire \$18 ; + wire [30:0] \$2 ; + wire \$20 ; + wire [30:0] \$4 ; + wire [30:0] \$5 ; + wire [30:0] \$7 ; + wire [30:0] \$8 ; + output bus__ack; + wire bus__ack; + input [29:0] bus__adr; + wire [29:0] bus__adr; + input [1:0] bus__bte; + wire [1:0] bus__bte; + input [2:0] bus__cti; + wire [2:0] bus__cti; + input bus__cyc; + wire bus__cyc; + output [31:0] bus__dat_r; + reg [31:0] bus__dat_r; + input [31:0] bus__dat_w; + wire [31:0] bus__dat_w; + output bus__err; + wire bus__err; + input [3:0] bus__sel; + wire [3:0] bus__sel; + input bus__stb; + wire bus__stb; + input bus__we; + wire bus__we; + input wb_ram_data_mem_bus__ack; + wire wb_ram_data_mem_bus__ack; + output [11:0] wb_ram_data_mem_bus__adr; + wire [11:0] wb_ram_data_mem_bus__adr; + output [1:0] wb_ram_data_mem_bus__bte; + wire [1:0] wb_ram_data_mem_bus__bte; + output [2:0] wb_ram_data_mem_bus__cti; + wire [2:0] wb_ram_data_mem_bus__cti; + output wb_ram_data_mem_bus__cyc; + reg wb_ram_data_mem_bus__cyc; + input [31:0] wb_ram_data_mem_bus__dat_r; + wire [31:0] wb_ram_data_mem_bus__dat_r; + output [31:0] wb_ram_data_mem_bus__dat_w; + wire [31:0] wb_ram_data_mem_bus__dat_w; + input wb_ram_data_mem_bus__err; + wire wb_ram_data_mem_bus__err; + output [3:0] wb_ram_data_mem_bus__sel; + wire [3:0] wb_ram_data_mem_bus__sel; + output wb_ram_data_mem_bus__stb; + wire wb_ram_data_mem_bus__stb; + output wb_ram_data_mem_bus__we; + wire wb_ram_data_mem_bus__we; + input wb_ram_instr_mem_bus__ack; + wire wb_ram_instr_mem_bus__ack; + output [15:0] wb_ram_instr_mem_bus__adr; + wire [15:0] wb_ram_instr_mem_bus__adr; + output [1:0] wb_ram_instr_mem_bus__bte; + wire [1:0] wb_ram_instr_mem_bus__bte; + output [2:0] wb_ram_instr_mem_bus__cti; + wire [2:0] wb_ram_instr_mem_bus__cti; + output wb_ram_instr_mem_bus__cyc; + reg wb_ram_instr_mem_bus__cyc; + input [31:0] wb_ram_instr_mem_bus__dat_r; + wire [31:0] wb_ram_instr_mem_bus__dat_r; + output [31:0] wb_ram_instr_mem_bus__dat_w; + wire [31:0] wb_ram_instr_mem_bus__dat_w; + input wb_ram_instr_mem_bus__err; + wire wb_ram_instr_mem_bus__err; + output [3:0] wb_ram_instr_mem_bus__sel; + wire [3:0] wb_ram_instr_mem_bus__sel; + output wb_ram_instr_mem_bus__stb; + wire wb_ram_instr_mem_bus__stb; + output wb_ram_instr_mem_bus__we; + wire wb_ram_instr_mem_bus__we; + input wb_uart_csr_wishbone__ack; + wire wb_uart_csr_wishbone__ack; + output [11:0] wb_uart_csr_wishbone__adr; + wire [11:0] wb_uart_csr_wishbone__adr; + output [1:0] wb_uart_csr_wishbone__bte; + wire [1:0] wb_uart_csr_wishbone__bte; + output [2:0] wb_uart_csr_wishbone__cti; + wire [2:0] wb_uart_csr_wishbone__cti; + output wb_uart_csr_wishbone__cyc; + reg wb_uart_csr_wishbone__cyc; + input [31:0] wb_uart_csr_wishbone__dat_r; + wire [31:0] wb_uart_csr_wishbone__dat_r; + output [31:0] wb_uart_csr_wishbone__dat_w; + wire [31:0] wb_uart_csr_wishbone__dat_w; + input wb_uart_csr_wishbone__err; + wire wb_uart_csr_wishbone__err; + output [3:0] wb_uart_csr_wishbone__sel; + wire [3:0] wb_uart_csr_wishbone__sel; + output wb_uart_csr_wishbone__stb; + wire wb_uart_csr_wishbone__stb; + output wb_uart_csr_wishbone__we; + wire wb_uart_csr_wishbone__we; + assign \$12 = \$10 | wb_ram_data_mem_bus__ack; + assign \$14 = \$12 | wb_uart_csr_wishbone__ack; + assign \$18 = \$16 | wb_ram_data_mem_bus__err; + assign \$20 = \$18 | wb_uart_csr_wishbone__err; + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$2 ) begin end + wb_ram_instr_mem_bus__cyc = 1'h0; + casez (bus__adr) + 30'h0000????: + wb_ram_instr_mem_bus__cyc = bus__cyc; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$2 ) begin end + bus__dat_r = 32'd0; + casez (bus__adr) + 30'h0000????: + bus__dat_r = wb_ram_instr_mem_bus__dat_r; + 30'h04000???: + bus__dat_r = wb_ram_data_mem_bus__dat_r; + 30'h3c000???: + bus__dat_r = wb_uart_csr_wishbone__dat_r; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$2 ) begin end + wb_ram_data_mem_bus__cyc = 1'h0; + casez (bus__adr) + 30'h0000????: + /* empty */; + 30'h04000???: + wb_ram_data_mem_bus__cyc = bus__cyc; + endcase + end + always @* begin + if (\$auto$verilog_backend.cc:2253:dump_module$2 ) begin end + wb_uart_csr_wishbone__cyc = 1'h0; + casez (bus__adr) + 30'h0000????: + /* empty */; + 30'h04000???: + /* empty */; + 30'h3c000???: + wb_uart_csr_wishbone__cyc = bus__cyc; + endcase + end + assign \$1 = \$2 ; + assign \$4 = \$5 ; + assign \$7 = \$8 ; + assign bus__err = \$20 ; + assign bus__ack = \$14 ; + assign wb_uart_csr_wishbone__bte = bus__bte; + assign wb_uart_csr_wishbone__cti = bus__cti; + assign wb_uart_csr_wishbone__stb = bus__stb; + assign wb_uart_csr_wishbone__we = bus__we; + assign wb_uart_csr_wishbone__sel = bus__sel; + assign wb_uart_csr_wishbone__dat_w = bus__dat_w; + assign wb_uart_csr_wishbone__adr = \$8 [11:0]; + assign wb_ram_data_mem_bus__bte = bus__bte; + assign wb_ram_data_mem_bus__cti = bus__cti; + assign wb_ram_data_mem_bus__stb = bus__stb; + assign wb_ram_data_mem_bus__we = bus__we; + assign wb_ram_data_mem_bus__sel = bus__sel; + assign wb_ram_data_mem_bus__dat_w = bus__dat_w; + assign wb_ram_data_mem_bus__adr = \$5 [11:0]; + assign wb_ram_instr_mem_bus__bte = bus__bte; + assign wb_ram_instr_mem_bus__cti = bus__cti; + assign wb_ram_instr_mem_bus__stb = bus__stb; + assign wb_ram_instr_mem_bus__we = bus__we; + assign wb_ram_instr_mem_bus__sel = bus__sel; + assign wb_ram_instr_mem_bus__dat_w = bus__dat_w; + assign wb_ram_instr_mem_bus__adr = \$2 [15:0]; + assign \$2 = { 1'h0, bus__adr }; + assign \$5 = { 1'h0, bus__adr }; + assign \$8 = { 1'h0, bus__adr }; + assign \$10 = wb_ram_instr_mem_bus__ack; + assign \$16 = wb_ram_instr_mem_bus__err; +endmodule diff --git a/examples/soc/sources/wb_uart.v b/examples/soc/sources/wb_uart.v new file mode 100644 index 00000000..2bdbc917 --- /dev/null +++ b/examples/soc/sources/wb_uart.v @@ -0,0 +1,814 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : wb_uart.v +// Device : xc7k70tfbg484-3 +// LiteX sha1 : a064ced +// Date : 2024-04-18 14:06:41 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module wb_uart ( + input wire sys_clk, + input wire sys_rst, + output reg serial1_tx, + input wire serial1_rx, + input wire [29:0] csr_wishbone_adr, + input wire [31:0] csr_wishbone_mosi, + output reg [31:0] csr_wishbone_miso, + input wire [3:0] csr_wishbone_sel, + input wire csr_wishbone_cyc, + input wire csr_wishbone_stb, + output reg csr_wishbone_ack, + input wire csr_wishbone_we, + input wire [2:0] csr_wishbone_cti, + input wire [1:0] csr_wishbone_bte, + input wire csr_wishbone_err +); + + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire tx_sink_valid; +reg tx_sink_ready = 1'd0; +wire tx_sink_first; +wire tx_sink_last; +wire [7:0] tx_sink_payload_data; +reg [7:0] tx_data = 8'd0; +reg [3:0] tx_count = 4'd0; +reg tx_enable = 1'd0; +reg tx_tick = 1'd0; +reg [31:0] tx_phase = 32'd0; +reg rx_source_valid = 1'd0; +wire rx_source_ready; +reg rx_source_first = 1'd0; +reg rx_source_last = 1'd0; +reg [7:0] rx_source_payload_data = 8'd0; +reg [7:0] rx_data = 8'd0; +reg [3:0] rx_count = 4'd0; +reg rx_enable = 1'd0; +reg rx_tick = 1'd0; +reg [31:0] rx_phase = 32'd0; +wire rx_rx; +reg rx_rx_d = 1'd0; +reg rxtx_re = 1'd0; +wire [7:0] rxtx_r; +reg rxtx_we = 1'd0; +wire [7:0] rxtx_w; +wire txfull_status; +wire txfull_we0; +reg txfull_re0 = 1'd0; +wire rxempty_status; +wire rxempty_we0; +reg rxempty_re0 = 1'd0; +wire irq; +wire tx_status; +reg tx_pending = 1'd0; +wire tx_trigger; +reg tx_clear = 1'd0; +reg tx_trigger_d = 1'd0; +wire rx_status; +reg rx_pending = 1'd0; +wire rx_trigger; +reg rx_clear = 1'd0; +reg rx_trigger_d = 1'd0; +wire tx0; +wire rx0; +reg [1:0] status_status = 2'd0; +wire status_we; +reg status_re = 1'd0; +wire tx1; +wire rx1; +reg [1:0] pending_status = 2'd0; +wire pending_we; +reg pending_re = 1'd0; +reg [1:0] pending_r = 2'd0; +wire tx2; +wire rx2; +reg [1:0] enable_storage = 2'd0; +reg enable_re = 1'd0; +wire txempty_status; +wire txempty_we0; +reg txempty_re0 = 1'd0; +wire rxfull_status; +wire rxfull_we0; +reg rxfull_re0 = 1'd0; +wire uart_sink_valid; +wire uart_sink_ready; +wire uart_sink_first; +wire uart_sink_last; +wire [7:0] uart_sink_payload_data; +wire uart_source_valid; +wire uart_source_ready; +wire uart_source_first; +wire uart_source_last; +wire [7:0] uart_source_payload_data; +wire tx_fifo_sink_valid; +wire tx_fifo_sink_ready; +reg tx_fifo_sink_first = 1'd0; +reg tx_fifo_sink_last = 1'd0; +wire [7:0] tx_fifo_sink_payload_data; +wire tx_fifo_source_valid; +wire tx_fifo_source_ready; +wire tx_fifo_source_first; +wire tx_fifo_source_last; +wire [7:0] tx_fifo_source_payload_data; +wire tx_fifo_re; +reg tx_fifo_readable = 1'd0; +wire tx_fifo_syncfifo_we; +wire tx_fifo_syncfifo_writable; +wire tx_fifo_syncfifo_re; +wire tx_fifo_syncfifo_readable; +wire [9:0] tx_fifo_syncfifo_din; +wire [9:0] tx_fifo_syncfifo_dout; +reg [4:0] tx_fifo_level0 = 5'd0; +reg tx_fifo_replace = 1'd0; +reg [3:0] tx_fifo_produce = 4'd0; +reg [3:0] tx_fifo_consume = 4'd0; +reg [3:0] tx_fifo_wrport_adr = 4'd0; +wire [9:0] tx_fifo_wrport_dat_r; +wire tx_fifo_wrport_we; +wire [9:0] tx_fifo_wrport_dat_w; +wire tx_fifo_do_read; +wire [3:0] tx_fifo_rdport_adr; +wire [9:0] tx_fifo_rdport_dat_r; +wire tx_fifo_rdport_re; +wire [4:0] tx_fifo_level1; +wire [7:0] tx_fifo_fifo_in_payload_data; +wire tx_fifo_fifo_in_first; +wire tx_fifo_fifo_in_last; +wire [7:0] tx_fifo_fifo_out_payload_data; +wire tx_fifo_fifo_out_first; +wire tx_fifo_fifo_out_last; +wire rx_fifo_sink_valid; +wire rx_fifo_sink_ready; +wire rx_fifo_sink_first; +wire rx_fifo_sink_last; +wire [7:0] rx_fifo_sink_payload_data; +wire rx_fifo_source_valid; +wire rx_fifo_source_ready; +wire rx_fifo_source_first; +wire rx_fifo_source_last; +wire [7:0] rx_fifo_source_payload_data; +wire rx_fifo_re; +reg rx_fifo_readable = 1'd0; +wire rx_fifo_syncfifo_we; +wire rx_fifo_syncfifo_writable; +wire rx_fifo_syncfifo_re; +wire rx_fifo_syncfifo_readable; +wire [9:0] rx_fifo_syncfifo_din; +wire [9:0] rx_fifo_syncfifo_dout; +reg [4:0] rx_fifo_level0 = 5'd0; +reg rx_fifo_replace = 1'd0; +reg [3:0] rx_fifo_produce = 4'd0; +reg [3:0] rx_fifo_consume = 4'd0; +reg [3:0] rx_fifo_wrport_adr = 4'd0; +wire [9:0] rx_fifo_wrport_dat_r; +wire rx_fifo_wrport_we; +wire [9:0] rx_fifo_wrport_dat_w; +wire rx_fifo_do_read; +wire [3:0] rx_fifo_rdport_adr; +wire [9:0] rx_fifo_rdport_dat_r; +wire rx_fifo_rdport_re; +wire [4:0] rx_fifo_level1; +wire [7:0] rx_fifo_fifo_in_payload_data; +wire rx_fifo_fifo_in_first; +wire rx_fifo_fifo_in_last; +wire [7:0] rx_fifo_fifo_out_payload_data; +wire rx_fifo_fifo_out_first; +wire rx_fifo_fifo_out_last; +reg [13:0] csr_master_adr = 14'd0; +reg csr_master_we = 1'd0; +reg [7:0] csr_master_dat_w = 8'd0; +wire [7:0] csr_master_dat_r; +wire [13:0] bank_bus_adr; +wire bank_bus_we; +wire [7:0] bank_bus_dat_w; +reg [7:0] bank_bus_dat_r = 8'd0; +reg txfull_re1 = 1'd0; +wire txfull_r; +reg txfull_we1 = 1'd0; +wire txfull_w; +reg rxempty_re1 = 1'd0; +wire rxempty_r; +reg rxempty_we1 = 1'd0; +wire rxempty_w; +reg ev_status_re = 1'd0; +wire [1:0] ev_status_r; +reg ev_status_we = 1'd0; +wire [1:0] ev_status_w; +reg ev_pending_re = 1'd0; +wire [1:0] ev_pending_r; +reg ev_pending_we = 1'd0; +wire [1:0] ev_pending_w; +reg ev_enable0_re = 1'd0; +wire [1:0] ev_enable0_r; +reg ev_enable0_we = 1'd0; +wire [1:0] ev_enable0_w; +reg txempty_re1 = 1'd0; +wire txempty_r; +reg txempty_we1 = 1'd0; +wire txempty_w; +reg rxfull_re1 = 1'd0; +wire rxfull_r; +reg rxfull_we1 = 1'd0; +wire rxfull_w; +wire sel; +reg rs232phytx_state = 1'd0; +reg rs232phytx_next_state = 1'd0; +reg [3:0] tx_count_rs232phytx_next_value0 = 4'd0; +reg tx_count_rs232phytx_next_value_ce0 = 1'd0; +reg serial1_tx_rs232phytx_next_value1 = 1'd0; +reg serial1_tx_rs232phytx_next_value_ce1 = 1'd0; +reg [7:0] tx_data_rs232phytx_next_value2 = 8'd0; +reg tx_data_rs232phytx_next_value_ce2 = 1'd0; +reg rs232phyrx_state = 1'd0; +reg rs232phyrx_next_state = 1'd0; +reg [3:0] rx_count_rs232phyrx_next_value0 = 4'd0; +reg rx_count_rs232phyrx_next_value_ce0 = 1'd0; +reg [7:0] rx_data_rs232phyrx_next_value1 = 8'd0; +reg rx_data_rs232phyrx_next_value_ce1 = 1'd0; +reg [1:0] state = 2'd0; +reg [1:0] next_state = 2'd0; +reg [7:0] csr_master_dat_w_next_value0 = 8'd0; +reg csr_master_dat_w_next_value_ce0 = 1'd0; +reg [13:0] csr_master_adr_next_value1 = 14'd0; +reg csr_master_adr_next_value_ce1 = 1'd0; +reg csr_master_we_next_value2 = 1'd0; +reg csr_master_we_next_value_ce2 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg regs1 = 1'd0; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +always @(*) begin + rs232phytx_next_state = 1'd0; + tx_enable = 1'd0; + tx_count_rs232phytx_next_value0 = 4'd0; + tx_count_rs232phytx_next_value_ce0 = 1'd0; + serial1_tx_rs232phytx_next_value1 = 1'd0; + serial1_tx_rs232phytx_next_value_ce1 = 1'd0; + tx_data_rs232phytx_next_value2 = 8'd0; + tx_data_rs232phytx_next_value_ce2 = 1'd0; + tx_sink_ready = 1'd0; + rs232phytx_next_state = rs232phytx_state; + case (rs232phytx_state) + 1'd1: begin + tx_enable = 1'd1; + if (tx_tick) begin + serial1_tx_rs232phytx_next_value1 = tx_data; + serial1_tx_rs232phytx_next_value_ce1 = 1'd1; + tx_count_rs232phytx_next_value0 = (tx_count + 1'd1); + tx_count_rs232phytx_next_value_ce0 = 1'd1; + tx_data_rs232phytx_next_value2 = {1'd1, tx_data[7:1]}; + tx_data_rs232phytx_next_value_ce2 = 1'd1; + if ((tx_count == 4'd9)) begin + tx_sink_ready = 1'd1; + rs232phytx_next_state = 1'd0; + end + end + end + default: begin + tx_count_rs232phytx_next_value0 = 1'd0; + tx_count_rs232phytx_next_value_ce0 = 1'd1; + serial1_tx_rs232phytx_next_value1 = 1'd1; + serial1_tx_rs232phytx_next_value_ce1 = 1'd1; + if (tx_sink_valid) begin + serial1_tx_rs232phytx_next_value1 = 1'd0; + serial1_tx_rs232phytx_next_value_ce1 = 1'd1; + tx_data_rs232phytx_next_value2 = tx_sink_payload_data; + tx_data_rs232phytx_next_value_ce2 = 1'd1; + rs232phytx_next_state = 1'd1; + end + end + endcase +end +always @(*) begin + rx_source_payload_data = 8'd0; + rx_enable = 1'd0; + rs232phyrx_next_state = 1'd0; + rx_count_rs232phyrx_next_value0 = 4'd0; + rx_count_rs232phyrx_next_value_ce0 = 1'd0; + rx_data_rs232phyrx_next_value1 = 8'd0; + rx_data_rs232phyrx_next_value_ce1 = 1'd0; + rx_source_valid = 1'd0; + rs232phyrx_next_state = rs232phyrx_state; + case (rs232phyrx_state) + 1'd1: begin + rx_enable = 1'd1; + if (rx_tick) begin + rx_count_rs232phyrx_next_value0 = (rx_count + 1'd1); + rx_count_rs232phyrx_next_value_ce0 = 1'd1; + rx_data_rs232phyrx_next_value1 = {rx_rx, rx_data[7:1]}; + rx_data_rs232phyrx_next_value_ce1 = 1'd1; + if ((rx_count == 4'd9)) begin + rx_source_valid = (rx_rx == 1'd1); + rx_source_payload_data = rx_data; + rs232phyrx_next_state = 1'd0; + end + end + end + default: begin + rx_count_rs232phyrx_next_value0 = 1'd0; + rx_count_rs232phyrx_next_value_ce0 = 1'd1; + if (((rx_rx == 1'd0) & (rx_rx_d == 1'd1))) begin + rs232phyrx_next_state = 1'd1; + end + end + endcase +end +assign uart_sink_valid = rx_source_valid; +assign rx_source_ready = uart_sink_ready; +assign uart_sink_first = rx_source_first; +assign uart_sink_last = rx_source_last; +assign uart_sink_payload_data = rx_source_payload_data; +assign tx_sink_valid = uart_source_valid; +assign uart_source_ready = tx_sink_ready; +assign tx_sink_first = uart_source_first; +assign tx_sink_last = uart_source_last; +assign tx_sink_payload_data = uart_source_payload_data; +assign tx_fifo_sink_valid = rxtx_re; +assign tx_fifo_sink_payload_data = rxtx_r; +assign uart_source_valid = tx_fifo_source_valid; +assign tx_fifo_source_ready = uart_source_ready; +assign uart_source_first = tx_fifo_source_first; +assign uart_source_last = tx_fifo_source_last; +assign uart_source_payload_data = tx_fifo_source_payload_data; +assign txfull_status = (~tx_fifo_sink_ready); +assign txempty_status = (~tx_fifo_source_valid); +assign tx_trigger = tx_fifo_sink_ready; +assign rx_fifo_sink_valid = uart_sink_valid; +assign uart_sink_ready = rx_fifo_sink_ready; +assign rx_fifo_sink_first = uart_sink_first; +assign rx_fifo_sink_last = uart_sink_last; +assign rx_fifo_sink_payload_data = uart_sink_payload_data; +assign rxtx_w = rx_fifo_source_payload_data; +assign rx_fifo_source_ready = (rx_clear | (1'd0 & rxtx_we)); +assign rxempty_status = (~rx_fifo_source_valid); +assign rxfull_status = (~rx_fifo_sink_ready); +assign rx_trigger = rx_fifo_source_valid; +assign tx0 = tx_status; +assign tx1 = tx_pending; +always @(*) begin + tx_clear = 1'd0; + if ((pending_re & pending_r[0])) begin + tx_clear = 1'd1; + end +end +assign rx0 = rx_status; +assign rx1 = rx_pending; +always @(*) begin + rx_clear = 1'd0; + if ((pending_re & pending_r[1])) begin + rx_clear = 1'd1; + end +end +assign irq = ((pending_status[0] & enable_storage[0]) | (pending_status[1] & enable_storage[1])); +assign tx_status = tx_trigger; +assign rx_status = rx_trigger; +assign tx_fifo_syncfifo_din = {tx_fifo_fifo_in_last, tx_fifo_fifo_in_first, tx_fifo_fifo_in_payload_data}; +assign {tx_fifo_fifo_out_last, tx_fifo_fifo_out_first, tx_fifo_fifo_out_payload_data} = tx_fifo_syncfifo_dout; +assign tx_fifo_sink_ready = tx_fifo_syncfifo_writable; +assign tx_fifo_syncfifo_we = tx_fifo_sink_valid; +assign tx_fifo_fifo_in_first = tx_fifo_sink_first; +assign tx_fifo_fifo_in_last = tx_fifo_sink_last; +assign tx_fifo_fifo_in_payload_data = tx_fifo_sink_payload_data; +assign tx_fifo_source_valid = tx_fifo_readable; +assign tx_fifo_source_first = tx_fifo_fifo_out_first; +assign tx_fifo_source_last = tx_fifo_fifo_out_last; +assign tx_fifo_source_payload_data = tx_fifo_fifo_out_payload_data; +assign tx_fifo_re = tx_fifo_source_ready; +assign tx_fifo_syncfifo_re = (tx_fifo_syncfifo_readable & ((~tx_fifo_readable) | tx_fifo_re)); +assign tx_fifo_level1 = (tx_fifo_level0 + tx_fifo_readable); +always @(*) begin + tx_fifo_wrport_adr = 4'd0; + if (tx_fifo_replace) begin + tx_fifo_wrport_adr = (tx_fifo_produce - 1'd1); + end else begin + tx_fifo_wrport_adr = tx_fifo_produce; + end +end +assign tx_fifo_wrport_dat_w = tx_fifo_syncfifo_din; +assign tx_fifo_wrport_we = (tx_fifo_syncfifo_we & (tx_fifo_syncfifo_writable | tx_fifo_replace)); +assign tx_fifo_do_read = (tx_fifo_syncfifo_readable & tx_fifo_syncfifo_re); +assign tx_fifo_rdport_adr = tx_fifo_consume; +assign tx_fifo_syncfifo_dout = tx_fifo_rdport_dat_r; +assign tx_fifo_rdport_re = tx_fifo_do_read; +assign tx_fifo_syncfifo_writable = (tx_fifo_level0 != 5'd16); +assign tx_fifo_syncfifo_readable = (tx_fifo_level0 != 1'd0); +assign rx_fifo_syncfifo_din = {rx_fifo_fifo_in_last, rx_fifo_fifo_in_first, rx_fifo_fifo_in_payload_data}; +assign {rx_fifo_fifo_out_last, rx_fifo_fifo_out_first, rx_fifo_fifo_out_payload_data} = rx_fifo_syncfifo_dout; +assign rx_fifo_sink_ready = rx_fifo_syncfifo_writable; +assign rx_fifo_syncfifo_we = rx_fifo_sink_valid; +assign rx_fifo_fifo_in_first = rx_fifo_sink_first; +assign rx_fifo_fifo_in_last = rx_fifo_sink_last; +assign rx_fifo_fifo_in_payload_data = rx_fifo_sink_payload_data; +assign rx_fifo_source_valid = rx_fifo_readable; +assign rx_fifo_source_first = rx_fifo_fifo_out_first; +assign rx_fifo_source_last = rx_fifo_fifo_out_last; +assign rx_fifo_source_payload_data = rx_fifo_fifo_out_payload_data; +assign rx_fifo_re = rx_fifo_source_ready; +assign rx_fifo_syncfifo_re = (rx_fifo_syncfifo_readable & ((~rx_fifo_readable) | rx_fifo_re)); +assign rx_fifo_level1 = (rx_fifo_level0 + rx_fifo_readable); +always @(*) begin + rx_fifo_wrport_adr = 4'd0; + if (rx_fifo_replace) begin + rx_fifo_wrport_adr = (rx_fifo_produce - 1'd1); + end else begin + rx_fifo_wrport_adr = rx_fifo_produce; + end +end +assign rx_fifo_wrport_dat_w = rx_fifo_syncfifo_din; +assign rx_fifo_wrport_we = (rx_fifo_syncfifo_we & (rx_fifo_syncfifo_writable | rx_fifo_replace)); +assign rx_fifo_do_read = (rx_fifo_syncfifo_readable & rx_fifo_syncfifo_re); +assign rx_fifo_rdport_adr = rx_fifo_consume; +assign rx_fifo_syncfifo_dout = rx_fifo_rdport_dat_r; +assign rx_fifo_rdport_re = rx_fifo_do_read; +assign rx_fifo_syncfifo_writable = (rx_fifo_level0 != 5'd16); +assign rx_fifo_syncfifo_readable = (rx_fifo_level0 != 1'd0); +assign sel = (bank_bus_adr[13:7] == 1'd0); +assign rxtx_r = bank_bus_dat_w[7:0]; +always @(*) begin + rxtx_we = 1'd0; + rxtx_re = 1'd0; + if ((sel & (bank_bus_adr[6:0] == 1'd0))) begin + rxtx_re = bank_bus_we; + rxtx_we = (~bank_bus_we); + end +end +assign txfull_r = bank_bus_dat_w[0]; +always @(*) begin + txfull_re1 = 1'd0; + txfull_we1 = 1'd0; + if ((sel & (bank_bus_adr[6:0] == 1'd1))) begin + txfull_re1 = bank_bus_we; + txfull_we1 = (~bank_bus_we); + end +end +assign rxempty_r = bank_bus_dat_w[0]; +always @(*) begin + rxempty_re1 = 1'd0; + rxempty_we1 = 1'd0; + if ((sel & (bank_bus_adr[6:0] == 2'd2))) begin + rxempty_re1 = bank_bus_we; + rxempty_we1 = (~bank_bus_we); + end +end +assign ev_status_r = bank_bus_dat_w[1:0]; +always @(*) begin + ev_status_we = 1'd0; + ev_status_re = 1'd0; + if ((sel & (bank_bus_adr[6:0] == 2'd3))) begin + ev_status_re = bank_bus_we; + ev_status_we = (~bank_bus_we); + end +end +assign ev_pending_r = bank_bus_dat_w[1:0]; +always @(*) begin + ev_pending_we = 1'd0; + ev_pending_re = 1'd0; + if ((sel & (bank_bus_adr[6:0] == 3'd4))) begin + ev_pending_re = bank_bus_we; + ev_pending_we = (~bank_bus_we); + end +end +assign ev_enable0_r = bank_bus_dat_w[1:0]; +always @(*) begin + ev_enable0_re = 1'd0; + ev_enable0_we = 1'd0; + if ((sel & (bank_bus_adr[6:0] == 3'd5))) begin + ev_enable0_re = bank_bus_we; + ev_enable0_we = (~bank_bus_we); + end +end +assign txempty_r = bank_bus_dat_w[0]; +always @(*) begin + txempty_we1 = 1'd0; + txempty_re1 = 1'd0; + if ((sel & (bank_bus_adr[6:0] == 3'd6))) begin + txempty_re1 = bank_bus_we; + txempty_we1 = (~bank_bus_we); + end +end +assign rxfull_r = bank_bus_dat_w[0]; +always @(*) begin + rxfull_we1 = 1'd0; + rxfull_re1 = 1'd0; + if ((sel & (bank_bus_adr[6:0] == 3'd7))) begin + rxfull_re1 = bank_bus_we; + rxfull_we1 = (~bank_bus_we); + end +end +assign txfull_w = txfull_status; +assign txfull_we0 = txfull_we1; +assign rxempty_w = rxempty_status; +assign rxempty_we0 = rxempty_we1; +always @(*) begin + status_status = 2'd0; + status_status[0] = tx0; + status_status[1] = rx0; +end +assign ev_status_w = status_status[1:0]; +assign status_we = ev_status_we; +always @(*) begin + pending_status = 2'd0; + pending_status[0] = tx1; + pending_status[1] = rx1; +end +assign ev_pending_w = pending_status[1:0]; +assign pending_we = ev_pending_we; +assign tx2 = enable_storage[0]; +assign rx2 = enable_storage[1]; +assign ev_enable0_w = enable_storage[1:0]; +assign txempty_w = txempty_status; +assign txempty_we0 = txempty_we1; +assign rxfull_w = rxfull_status; +assign rxfull_we0 = rxfull_we1; +assign bank_bus_adr = csr_master_adr; +assign bank_bus_we = csr_master_we; +assign bank_bus_dat_w = csr_master_dat_w; +assign csr_master_dat_r = bank_bus_dat_r; +always @(*) begin + next_state = 2'd0; + csr_master_dat_w_next_value0 = 8'd0; + csr_master_dat_w_next_value_ce0 = 1'd0; + csr_master_adr_next_value1 = 14'd0; + csr_wishbone_miso = 32'd0; + csr_master_adr_next_value_ce1 = 1'd0; + csr_master_we_next_value2 = 1'd0; + csr_master_we_next_value_ce2 = 1'd0; + csr_wishbone_ack = 1'd0; + next_state = state; + case (state) + 1'd1: begin + csr_master_adr_next_value1 = 1'd0; + csr_master_adr_next_value_ce1 = 1'd1; + csr_master_we_next_value2 = 1'd0; + csr_master_we_next_value_ce2 = 1'd1; + next_state = 2'd2; + end + 2'd2: begin + csr_wishbone_ack = 1'd1; + csr_wishbone_miso = csr_master_dat_r; + next_state = 1'd0; + end + default: begin + csr_master_dat_w_next_value0 = csr_wishbone_mosi; + csr_master_dat_w_next_value_ce0 = 1'd1; + if ((csr_wishbone_cyc & csr_wishbone_stb)) begin + csr_master_adr_next_value1 = csr_wishbone_adr; + csr_master_adr_next_value_ce1 = 1'd1; + csr_master_we_next_value2 = (csr_wishbone_we & (csr_wishbone_sel != 1'd0)); + csr_master_we_next_value_ce2 = 1'd1; + next_state = 1'd1; + end + end + endcase +end +assign rx_rx = regs1; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge sys_clk) begin + {tx_tick, tx_phase} <= 23'd4947802; + if (tx_enable) begin + {tx_tick, tx_phase} <= (tx_phase + 23'd4947802); + end + rs232phytx_state <= rs232phytx_next_state; + if (tx_count_rs232phytx_next_value_ce0) begin + tx_count <= tx_count_rs232phytx_next_value0; + end + if (serial1_tx_rs232phytx_next_value_ce1) begin + serial1_tx <= serial1_tx_rs232phytx_next_value1; + end + if (tx_data_rs232phytx_next_value_ce2) begin + tx_data <= tx_data_rs232phytx_next_value2; + end + rx_rx_d <= rx_rx; + {rx_tick, rx_phase} <= 32'd2147483648; + if (rx_enable) begin + {rx_tick, rx_phase} <= (rx_phase + 23'd4947802); + end + rs232phyrx_state <= rs232phyrx_next_state; + if (rx_count_rs232phyrx_next_value_ce0) begin + rx_count <= rx_count_rs232phyrx_next_value0; + end + if (rx_data_rs232phyrx_next_value_ce1) begin + rx_data <= rx_data_rs232phyrx_next_value1; + end + if (tx_clear) begin + tx_pending <= 1'd0; + end + tx_trigger_d <= tx_trigger; + if ((tx_trigger & (~tx_trigger_d))) begin + tx_pending <= 1'd1; + end + if (rx_clear) begin + rx_pending <= 1'd0; + end + rx_trigger_d <= rx_trigger; + if ((rx_trigger & (~rx_trigger_d))) begin + rx_pending <= 1'd1; + end + if (tx_fifo_syncfifo_re) begin + tx_fifo_readable <= 1'd1; + end else begin + if (tx_fifo_re) begin + tx_fifo_readable <= 1'd0; + end + end + if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin + tx_fifo_produce <= (tx_fifo_produce + 1'd1); + end + if (tx_fifo_do_read) begin + tx_fifo_consume <= (tx_fifo_consume + 1'd1); + end + if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin + if ((~tx_fifo_do_read)) begin + tx_fifo_level0 <= (tx_fifo_level0 + 1'd1); + end + end else begin + if (tx_fifo_do_read) begin + tx_fifo_level0 <= (tx_fifo_level0 - 1'd1); + end + end + if (rx_fifo_syncfifo_re) begin + rx_fifo_readable <= 1'd1; + end else begin + if (rx_fifo_re) begin + rx_fifo_readable <= 1'd0; + end + end + if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin + rx_fifo_produce <= (rx_fifo_produce + 1'd1); + end + if (rx_fifo_do_read) begin + rx_fifo_consume <= (rx_fifo_consume + 1'd1); + end + if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin + if ((~rx_fifo_do_read)) begin + rx_fifo_level0 <= (rx_fifo_level0 + 1'd1); + end + end else begin + if (rx_fifo_do_read) begin + rx_fifo_level0 <= (rx_fifo_level0 - 1'd1); + end + end + bank_bus_dat_r <= 1'd0; + if (sel) begin + case (bank_bus_adr[6:0]) + 1'd0: begin + bank_bus_dat_r <= rxtx_w; + end + 1'd1: begin + bank_bus_dat_r <= txfull_w; + end + 2'd2: begin + bank_bus_dat_r <= rxempty_w; + end + 2'd3: begin + bank_bus_dat_r <= ev_status_w; + end + 3'd4: begin + bank_bus_dat_r <= ev_pending_w; + end + 3'd5: begin + bank_bus_dat_r <= ev_enable0_w; + end + 3'd6: begin + bank_bus_dat_r <= txempty_w; + end + 3'd7: begin + bank_bus_dat_r <= rxfull_w; + end + endcase + end + txfull_re0 <= txfull_re1; + rxempty_re0 <= rxempty_re1; + status_re <= ev_status_re; + if (ev_pending_re) begin + pending_r[1:0] <= ev_pending_r; + end + pending_re <= ev_pending_re; + if (ev_enable0_re) begin + enable_storage[1:0] <= ev_enable0_r; + end + enable_re <= ev_enable0_re; + txempty_re0 <= txempty_re1; + rxfull_re0 <= rxfull_re1; + state <= next_state; + if (csr_master_dat_w_next_value_ce0) begin + csr_master_dat_w <= csr_master_dat_w_next_value0; + end + if (csr_master_adr_next_value_ce1) begin + csr_master_adr <= csr_master_adr_next_value1; + end + if (csr_master_we_next_value_ce2) begin + csr_master_we <= csr_master_we_next_value2; + end + if (sys_rst) begin + serial1_tx <= 1'd1; + tx_tick <= 1'd0; + rx_tick <= 1'd0; + rx_rx_d <= 1'd0; + txfull_re0 <= 1'd0; + rxempty_re0 <= 1'd0; + tx_pending <= 1'd0; + tx_trigger_d <= 1'd0; + rx_pending <= 1'd0; + rx_trigger_d <= 1'd0; + status_re <= 1'd0; + pending_re <= 1'd0; + pending_r <= 2'd0; + enable_storage <= 2'd0; + enable_re <= 1'd0; + txempty_re0 <= 1'd0; + rxfull_re0 <= 1'd0; + tx_fifo_readable <= 1'd0; + tx_fifo_level0 <= 5'd0; + tx_fifo_produce <= 4'd0; + tx_fifo_consume <= 4'd0; + rx_fifo_readable <= 1'd0; + rx_fifo_level0 <= 5'd0; + rx_fifo_produce <= 4'd0; + rx_fifo_consume <= 4'd0; + csr_master_we <= 1'd0; + rs232phytx_state <= 1'd0; + rs232phyrx_state <= 1'd0; + state <= 2'd0; + end + regs0 <= serial1_rx; + regs1 <= regs0; +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory storage: 16-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage[0:15]; +reg [9:0] storage_dat0; +reg [9:0] storage_dat1; +always @(posedge sys_clk) begin + if (tx_fifo_wrport_we) + storage[tx_fifo_wrport_adr] <= tx_fifo_wrport_dat_w; + storage_dat0 <= storage[tx_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (tx_fifo_rdport_re) + storage_dat1 <= storage[tx_fifo_rdport_adr]; +end +assign tx_fifo_wrport_dat_r = storage_dat0; +assign tx_fifo_rdport_dat_r = storage_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 16-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_1[0:15]; +reg [9:0] storage_1_dat0; +reg [9:0] storage_1_dat1; +always @(posedge sys_clk) begin + if (rx_fifo_wrport_we) + storage_1[rx_fifo_wrport_adr] <= rx_fifo_wrport_dat_w; + storage_1_dat0 <= storage_1[rx_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (rx_fifo_rdport_re) + storage_1_dat1 <= storage_1[rx_fifo_rdport_adr]; +end +assign rx_fifo_wrport_dat_r = storage_1_dat0; +assign rx_fifo_rdport_dat_r = storage_1_dat1; + + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-18 14:06:41. +//------------------------------------------------------------------------------ diff --git a/examples/soc/verilator.mk b/examples/soc/verilator.mk new file mode 100644 index 00000000..e23ae743 --- /dev/null +++ b/examples/soc/verilator.mk @@ -0,0 +1,13 @@ +# Copyright 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +VERILATOR = verilator + +VERILOG_SRC = build/simple_soc.v sources/mem.v sources/VexRiscv.v sources/wb_uart.v sources/crg.v sources/wb_interconnect.v +CPP_SRC = sim.cpp + +VERILATOR_FLAGS += -cc --exe -x-assign fast -Wall --trace --assert --coverage -Wno-COMBDLY -Wno-CASEINCOMPLETE -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-TIMESCALEMOD -Wno-INITIALDLY -Wno-fatal --build --build-jobs 0 --top-module simple_soc --Mdir obj_dir +VERILATOR_INPUT = $(VERILOG_SRC) $(CPP_SRC) + +$(BUILD_DIR)/obj_dir/Vtop: $(VERILOG_SRC) + $(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_INPUT)