diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index a98124e..4ab1814 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -21,7 +21,7 @@ on: [push, pull_request] jobs: Run-tests: - runs-on: ubuntu-latest + runs-on: ubuntu-20.04 steps: diff --git a/.gitignore b/.gitignore index 56d3484..a299974 100644 --- a/.gitignore +++ b/.gitignore @@ -3,4 +3,4 @@ *.so *.swp *.log -ql-qlf-plugin/pmgen/* +/*/build diff --git a/Makefile b/Makefile index 044fe00..fc39ff4 100644 --- a/Makefile +++ b/Makefile @@ -20,6 +20,7 @@ PLUGINS_INSTALL := $(foreach plugin,$(PLUGIN_LIST),install_$(plugin)) PLUGINS_CLEAN := $(foreach plugin,$(PLUGIN_LIST),clean_$(plugin)) PLUGINS_TEST := $(foreach plugin,$(PLUGIN_LIST),test_$(plugin)) +.PHONY: all all: plugins TOP_DIR := $(realpath $(dir $(lastword $(MAKEFILE_LIST)))) @@ -29,15 +30,19 @@ ENVIRONMENT_FILE ?= environment.yml -include third_party/make-env/conda.mk define install_plugin = +.PHONY: $(1).so $(1).so: $$(MAKE) -C $(1)-plugin $$@ +.PHONY: install_$(1) install_$(1): $$(MAKE) -C $(1)-plugin install +.PHONY: clean_$(1) clean_$(1): $$(MAKE) -C $(1)-plugin clean +.PHONY: test_$(1) test_$(1): @$$(MAKE) --no-print-directory -C $(1)-plugin test endef @@ -47,21 +52,28 @@ $(foreach plugin,$(PLUGIN_LIST),$(eval $(call install_plugin,$(plugin)))) pmgen.py: wget -nc -O $@ https://raw.githubusercontent.com/YosysHQ/yosys/master/passes/pmgen/pmgen.py +.PHONY: plugins plugins: $(PLUGINS) +.PHONY: install install: $(PLUGINS_INSTALL) +.PHONY: test test: $(PLUGINS_TEST) +.PHONY: plugins_clean plugins_clean: $(PLUGINS_CLEAN) +.PHONY: clean clean:: plugins_clean rm -rf pmgen.py CLANG_FORMAT ?= clang-format-8 +.PHONY: format format: find . \( -name "*.h" -o -name "*.cc" \) -and -not -path './third_party/*' -print0 | xargs -0 -P $$(nproc) ${CLANG_FORMAT} -style=file -i VERIBLE_FORMAT ?= verible-verilog-format +.PHONY: format-verilog format-verilog: find */tests \( -name "*.v" -o -name "*.sv" \) -and -not -path './third_party/*' -print0 | xargs -0 $(VERIBLE_FORMAT) --inplace diff --git a/Makefile_plugin.common b/Makefile_plugin.common index fd6d86e..45c2640 100644 --- a/Makefile_plugin.common +++ b/Makefile_plugin.common @@ -5,6 +5,7 @@ # This shared object can be imported to Yosys with `plugin -i` command. # # Below is an example of a plugin Makefile that uses this template: +# PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) # NAME = plugin_name # SOURCES = source1.cc source2.cc # include ../Makefile_plugin.common @@ -40,6 +41,11 @@ SHELL := /usr/bin/env bash +# Directory containing this Makefile +TOP_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + +_MAKEFILES := $(abspath $(filter-out %.d,$(MAKEFILE_LIST))) + # Either find yosys in system and use its path or use the given path YOSYS_PATH ?= $(realpath $(dir $(shell command -v yosys))/..) @@ -55,35 +61,94 @@ LDFLAGS := $(shell $(YOSYS_CONFIG) --ldflags) $(LDFLAGS) LDLIBS := $(shell $(YOSYS_CONFIG) --ldlibs) $(LDLIBS) EXTRA_FLAGS ?= -DATA_DIR = $(DESTDIR)$(shell $(YOSYS_CONFIG) --datdir) -PLUGINS_DIR = $(DATA_DIR)/plugins +YOSYS_DATA_DIR = $(DESTDIR)$(shell $(YOSYS_CONFIG) --datdir) +YOSYS_PLUGINS_DIR = $(YOSYS_DATA_DIR)/plugins -OBJS := $(patsubst %.cc,%.o,$(SOURCES)) -DEPS ?= +BUILD_DIR := $(PLUGIN_DIR)/build -$(PLUGINS_DIR): - @mkdir -p $@ +# Filled below with all object file paths +_ALL_OBJECTS := +# Filled below with all build directory paths +_ALL_BUILD_SUBDIRS := + +# Default rule +.PHONY: all all: $(NAME).so -$(OBJS): %.o: %.cc $(DEPS) - $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(EXTRA_FLAGS) -c -o $@ $(filter %.cc, $^) +# Object files + +define _process-single-source-file +_source_abs := $(abspath $(addprefix $(PLUGIN_DIR)/,$(source))) +_object_abs := $(abspath $(addprefix $(BUILD_DIR)/,$(source).o)) +_object_dir := $(abspath $(dir $(_object_abs))) +_ALL_OBJECTS += $(_object_abs) +_ALL_BUILD_SUBDIRS += $(_object_dir) + +-include $(abspath $(addprefix $(BUILD_DIR)/,$(source).d)) + +$(_object_abs): TARGET_SOURCES := $(_source_abs) +$(_object_abs): $(_source_abs) | $(_object_dir) +endef +$(foreach source,$(SOURCES),$(eval $(value _process-single-source-file))) -$(NAME).so: $(OBJS) - $(CXX) $(CXXFLAGS) $(LDFLAGS) -shared -o $@ $^ $(LDLIBS) +$(_ALL_OBJECTS): $(_MAKEFILES) + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(EXTRA_FLAGS) -MMD -c -o $@ $(TARGET_SOURCES) -../pmgen.py: - @$(MAKE) -C .. pmgen.py +# Objects list for the purpose of adding extra dependencies after inclusion. +# Example use: `$(OBJECTS): $(BUILD_DIR)/some-file.h` +OBJECTS := $(_ALL_OBJECTS) -install_plugin: $(NAME).so | $(PLUGINS_DIR) - install -D $< $(PLUGINS_DIR)/$< +# Shared library +_SO_LIB := $(BUILD_DIR)/$(NAME).so +_ALL_BUILD_SUBDIRS += $(abspath $(dir $(_SO_LIB))) + +$(_SO_LIB): $(_ALL_OBJECTS) $(_MAKEFILES) | $(abspath $(dir $(_SO_LIB))) + $(CXX) $(CXXFLAGS) $(LDFLAGS) -shared -o $@ $(_ALL_OBJECTS) $(LDLIBS) + +.PHONY: $(NAME).so +$(NAME).so: $(_SO_LIB) + +# Tests + +.PHONY: test test_clean +ifneq ($(wildcard $(PLUGIN_DIR)/tests/Makefile),) test: @$(MAKE) -C tests all +test_clean: + $(MAKE) -C tests clean +else +test: +test_clean: +endif + +# Installation + +$(YOSYS_PLUGINS_DIR)/$(NAME).so: $(_SO_LIB) | $(YOSYS_PLUGINS_DIR) + install -D $(_SO_LIB) $@ + +.PHONY: install_plugin +install_plugin: $(YOSYS_PLUGINS_DIR)/$(NAME).so .PHONY: install install: install_plugin -clean: - rm -f *.d *.o *.so - $(MAKE) -C tests clean +# Cleanup + +clean: test_clean + rm -rf $(BUILD_DIR) + +# Other + +$(sort $(_ALL_BUILD_SUBDIRS)): + mkdir -p $@ + +$(YOSYS_PLUGINS_DIR): + @mkdir -p $@ + +PMGEN_PY := $(TOP_DIR)/pmgen.py + +$(PMGEN_PY): + @$(MAKE) -C $(TOP_DIR) pmgen.py + diff --git a/design_introspection-plugin/Makefile b/design_introspection-plugin/Makefile index 604254e..178d5f3 100644 --- a/design_introspection-plugin/Makefile +++ b/design_introspection-plugin/Makefile @@ -14,6 +14,8 @@ # # SPDX-License-Identifier: Apache-2.0 +PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + NAME = design_introspection SOURCES = design_introspection.cc \ get_cmd.cc \ diff --git a/dsp-ff-plugin/Makefile b/dsp-ff-plugin/Makefile index 9cd9800..0466d85 100644 --- a/dsp-ff-plugin/Makefile +++ b/dsp-ff-plugin/Makefile @@ -14,11 +14,13 @@ # # SPDX-License-Identifier: Apache-2.0 +PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + NAME = dsp-ff SOURCES = dsp_ff.cc include ../Makefile_plugin.common install: - install -D nexus-dsp_rules.txt $(DATA_DIR)/nexus/dsp_rules.txt + install -D nexus-dsp_rules.txt $(YOSYS_DATA_DIR)/nexus/dsp_rules.txt diff --git a/fasm-plugin/Makefile b/fasm-plugin/Makefile index b149198..3ce41d5 100644 --- a/fasm-plugin/Makefile +++ b/fasm-plugin/Makefile @@ -14,6 +14,8 @@ # # SPDX-License-Identifier: Apache-2.0 +PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + NAME = fasm SOURCES = fasm.cc include ../Makefile_plugin.common diff --git a/integrateinv-plugin/Makefile b/integrateinv-plugin/Makefile index f93225a..21b75ca 100644 --- a/integrateinv-plugin/Makefile +++ b/integrateinv-plugin/Makefile @@ -14,6 +14,8 @@ # # SPDX-License-Identifier: Apache-2.0 +PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + NAME = integrateinv SOURCES = integrateinv.cc include ../Makefile_plugin.common diff --git a/params-plugin/Makefile b/params-plugin/Makefile index 9740c7b..b4e2d29 100644 --- a/params-plugin/Makefile +++ b/params-plugin/Makefile @@ -14,6 +14,8 @@ # # SPDX-License-Identifier: Apache-2.0 +PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + NAME = params SOURCES = params.cc include ../Makefile_plugin.common diff --git a/ql-iob-plugin/Makefile b/ql-iob-plugin/Makefile index dc89757..4091a6a 100644 --- a/ql-iob-plugin/Makefile +++ b/ql-iob-plugin/Makefile @@ -14,6 +14,8 @@ # # SPDX-License-Identifier: Apache-2.0 +PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + NAME = ql-iob SOURCES = ql-iob.cc pcf_parser.cc pinmap_parser.cc include ../Makefile_plugin.common diff --git a/ql-qlf-plugin/Makefile b/ql-qlf-plugin/Makefile index b0411b8..d754156 100644 --- a/ql-qlf-plugin/Makefile +++ b/ql-qlf-plugin/Makefile @@ -14,6 +14,8 @@ # # SPDX-License-Identifier: Apache-2.0 +PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + NAME = ql-qlf SOURCES = synth_quicklogic.cc \ ql-dsp.cc \ @@ -26,13 +28,11 @@ SOURCES = synth_quicklogic.cc \ ql-dsp-io-regs.cc \ ql-bram-asymmetric.cc -DEPS = pmgen/ql-dsp-pm.h \ - pmgen/ql-dsp-macc.h \ - pmgen/ql-bram-asymmetric-wider-write.h \ - pmgen/ql-bram-asymmetric-wider-read.h - include ../Makefile_plugin.common +# For pmgen/*.h +CXXFLAGS += -I$(BUILD_DIR) + COMMON = common QLF_K4N8_DIR = qlf_k4n8 QLF_K6N10_DIR = qlf_k6n10 @@ -55,6 +55,7 @@ VERILOG_MODULES = $(COMMON)/cells_sim.v \ $(QLF_K6N10F_DIR)/brams.txt \ $(QLF_K6N10F_DIR)/cells_sim.v \ $(QLF_K6N10F_DIR)/dsp_sim.v \ + $(QLF_K6N10F_DIR)/brams_sim.v \ $(QLF_K6N10F_DIR)/sram1024x18.v \ $(QLF_K6N10F_DIR)/TDP18K_FIFO.v \ $(QLF_K6N10F_DIR)/ufifo_ctl.v \ @@ -77,28 +78,35 @@ VERILOG_MODULES = $(COMMON)/cells_sim.v \ $(PP3_DIR)/bram_init_32.vh \ $(PP3_DIR)/qlal4s3b_sim.v \ $(PP3_DIR)/mult_sim.v \ - $(PP3_DIR)/qlal3_sim.v \ + $(PP3_DIR)/qlal3_sim.v + +PMGEN_OUT_DIR := $(BUILD_DIR)/pmgen -pmgen: - mkdir -p pmgen +$(PMGEN_OUT_DIR): + mkdir -p $@ -pmgen/ql-dsp-pm.h: ../pmgen.py ql_dsp.pmg | pmgen - python3 ../pmgen.py -o $@ -p ql_dsp ql_dsp.pmg +DEPS := $(PMGEN_OUT_DIR)/ql-dsp-pm.h \ + $(PMGEN_OUT_DIR)/ql-dsp-macc.h \ + $(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-write.h \ + $(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-read.h -pmgen/ql-dsp-macc.h: ../pmgen.py ql-dsp-macc.pmg | pmgen - python3 ../pmgen.py -o $@ -p ql_dsp_macc ql-dsp-macc.pmg +$(DEPS): $(PMGEN_PY) | $(PMGEN_OUT_DIR) -pmgen/ql-bram-asymmetric-wider-write.h: ../pmgen.py ql-bram-asymmetric-wider-write.pmg | pmgen - python3 ../pmgen.py -o $@ -p ql_bram_asymmetric_wider_write ql-bram-asymmetric-wider-write.pmg +$(OBJECTS): $(DEPS) -pmgen/ql-bram-asymmetric-wider-read.h: ../pmgen.py ql-bram-asymmetric-wider-read.pmg | pmgen - python3 ../pmgen.py -o $@ -p ql_bram_asymmetric_wider_read ql-bram-asymmetric-wider-read.pmg +$(PMGEN_OUT_DIR)/ql-dsp-pm.h: ql_dsp.pmg + python3 $(PMGEN_PY) -o $@ -p ql_dsp ql_dsp.pmg + +$(PMGEN_OUT_DIR)/ql-dsp-macc.h: ql-dsp-macc.pmg + python3 $(PMGEN_PY) -o $@ -p ql_dsp_macc ql-dsp-macc.pmg + +$(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-write.h: ql-bram-asymmetric-wider-write.pmg + python3 $(PMGEN_PY) -o $@ -p ql_bram_asymmetric_wider_write ql-bram-asymmetric-wider-write.pmg + +$(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-read.h: ql-bram-asymmetric-wider-read.pmg + python3 $(PMGEN_PY) -o $@ -p ql_bram_asymmetric_wider_read ql-bram-asymmetric-wider-read.pmg install_modules: $(VERILOG_MODULES) - $(foreach f,$^,install -D $(f) $(DATA_DIR)/quicklogic/$(f);) + $(foreach f,$^,install -D $(f) $(YOSYS_DATA_DIR)/quicklogic/$(f);) install: install_modules - -clean: - $(MAKE) -f ../Makefile_plugin.common $@ - rm -rf pmgen diff --git a/ql-qlf-plugin/ql-bram-split.cc b/ql-qlf-plugin/ql-bram-split.cc index f699ee5..6a7d2f9 100644 --- a/ql-qlf-plugin/ql-bram-split.cc +++ b/ql-qlf-plugin/ql-bram-split.cc @@ -129,6 +129,97 @@ struct QlBramSplitPass : public Pass { } } + void map_pairs(std::vector group, BramConfig config, std::vector *cellsToRemove, RTLIL::Module *module) + { + // Ensure an even number + size_t count = group.size(); + if (count & 1) + count--; + + // Map SIMD pairs + for (size_t i = 0; i < count; i += 2) { + const RTLIL::Cell *bram_0 = group[i]; + const RTLIL::Cell *bram_1 = group[i + 1]; + + if (bram_0->type != bram_1->type) + log_error("Unsupported BRAM configuration: one half of TDP36K is TDP, second SDP"); + + std::vector> m_BramDataPorts_0; + std::vector> m_BramDataPorts_1; + std::string m_Bram1x18Type; + std::string m_Bram2x18Type; + // Distinguish between TDP and SDP + if (bram_0->type == RTLIL::escape_id(m_Bram1x18TDPType)) { + m_BramDataPorts_0 = m_BramTDPDataPorts_0; + m_BramDataPorts_1 = m_BramTDPDataPorts_1; + m_Bram1x18Type = m_Bram1x18TDPType; + m_Bram2x18Type = m_Bram2x18TDPType; + } else { + m_BramDataPorts_0 = m_BramSDPDataPorts_0; + m_BramDataPorts_1 = m_BramSDPDataPorts_1; + m_Bram1x18Type = m_Bram1x18SDPType; + m_Bram2x18Type = m_Bram2x18SDPType; + } + + std::string name = stringf("bram_%s_%s", RTLIL::unescape_id(bram_0->name).c_str(), RTLIL::unescape_id(bram_1->name).c_str()); + + log(" BRAM: %s (%s) + %s (%s) => %s (%s)\n", RTLIL::unescape_id(bram_0->name).c_str(), RTLIL::unescape_id(bram_0->type).c_str(), + RTLIL::unescape_id(bram_1->name).c_str(), RTLIL::unescape_id(bram_1->type).c_str(), RTLIL::unescape_id(name).c_str(), + m_Bram2x18Type.c_str()); + + // Create the new cell + RTLIL::Cell *bram_2x18 = module->addCell(RTLIL::escape_id(name), RTLIL::escape_id(m_Bram2x18Type)); + + // Check if the target cell is known (important to know + // its port widths) + if (!bram_2x18->known()) { + log_error(" The target cell type '%s' is not known!", m_Bram2x18Type.c_str()); + } + + // Connect shared ports + for (const auto &it : m_BramSharedPorts) { + auto src = RTLIL::escape_id(it.first); + auto dst = RTLIL::escape_id(it.second); + + bram_2x18->setPort(dst, config.connections.at(src)); + } + + // Connect data ports + // Connect first bram + map_ports(m_BramDataPorts_0, bram_0, bram_2x18); + // Connect second bram + map_ports(m_BramDataPorts_1, bram_1, bram_2x18); + + // Set bram parameters + for (const auto &it : m_BramParams) { + auto val = bram_0->getParam(RTLIL::escape_id(it)); + bram_2x18->setParam(RTLIL::escape_id(it), val); + } + + // Setting manual parameters + if (bram_0->type == RTLIL::escape_id(m_Bram1x18TDPType)) { + bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_B"), bram_0->getParam(RTLIL::escape_id("CFG_ENABLE_B"))); + bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_D"), bram_0->getParam(RTLIL::escape_id("CFG_ENABLE_D"))); + bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_F"), bram_1->getParam(RTLIL::escape_id("CFG_ENABLE_B"))); + bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_H"), bram_1->getParam(RTLIL::escape_id("CFG_ENABLE_D"))); + } else { + bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_B"), bram_0->getParam(RTLIL::escape_id("CFG_ENABLE_B"))); + bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_D"), bram_1->getParam(RTLIL::escape_id("CFG_ENABLE_B"))); + } + if (bram_0->hasParam(RTLIL::escape_id("INIT"))) + bram_2x18->setParam(RTLIL::escape_id("INIT0"), bram_0->getParam(RTLIL::escape_id("INIT"))); + if (bram_1->hasParam(RTLIL::escape_id("INIT"))) + bram_2x18->setParam(RTLIL::escape_id("INIT1"), bram_1->getParam(RTLIL::escape_id("INIT"))); + + // Since in this pass we are mapping the inferred cell directly then mark it as inferred + bram_2x18->set_bool_attribute(RTLIL::escape_id("is_inferred"), true); + + // Mark BRAM parts for removal + cellsToRemove->push_back(bram_0); + cellsToRemove->push_back(bram_1); + } + } + void execute(std::vector a_Args, RTLIL::Design *a_Design) override { log_header(a_Design, "Executing QL_BRAM_Split pass.\n"); @@ -144,115 +235,37 @@ struct QlBramSplitPass : public Pass { m_SigMap.set(module); // Assemble BRAM cell groups - dict> groups; + dict> sdp_groups, tdp_groups; for (auto cell : module->selected_cells()) { - // Check if this is a BRAM cell - if (cell->type != RTLIL::escape_id(m_Bram1x18TDPType) && cell->type != RTLIL::escape_id(m_Bram1x18SDPType)) { - continue; - } - // Skip if it has the (* keep *) attribute set if (cell->has_keep_attr()) { continue; } - // Add to a group + // Check if this is a BRAM cell and add to a group const auto key = getBramConfig(cell); - groups[key].push_back(cell); + if (cell->type == RTLIL::escape_id(m_Bram1x18TDPType)) { + tdp_groups[key].push_back(cell); + } else if (cell->type == RTLIL::escape_id(m_Bram1x18SDPType)) { + sdp_groups[key].push_back(cell); + } else { + continue; + } } std::vector cellsToRemove; // Map cell pairs to the target BRAM 2x18 cell - for (const auto &it : groups) { + for (const auto &it : sdp_groups) { const auto &group = it.second; const auto &config = it.first; - - // Ensure an even number - size_t count = group.size(); - if (count & 1) - count--; - - // Map SIMD pairs - for (size_t i = 0; i < count; i += 2) { - const RTLIL::Cell *bram_0 = group[i]; - const RTLIL::Cell *bram_1 = group[i + 1]; - - if (bram_0->type != bram_1->type) - log_error("Unsupported BRAM configuration: one half of TDP36K is TDP, second SDP"); - - std::vector> m_BramDataPorts_0; - std::vector> m_BramDataPorts_1; - std::string m_Bram1x18Type; - std::string m_Bram2x18Type; - // Distinguish between TDP and SDP - if (bram_0->type == RTLIL::escape_id(m_Bram1x18TDPType)) { - m_BramDataPorts_0 = m_BramTDPDataPorts_0; - m_BramDataPorts_1 = m_BramTDPDataPorts_1; - m_Bram1x18Type = m_Bram1x18TDPType; - m_Bram2x18Type = m_Bram2x18TDPType; - } else { - m_BramDataPorts_0 = m_BramSDPDataPorts_0; - m_BramDataPorts_1 = m_BramSDPDataPorts_1; - m_Bram1x18Type = m_Bram1x18SDPType; - m_Bram2x18Type = m_Bram2x18SDPType; - } - - std::string name = stringf("bram_%s_%s", RTLIL::unescape_id(bram_0->name).c_str(), RTLIL::unescape_id(bram_1->name).c_str()); - - log(" BRAM: %s (%s) + %s (%s) => %s (%s)\n", RTLIL::unescape_id(bram_0->name).c_str(), RTLIL::unescape_id(bram_0->type).c_str(), - RTLIL::unescape_id(bram_1->name).c_str(), RTLIL::unescape_id(bram_1->type).c_str(), RTLIL::unescape_id(name).c_str(), - m_Bram2x18Type.c_str()); - - // Create the new cell - RTLIL::Cell *bram_2x18 = module->addCell(RTLIL::escape_id(name), RTLIL::escape_id(m_Bram2x18Type)); - - // Check if the target cell is known (important to know - // its port widths) - if (!bram_2x18->known()) { - log_error(" The target cell type '%s' is not known!", m_Bram2x18Type.c_str()); - } - - // Connect shared ports - for (const auto &it : m_BramSharedPorts) { - auto src = RTLIL::escape_id(it.first); - auto dst = RTLIL::escape_id(it.second); - - bram_2x18->setPort(dst, config.connections.at(src)); - } - - // Connect data ports - // Connect first bram - map_ports(m_BramDataPorts_0, bram_0, bram_2x18); - // Connect second bram - map_ports(m_BramDataPorts_1, bram_1, bram_2x18); - - // Set bram parameters - for (const auto &it : m_BramParams) { - auto val = bram_0->getParam(RTLIL::escape_id(it)); - bram_2x18->setParam(RTLIL::escape_id(it), val); - } - - // Setting manual parameters - if (bram_0->type == RTLIL::escape_id(m_Bram1x18TDPType)) { - bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_B"), bram_0->getParam(RTLIL::escape_id("CFG_ENABLE_B"))); - bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_D"), bram_0->getParam(RTLIL::escape_id("CFG_ENABLE_D"))); - bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_F"), bram_1->getParam(RTLIL::escape_id("CFG_ENABLE_B"))); - bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_H"), bram_1->getParam(RTLIL::escape_id("CFG_ENABLE_D"))); - } else { - bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_B"), bram_0->getParam(RTLIL::escape_id("CFG_ENABLE_B"))); - bram_2x18->setParam(RTLIL::escape_id("CFG_ENABLE_D"), bram_1->getParam(RTLIL::escape_id("CFG_ENABLE_B"))); - } - if (bram_0->hasParam(RTLIL::escape_id("INIT"))) - bram_2x18->setParam(RTLIL::escape_id("INIT0"), bram_0->getParam(RTLIL::escape_id("INIT"))); - if (bram_1->hasParam(RTLIL::escape_id("INIT"))) - bram_2x18->setParam(RTLIL::escape_id("INIT1"), bram_1->getParam(RTLIL::escape_id("INIT"))); - - // Mark BRAM parts for removal - cellsToRemove.push_back(bram_0); - cellsToRemove.push_back(bram_1); - } + map_pairs(group, config, &cellsToRemove, module); + } + for (const auto &it : tdp_groups) { + const auto &group = it.second; + const auto &config = it.first; + map_pairs(group, config, &cellsToRemove, module); } // Remove old cells diff --git a/ql-qlf-plugin/qlf_k6n10f/brams_final_map.v b/ql-qlf-plugin/qlf_k6n10f/brams_final_map.v index aa4bb5d..7637595 100644 --- a/ql-qlf-plugin/qlf_k6n10f/brams_final_map.v +++ b/ql-qlf-plugin/qlf_k6n10f/brams_final_map.v @@ -227,6 +227,9 @@ module BRAM2x18_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, wire PORT_B2_WEN = H1EN[0]; wire [CFG_ENABLE_H-1:0] PORT_B2_BE = {H1EN[1],H1EN[0]}; + (* is_split = 1 *) + (* rd_data_width = CFG_DBITS *) + (* wr_data_width = CFG_DBITS *) TDP36K _TECHMAP_REPLACE_ ( .WDATA_A1_i(PORT_A1_WDATA), .RDATA_A1_o(PORT_A1_RDATA), @@ -443,6 +446,9 @@ module BRAM2x18_SDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, wire PORT_B2_WEN = D1EN[0]; wire [CFG_ENABLE_D-1:0] PORT_B2_BE = {D1EN[1],D1EN[0]}; + (* is_split = 1 *) + (* rd_data_width = CFG_DBITS *) + (* wr_data_width = CFG_DBITS *) TDP36K _TECHMAP_REPLACE_ ( .WDATA_A1_i(PORT_A1_WDATA), .RDATA_A1_o(PORT_A1_RDATA), diff --git a/ql-qlf-plugin/qlf_k6n10f/brams_map.v b/ql-qlf-plugin/qlf_k6n10f/brams_map.v index 873a5d7..d510848 100644 --- a/ql-qlf-plugin/qlf_k6n10f/brams_map.v +++ b/ql-qlf-plugin/qlf_k6n10f/brams_map.v @@ -163,6 +163,9 @@ module \$__QLF_FACTOR_BRAM36_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1 assign FLUSH1 = 1'b0; assign FLUSH2 = 1'b0; + (* is_inferred = 1 *) + (* rd_data_width = CFG_DBITS *) + (* wr_data_width = CFG_DBITS *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(B1DATA_TOTAL[17:0]), @@ -233,6 +236,7 @@ module \$__QLF_FACTOR_BRAM18_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1 input [CFG_DBITS-1:0] D1DATA; input [CFG_ENABLE_D-1:0] D1EN; + (* is_inferred = 1 *) BRAM2x18_TDP #( .CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS), @@ -296,6 +300,7 @@ module \$__QLF_FACTOR_BRAM18_SDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, CL input [CFG_DBITS-1:0] B1DATA; input [CFG_ENABLE_B-1:0] B1EN; + (* is_inferred = 1 *) BRAM2x18_SDP #( .CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS), @@ -446,6 +451,9 @@ module \$__QLF_FACTOR_BRAM36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DA assign FLUSH1 = 1'b0; assign FLUSH2 = 1'b0; + (* is_inferred = 1 *) + (* rd_data_width = CFG_DBITS *) + (* wr_data_width = CFG_DBITS *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(18'h3FFFF), @@ -968,6 +976,9 @@ module \$__QLF_FACTOR_BRAM36_SDP_ASYMMETRIC (RD_ADDR, RD_ARST, RD_CLK, RD_DATA, wire PORT_A2_WEN = WR_EN; wire [1:0] PORT_A2_BE = {PORT_A2_WEN, PORT_A2_WEN}; + (* is_inferred = 1 *) + (* rd_data_width = RD_DATA_WIDTH *) + (* wr_data_width = WR_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), diff --git a/ql-qlf-plugin/qlf_k6n10f/brams_sim.v b/ql-qlf-plugin/qlf_k6n10f/brams_sim.v new file mode 100644 index 0000000..c718966 --- /dev/null +++ b/ql-qlf-plugin/qlf_k6n10f/brams_sim.v @@ -0,0 +1,5846 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +module TDP_BRAM18 ( + (* clkbuf_sink *) + input wire CLOCKA, + (* clkbuf_sink *) + input wire CLOCKB, + input wire READENABLEA, + input wire READENABLEB, + input wire [13:0] ADDRA, + input wire [13:0] ADDRB, + input wire [15:0] WRITEDATAA, + input wire [15:0] WRITEDATAB, + input wire [1:0] WRITEDATAAP, + input wire [1:0] WRITEDATABP, + input wire WRITEENABLEA, + input wire WRITEENABLEB, + input wire [1:0] BYTEENABLEA, + input wire [1:0] BYTEENABLEB, + //input wire [2:0] WRITEDATAWIDTHA, + //input wire [2:0] WRITEDATAWIDTHB, + //input wire [2:0] READDATAWIDTHA, + //input wire [2:0] READDATAWIDTHB, + output wire [15:0] READDATAA, + output wire [15:0] READDATAB, + output wire [1:0] READDATAAP, + output wire [1:0] READDATABP +); + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + +endmodule + +module TDP36K ( + RESET_ni, + WEN_A1_i, + WEN_B1_i, + REN_A1_i, + REN_B1_i, + CLK_A1_i, + CLK_B1_i, + BE_A1_i, + BE_B1_i, + ADDR_A1_i, + ADDR_B1_i, + WDATA_A1_i, + WDATA_B1_i, + RDATA_A1_o, + RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, + WEN_B2_i, + REN_A2_i, + REN_B2_i, + CLK_A2_i, + CLK_B2_i, + BE_A2_i, + BE_B2_i, + ADDR_A2_i, + ADDR_B2_i, + WDATA_A2_i, + WDATA_B2_i, + RDATA_A2_o, + RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + // First 18K RAMFIFO (41 bits) + localparam [ 0:0] SYNC_FIFO1_i = MODE_BITS[0]; + localparam [ 2:0] RMODE_A1_i = MODE_BITS[3 : 1]; + localparam [ 2:0] RMODE_B1_i = MODE_BITS[6 : 4]; + localparam [ 2:0] WMODE_A1_i = MODE_BITS[9 : 7]; + localparam [ 2:0] WMODE_B1_i = MODE_BITS[12:10]; + localparam [ 0:0] FMODE1_i = MODE_BITS[13]; + localparam [ 0:0] POWERDN1_i = MODE_BITS[14]; + localparam [ 0:0] SLEEP1_i = MODE_BITS[15]; + localparam [ 0:0] PROTECT1_i = MODE_BITS[16]; + localparam [11:0] UPAE1_i = MODE_BITS[28:17]; + localparam [11:0] UPAF1_i = MODE_BITS[40:29]; + + // Second 18K RAMFIFO (39 bits) + localparam [ 0:0] SYNC_FIFO2_i = MODE_BITS[41]; + localparam [ 2:0] RMODE_A2_i = MODE_BITS[44:42]; + localparam [ 2:0] RMODE_B2_i = MODE_BITS[47:45]; + localparam [ 2:0] WMODE_A2_i = MODE_BITS[50:48]; + localparam [ 2:0] WMODE_B2_i = MODE_BITS[53:51]; + localparam [ 0:0] FMODE2_i = MODE_BITS[54]; + localparam [ 0:0] POWERDN2_i = MODE_BITS[55]; + localparam [ 0:0] SLEEP2_i = MODE_BITS[56]; + localparam [ 0:0] PROTECT2_i = MODE_BITS[57]; + localparam [10:0] UPAE2_i = MODE_BITS[68:58]; + localparam [10:0] UPAF2_i = MODE_BITS[79:69]; + + // Split (1 bit) + localparam [ 0:0] SPLIT_i = MODE_BITS[80]; + + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + input wire RESET_ni; + input wire WEN_A1_i; + input wire WEN_B1_i; + input wire REN_A1_i; + input wire REN_B1_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + input wire [1:0] BE_A1_i; + input wire [1:0] BE_B1_i; + input wire [14:0] ADDR_A1_i; + input wire [14:0] ADDR_B1_i; + input wire [17:0] WDATA_A1_i; + input wire [17:0] WDATA_B1_i; + output reg [17:0] RDATA_A1_o; + output reg [17:0] RDATA_B1_o; + input wire FLUSH1_i; + input wire WEN_A2_i; + input wire WEN_B2_i; + input wire REN_A2_i; + input wire REN_B2_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + input wire [1:0] BE_A2_i; + input wire [1:0] BE_B2_i; + input wire [13:0] ADDR_A2_i; + input wire [13:0] ADDR_B2_i; + input wire [17:0] WDATA_A2_i; + input wire [17:0] WDATA_B2_i; + output reg [17:0] RDATA_A2_o; + output reg [17:0] RDATA_B2_o; + input wire FLUSH2_i; + wire EMPTY2; + wire EPO2; + wire EWM2; + wire FULL2; + wire FMO2; + wire FWM2; + wire EMPTY1; + wire EPO1; + wire EWM1; + wire FULL1; + wire FMO1; + wire FWM1; + wire UNDERRUN1; + wire OVERRUN1; + wire UNDERRUN2; + wire OVERRUN2; + wire UNDERRUN3; + wire OVERRUN3; + wire EMPTY3; + wire EPO3; + wire EWM3; + wire FULL3; + wire FMO3; + wire FWM3; + wire ram_fmode1; + wire ram_fmode2; + wire [17:0] ram_rdata_a1; + wire [17:0] ram_rdata_b1; + wire [17:0] ram_rdata_a2; + wire [17:0] ram_rdata_b2; + reg [17:0] ram_wdata_a1; + reg [17:0] ram_wdata_b1; + reg [17:0] ram_wdata_a2; + reg [17:0] ram_wdata_b2; + reg [14:0] laddr_a1; + reg [14:0] laddr_b1; + wire [13:0] ram_addr_a1; + wire [13:0] ram_addr_b1; + wire [13:0] ram_addr_a2; + wire [13:0] ram_addr_b2; + wire smux_clk_a1; + wire smux_clk_b1; + wire smux_clk_a2; + wire smux_clk_b2; + reg [1:0] ram_be_a1; + reg [1:0] ram_be_a2; + reg [1:0] ram_be_b1; + reg [1:0] ram_be_b2; + wire [2:0] ram_rmode_a1; + wire [2:0] ram_wmode_a1; + wire [2:0] ram_rmode_b1; + wire [2:0] ram_wmode_b1; + wire [2:0] ram_rmode_a2; + wire [2:0] ram_wmode_a2; + wire [2:0] ram_rmode_b2; + wire [2:0] ram_wmode_b2; + wire ram_ren_a1; + wire ram_ren_b1; + wire ram_ren_a2; + wire ram_ren_b2; + wire ram_wen_a1; + wire ram_wen_b1; + wire ram_wen_a2; + wire ram_wen_b2; + wire ren_o; + wire [11:0] ff_raddr; + wire [11:0] ff_waddr; + reg [35:0] fifo_rdata; + wire [1:0] fifo_rmode; + wire [1:0] fifo_wmode; + wire [1:0] bwl; + wire [17:0] pl_dout0; + wire [17:0] pl_dout1; + wire sclk_a1; + wire sclk_b1; + wire sclk_a2; + wire sclk_b2; + wire sreset; + wire flush1; + wire flush2; + assign sreset = RESET_ni; + assign flush1 = ~FLUSH1_i; + assign flush2 = ~FLUSH2_i; + assign ram_fmode1 = FMODE1_i & SPLIT_i; + assign ram_fmode2 = FMODE2_i & SPLIT_i; + assign smux_clk_a1 = CLK_A1_i; + assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i); + assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i); + assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); + assign sclk_a1 = smux_clk_a1; + assign sclk_a2 = smux_clk_a2; + assign sclk_b1 = smux_clk_b1; + assign sclk_b2 = smux_clk_b2; + assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i)); + assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i)); + localparam MODE_36 = 3'b011; + assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4]))); + assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4]))); + assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4])); + assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4])); + assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3])); + localparam MODE_18 = 3'b010; + localparam MODE_9 = 3'b001; + always @(*) begin : WDATA_SEL + case (SPLIT_i) + 1: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_wdata_b1 = WDATA_B1_i; + ram_wdata_b2 = WDATA_B2_i; + ram_be_a2 = BE_A2_i; + ram_be_b2 = BE_B2_i; + ram_be_a1 = BE_A1_i; + ram_be_b1 = BE_B1_i; + end + 0: begin + case (WMODE_A1_i) + MODE_36: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + MODE_18: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i); + ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i); + end + MODE_9: begin + ram_wdata_a1[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a1[16] = WDATA_A1_i[16]; + ram_wdata_a1[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a1[17] = WDATA_A1_i[16]; + ram_wdata_a2[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a2[16] = WDATA_A1_i[16]; + ram_wdata_a2[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a2[17] = WDATA_A1_i[16]; + case (bwl) + 0: {ram_be_a2, ram_be_a1} = 4'b0001; + 1: {ram_be_a2, ram_be_a1} = 4'b0010; + 2: {ram_be_a2, ram_be_a1} = 4'b0100; + 3: {ram_be_a2, ram_be_a1} = 4'b1000; + endcase + end + default: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + endcase + case (WMODE_B1_i) + MODE_36: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i); + ram_be_b2 = BE_B2_i; + ram_be_b1 = BE_B1_i; + end + MODE_18: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b1 = BE_B1_i; + ram_be_b2 = BE_B1_i; + end + MODE_9: begin + ram_wdata_b1[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b1[16] = WDATA_B1_i[16]; + ram_wdata_b1[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b1[17] = WDATA_B1_i[16]; + ram_wdata_b2[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b2[16] = WDATA_B1_i[16]; + ram_wdata_b2[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b2[17] = WDATA_B1_i[16]; + case (ADDR_B1_i[4:3]) + 0: {ram_be_b2, ram_be_b1} = 4'b0001; + 1: {ram_be_b2, ram_be_b1} = 4'b0010; + 2: {ram_be_b2, ram_be_b1} = 4'b0100; + 3: {ram_be_b2, ram_be_b1} = 4'b1000; + endcase + end + default: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b2 = BE_B1_i; + ram_be_b1 = BE_B1_i; + end + endcase + end + endcase + end + assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + always @(*) begin : FIFO_READ_SEL + case (RMODE_B1_i) + MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; + MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1}); + MODE_9: + case (ff_raddr[1:0]) + 0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}; + 1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]}; + 2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]}; + 3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]}; + endcase + default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1}; + endcase + end + localparam MODE_1 = 3'b101; + localparam MODE_2 = 3'b110; + localparam MODE_4 = 3'b100; + always @(*) begin : RDATA_SEL + case (SPLIT_i) + 1: begin + RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1); + RDATA_B1_o = ram_rdata_b1; + RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2); + RDATA_B2_o = ram_rdata_b2; + end + 0: begin + if (FMODE1_i) begin + RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3}; + RDATA_A2_o = 18'b000000000000000000; + end + else + case (RMODE_A1_i) + MODE_36: begin + RDATA_A1_o = {ram_rdata_a1[17:0]}; + RDATA_A2_o = {ram_rdata_a2[17:0]}; + end + MODE_18: begin + RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}}); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:4] = 14'b00000000000000; + RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]); + end + MODE_2: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:2] = 16'b0000000000000000; + RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]); + end + MODE_1: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:1] = 17'b00000000000000000; + RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]); + end + default: begin + RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]}; + RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]}; + end + endcase + case (RMODE_B1_i) + MODE_36: begin + RDATA_B1_o = {ram_rdata_b1}; + RDATA_B2_o = {ram_rdata_b2}; + end + MODE_18: begin + RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1)); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]})); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:4] = 14'b00000000000000; + RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]); + end + MODE_2: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:2] = 16'b0000000000000000; + RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]); + end + MODE_1: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:1] = 17'b00000000000000000; + RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]); + end + default: begin + RDATA_B1_o = ram_rdata_b1; + RDATA_B2_o = ram_rdata_b2; + end + endcase + end + endcase + end + always @(posedge sclk_a1 or negedge sreset) + if (sreset == 0) + laddr_a1 <= 1'sb0; + else + laddr_a1 <= ADDR_A1_i; + always @(posedge sclk_b1 or negedge sreset) + if (sreset == 0) + laddr_b1 <= 1'sb0; + else + laddr_b1 <= ADDR_B1_i; + assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00))); + assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00))); + fifo_ctl #( + .ADDR_WIDTH(12), + .FIFO_WIDTH(3'd4), + .DEPTH(7) + ) fifo36_ctl( + .rclk(sclk_b1), + .rst_R_n(flush1), + .wclk(sclk_a1), + .rst_W_n(flush1), + .ren(REN_B1_i), + .wen(ram_wen_a1), + .sync(SYNC_FIFO1_i), + .rmode(fifo_rmode), + .wmode(fifo_wmode), + .ren_o(ren_o), + .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}), + .raddr(ff_raddr), + .waddr(ff_waddr), + .upaf(UPAF1_i), + .upae(UPAE1_i) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF1_i[10:0]), + .UPAE_i(UPAE1_i[10:0]), + .SYNC_FIFO_i(SYNC_FIFO1_i), + .POWERDN_i(POWERDN1_i), + .SLEEP_i(SLEEP1_i), + .PROTECT_i(PROTECT1_i) + )u1( + .RMODE_A_i(ram_rmode_a1), + .RMODE_B_i(ram_rmode_b1), + .WMODE_A_i(ram_wmode_a1), + .WMODE_B_i(ram_wmode_b1), + .WEN_A_i(ram_wen_a1), + .WEN_B_i(ram_wen_b1), + .REN_A_i(ram_ren_a1), + .REN_B_i(ram_ren_b1), + .CLK_A_i(sclk_a1), + .CLK_B_i(sclk_b1), + .BE_A_i(ram_be_a1), + .BE_B_i(ram_be_b1), + .ADDR_A_i(ram_addr_a1), + .ADDR_B_i(ram_addr_b1), + .WDATA_A_i(ram_wdata_a1), + .WDATA_B_i(ram_wdata_b1), + .RDATA_A_o(ram_rdata_a1), + .RDATA_B_o(ram_rdata_b1), + .EMPTY_o(EMPTY1), + .EPO_o(EPO1), + .EWM_o(EWM1), + .UNDERRUN_o(UNDERRUN1), + .FULL_o(FULL1), + .FMO_o(FMO1), + .FWM_o(FWM1), + .OVERRUN_o(OVERRUN1), + .FLUSH_ni(flush1), + .FMODE_i(ram_fmode1) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF2_i), + .UPAE_i(UPAE2_i), + .SYNC_FIFO_i(SYNC_FIFO2_i), + .POWERDN_i(POWERDN2_i), + .SLEEP_i(SLEEP2_i), + .PROTECT_i(PROTECT2_i) + )u2( + .RMODE_A_i(ram_rmode_a2), + .RMODE_B_i(ram_rmode_b2), + .WMODE_A_i(ram_wmode_a2), + .WMODE_B_i(ram_wmode_b2), + .WEN_A_i(ram_wen_a2), + .WEN_B_i(ram_wen_b2), + .REN_A_i(ram_ren_a2), + .REN_B_i(ram_ren_b2), + .CLK_A_i(sclk_a2), + .CLK_B_i(sclk_b2), + .BE_A_i(ram_be_a2), + .BE_B_i(ram_be_b2), + .ADDR_A_i(ram_addr_a2), + .ADDR_B_i(ram_addr_b2), + .WDATA_A_i(ram_wdata_a2), + .WDATA_B_i(ram_wdata_b2), + .RDATA_A_o(ram_rdata_a2), + .RDATA_B_o(ram_rdata_b2), + .EMPTY_o(EMPTY2), + .EPO_o(EPO2), + .EWM_o(EWM2), + .UNDERRUN_o(UNDERRUN2), + .FULL_o(FULL2), + .FMO_o(FMO2), + .FWM_o(FWM2), + .OVERRUN_o(OVERRUN2), + .FLUSH_ni(flush2), + .FMODE_i(ram_fmode2) + ); +endmodule + +module BRAM2x18_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, CLK3, CLK4, D1ADDR, D1DATA, D1EN, E1ADDR, E1DATA, E1EN, F1ADDR, F1DATA, F1EN, G1ADDR, G1DATA, G1EN, H1ADDR, H1DATA, H1EN); + parameter CFG_ABITS = 11; + parameter CFG_DBITS = 18; + parameter CFG_ENABLE_B = 4; + parameter CFG_ENABLE_D = 4; + parameter CFG_ENABLE_F = 4; + parameter CFG_ENABLE_H = 4; + + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; + parameter [18431:0] INIT0 = 18432'bx; + parameter [18431:0] INIT1 = 18432'bx; + + localparam MODE_36 = 3'b011; // 36- or 32-bit + localparam MODE_18 = 3'b010; // 18- or 16-bit + localparam MODE_9 = 3'b001; // 9- or 8-bit + localparam MODE_4 = 3'b100; // 4-bit + localparam MODE_2 = 3'b110; // 2-bit + localparam MODE_1 = 3'b101; // 1-bit + + input wire CLK1; + input wire CLK2; + input wire CLK3; + input wire CLK4; + + input wire [CFG_ABITS-1:0] A1ADDR; + output wire [CFG_DBITS-1:0] A1DATA; + input wire A1EN; + + input wire [CFG_ABITS-1:0] B1ADDR; + input wire [CFG_DBITS-1:0] B1DATA; + input wire [CFG_ENABLE_B-1:0] B1EN; + + input wire [CFG_ABITS-1:0] C1ADDR; + output wire [CFG_DBITS-1:0] C1DATA; + input wire C1EN; + + input wire [CFG_ABITS-1:0] D1ADDR; + input wire [CFG_DBITS-1:0] D1DATA; + input wire [CFG_ENABLE_D-1:0] D1EN; + + input wire [CFG_ABITS-1:0] E1ADDR; + output wire [CFG_DBITS-1:0] E1DATA; + input wire E1EN; + + input wire [CFG_ABITS-1:0] F1ADDR; + input wire [CFG_DBITS-1:0] F1DATA; + input wire [CFG_ENABLE_F-1:0] F1EN; + + input wire [CFG_ABITS-1:0] G1ADDR; + output wire [CFG_DBITS-1:0] G1DATA; + input wire G1EN; + + input wire [CFG_ABITS-1:0] H1ADDR; + input wire [CFG_DBITS-1:0] H1DATA; + input wire [CFG_ENABLE_H-1:0] H1EN; + + wire FLUSH1; + wire FLUSH2; + wire SPLIT; + + wire [13:CFG_ABITS] A1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] B1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] C1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] D1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] E1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] F1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] G1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] H1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + + wire [13:0] A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR}; + wire [13:0] B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR}; + wire [13:0] C1ADDR_TOTAL = {C1ADDR_CMPL, C1ADDR}; + wire [13:0] D1ADDR_TOTAL = {D1ADDR_CMPL, D1ADDR}; + wire [13:0] E1ADDR_TOTAL = {E1ADDR_CMPL, E1ADDR}; + wire [13:0] F1ADDR_TOTAL = {F1ADDR_CMPL, F1ADDR}; + wire [13:0] G1ADDR_TOTAL = {G1ADDR_CMPL, G1ADDR}; + wire [13:0] H1ADDR_TOTAL = {H1ADDR_CMPL, H1ADDR}; + + wire [17:CFG_DBITS] A1_RDATA_CMPL; + wire [17:CFG_DBITS] C1_RDATA_CMPL; + wire [17:CFG_DBITS] E1_RDATA_CMPL; + wire [17:CFG_DBITS] G1_RDATA_CMPL; + + wire [17:CFG_DBITS] B1_WDATA_CMPL; + wire [17:CFG_DBITS] D1_WDATA_CMPL; + wire [17:CFG_DBITS] F1_WDATA_CMPL; + wire [17:CFG_DBITS] H1_WDATA_CMPL; + + wire [13:0] PORT_A1_ADDR; + wire [13:0] PORT_A2_ADDR; + wire [13:0] PORT_B1_ADDR; + wire [13:0] PORT_B2_ADDR; + + case (CFG_DBITS) + 1: begin + assign PORT_A1_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 14'd0); + assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0); + assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0); + assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0); + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0 + }; + end + + 2: begin + assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 1) : (B1EN ? (B1ADDR_TOTAL << 1) : 14'd0); + assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 1) : (D1EN ? (D1ADDR_TOTAL << 1) : 14'd0); + assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 1) : (F1EN ? (F1ADDR_TOTAL << 1) : 14'd0); + assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 1) : (H1EN ? (H1ADDR_TOTAL << 1) : 14'd0); + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0 + }; + end + + 4: begin + assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 2) : (B1EN ? (B1ADDR_TOTAL << 2) : 14'd0); + assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 2) : (D1EN ? (D1ADDR_TOTAL << 2) : 14'd0); + assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 2) : (F1EN ? (F1ADDR_TOTAL << 2) : 14'd0); + assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 2) : (H1EN ? (H1ADDR_TOTAL << 2) : 14'd0); + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0 + }; + end + + 8, 9: begin + assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 3) : (B1EN ? (B1ADDR_TOTAL << 3) : 14'd0); + assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 3) : (D1EN ? (D1ADDR_TOTAL << 3) : 14'd0); + assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 3) : (F1EN ? (F1ADDR_TOTAL << 3) : 14'd0); + assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 3) : (H1EN ? (H1ADDR_TOTAL << 3) : 14'd0); + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0 + }; + end + + 16, 18: begin + assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 4) : (B1EN ? (B1ADDR_TOTAL << 4) : 14'd0); + assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 4) : (D1EN ? (D1ADDR_TOTAL << 4) : 14'd0); + assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 4) : (F1EN ? (F1ADDR_TOTAL << 4) : 14'd0); + assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 4) : (H1EN ? (H1ADDR_TOTAL << 4) : 14'd0); + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0 + }; + end + + default: begin + assign PORT_A1_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 14'd0); + assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0); + assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0); + assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0); + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0 + }; + end + endcase + + assign FLUSH1 = 1'b0; + assign FLUSH2 = 1'b0; + + wire [17:0] PORT_A1_RDATA = {A1_RDATA_CMPL, A1DATA}; + wire [17:0] PORT_B1_RDATA = {C1_RDATA_CMPL, C1DATA}; + wire [17:0] PORT_A2_RDATA = {E1_RDATA_CMPL, E1DATA}; + wire [17:0] PORT_B2_RDATA = {G1_RDATA_CMPL, G1DATA}; + + wire [17:0] PORT_A1_WDATA = {B1_WDATA_CMPL, B1DATA}; + wire [17:0] PORT_B1_WDATA = {D1_WDATA_CMPL, D1DATA}; + wire [17:0] PORT_A2_WDATA = {F1_WDATA_CMPL, F1DATA}; + wire [17:0] PORT_B2_WDATA = {H1_WDATA_CMPL, H1DATA}; + + wire PORT_A1_CLK = CLK1; + wire PORT_A2_CLK = CLK3; + wire PORT_B1_CLK = CLK2; + wire PORT_B2_CLK = CLK4; + + wire PORT_A1_REN = A1EN; + wire PORT_A1_WEN = B1EN[0]; + wire [CFG_ENABLE_B-1:0] PORT_A1_BE = {B1EN[1],B1EN[0]}; + + wire PORT_A2_REN = E1EN; + wire PORT_A2_WEN = F1EN[0]; + wire [CFG_ENABLE_F-1:0] PORT_A2_BE = {F1EN[1],F1EN[0]}; + + wire PORT_B1_REN = C1EN; + wire PORT_B1_WEN = D1EN[0]; + wire [CFG_ENABLE_D-1:0] PORT_B1_BE = {D1EN[1],D1EN[0]}; + + wire PORT_B2_REN = G1EN; + wire PORT_B2_WEN = H1EN[0]; + wire [CFG_ENABLE_H-1:0] PORT_B2_BE = {H1EN[1],H1EN[0]}; + + TDP36K bram_2x18k ( + .WDATA_A1_i(PORT_A1_WDATA), + .RDATA_A1_o(PORT_A1_RDATA), + .ADDR_A1_i(PORT_A1_ADDR), + .CLK_A1_i(PORT_A1_CLK), + .REN_A1_i(PORT_A1_REN), + .WEN_A1_i(PORT_A1_WEN), + .BE_A1_i(PORT_A1_BE), + + .WDATA_A2_i(PORT_A2_WDATA), + .RDATA_A2_o(PORT_A2_RDATA), + .ADDR_A2_i(PORT_A2_ADDR), + .CLK_A2_i(PORT_A2_CLK), + .REN_A2_i(PORT_A2_REN), + .WEN_A2_i(PORT_A2_WEN), + .BE_A2_i(PORT_A2_BE), + + .WDATA_B1_i(PORT_B1_WDATA), + .RDATA_B1_o(PORT_B1_RDATA), + .ADDR_B1_i(PORT_B1_ADDR), + .CLK_B1_i(PORT_B1_CLK), + .REN_B1_i(PORT_B1_REN), + .WEN_B1_i(PORT_B1_WEN), + .BE_B1_i(PORT_B1_BE), + + .WDATA_B2_i(PORT_B2_WDATA), + .RDATA_B2_o(PORT_B2_RDATA), + .ADDR_B2_i(PORT_B2_ADDR), + .CLK_B2_i(PORT_B2_CLK), + .REN_B2_i(PORT_B2_REN), + .WEN_B2_i(PORT_B2_WEN), + .BE_B2_i(PORT_B2_BE), + + .FLUSH1_i(FLUSH1), + .FLUSH2_i(FLUSH2) + ); +endmodule + +module BRAM2x18_SDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, D1ADDR, D1DATA, D1EN); + parameter CFG_ABITS = 11; + parameter CFG_DBITS = 18; + parameter CFG_ENABLE_B = 4; + parameter CFG_ENABLE_D = 4; + + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; + parameter [18431:0] INIT0 = 18432'bx; + parameter [18431:0] INIT1 = 18432'bx; + + localparam MODE_36 = 3'b011; // 36- or 32-bit + localparam MODE_18 = 3'b010; // 18- or 16-bit + localparam MODE_9 = 3'b001; // 9- or 8-bit + localparam MODE_4 = 3'b100; // 4-bit + localparam MODE_2 = 3'b110; // 2-bit + localparam MODE_1 = 3'b101; // 1-bit + + input wire CLK1; + input wire CLK2; + + input wire [CFG_ABITS-1:0] A1ADDR; + output wire [CFG_DBITS-1:0] A1DATA; + input wire A1EN; + + input wire [CFG_ABITS-1:0] B1ADDR; + input wire [CFG_DBITS-1:0] B1DATA; + input wire [CFG_ENABLE_B-1:0] B1EN; + + input wire [CFG_ABITS-1:0] C1ADDR; + output wire [CFG_DBITS-1:0] C1DATA; + input wire C1EN; + + input wire [CFG_ABITS-1:0] D1ADDR; + input wire [CFG_DBITS-1:0] D1DATA; + input wire [CFG_ENABLE_D-1:0] D1EN; + + wire FLUSH1; + wire FLUSH2; + + wire [13:CFG_ABITS] A1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] B1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] C1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + wire [13:CFG_ABITS] D1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; + + wire [13:0] A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR}; + wire [13:0] B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR}; + wire [13:0] C1ADDR_TOTAL = {C1ADDR_CMPL, C1ADDR}; + wire [13:0] D1ADDR_TOTAL = {D1ADDR_CMPL, D1ADDR}; + + wire [17:CFG_DBITS] A1_RDATA_CMPL; + wire [17:CFG_DBITS] C1_RDATA_CMPL; + + wire [17:CFG_DBITS] B1_WDATA_CMPL; + wire [17:CFG_DBITS] D1_WDATA_CMPL; + + wire [13:0] PORT_A1_ADDR; + wire [13:0] PORT_A2_ADDR; + wire [13:0] PORT_B1_ADDR; + wire [13:0] PORT_B2_ADDR; + + case (CFG_DBITS) + 1: begin + assign PORT_A1_ADDR = A1ADDR_TOTAL; + assign PORT_B1_ADDR = B1ADDR_TOTAL; + assign PORT_A2_ADDR = C1ADDR_TOTAL; + assign PORT_B2_ADDR = D1ADDR_TOTAL; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0 + }; + end + + 2: begin + assign PORT_A1_ADDR = A1ADDR_TOTAL << 1; + assign PORT_B1_ADDR = B1ADDR_TOTAL << 1; + assign PORT_A2_ADDR = C1ADDR_TOTAL << 1; + assign PORT_B2_ADDR = D1ADDR_TOTAL << 1; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0 + }; + end + + 4: begin + assign PORT_A1_ADDR = A1ADDR_TOTAL << 2; + assign PORT_B1_ADDR = B1ADDR_TOTAL << 2; + assign PORT_A2_ADDR = C1ADDR_TOTAL << 2; + assign PORT_B2_ADDR = D1ADDR_TOTAL << 2; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0 + }; + end + + 8, 9: begin + assign PORT_A1_ADDR = A1ADDR_TOTAL << 3; + assign PORT_B1_ADDR = B1ADDR_TOTAL << 3; + assign PORT_A2_ADDR = C1ADDR_TOTAL << 3; + assign PORT_B2_ADDR = D1ADDR_TOTAL << 3; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0 + }; + end + + 16, 18: begin + assign PORT_A1_ADDR = A1ADDR_TOTAL << 4; + assign PORT_B1_ADDR = B1ADDR_TOTAL << 4; + assign PORT_A2_ADDR = C1ADDR_TOTAL << 4; + assign PORT_B2_ADDR = D1ADDR_TOTAL << 4; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0 + }; + end + + default: begin + assign PORT_A1_ADDR = A1ADDR_TOTAL; + assign PORT_B1_ADDR = B1ADDR_TOTAL; + assign PORT_A2_ADDR = D1ADDR_TOTAL; + assign PORT_B2_ADDR = C1ADDR_TOTAL; + defparam bram_2x18k.MODE_BITS = { 1'b1, + 11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0 + }; + end + endcase + + assign FLUSH1 = 1'b0; + assign FLUSH2 = 1'b0; + + wire [17:0] PORT_A1_RDATA; + wire [17:0] PORT_B1_RDATA; + wire [17:0] PORT_A2_RDATA; + wire [17:0] PORT_B2_RDATA; + + wire [17:0] PORT_A1_WDATA; + wire [17:0] PORT_B1_WDATA; + wire [17:0] PORT_A2_WDATA; + wire [17:0] PORT_B2_WDATA; + + // Assign read/write data - handle special case for 9bit mode + // parity bit for 9bit mode is placed in R/W port on bit #16 + case (CFG_DBITS) + 9: begin + assign A1DATA = {PORT_A1_RDATA[16], PORT_A1_RDATA[7:0]}; + assign C1DATA = {PORT_A2_RDATA[16], PORT_A2_RDATA[7:0]}; + assign PORT_A1_WDATA = {18{1'b0}}; + assign PORT_B1_WDATA = {B1_WDATA_CMPL[17], B1DATA[8], B1_WDATA_CMPL[16:9], B1DATA[7:0]}; + assign PORT_A2_WDATA = {18{1'b0}}; + assign PORT_B2_WDATA = {D1_WDATA_CMPL[17], D1DATA[8], D1_WDATA_CMPL[16:9], D1DATA[7:0]}; + end + default: begin + assign A1DATA = PORT_A1_RDATA[CFG_DBITS-1:0]; + assign C1DATA = PORT_A2_RDATA[CFG_DBITS-1:0]; + assign PORT_A1_WDATA = {18{1'b1}}; + assign PORT_B1_WDATA = {B1_WDATA_CMPL, B1DATA}; + assign PORT_A2_WDATA = {18{1'b1}}; + assign PORT_B2_WDATA = {D1_WDATA_CMPL, D1DATA}; + + end + endcase + + wire PORT_A1_CLK = CLK1; + wire PORT_A2_CLK = CLK2; + wire PORT_B1_CLK = CLK1; + wire PORT_B2_CLK = CLK2; + + wire PORT_A1_REN = A1EN; + wire PORT_A1_WEN = 1'b0; + wire [CFG_ENABLE_B-1:0] PORT_A1_BE = {PORT_A1_WEN,PORT_A1_WEN}; + + wire PORT_A2_REN = C1EN; + wire PORT_A2_WEN = 1'b0; + wire [CFG_ENABLE_D-1:0] PORT_A2_BE = {PORT_A2_WEN,PORT_A2_WEN}; + + wire PORT_B1_REN = 1'b0; + wire PORT_B1_WEN = B1EN[0]; + wire [CFG_ENABLE_B-1:0] PORT_B1_BE = {B1EN[1],B1EN[0]}; + + wire PORT_B2_REN = 1'b0; + wire PORT_B2_WEN = D1EN[0]; + wire [CFG_ENABLE_D-1:0] PORT_B2_BE = {D1EN[1],D1EN[0]}; + + TDP36K bram_2x18k ( + .WDATA_A1_i(PORT_A1_WDATA), + .RDATA_A1_o(PORT_A1_RDATA), + .ADDR_A1_i(PORT_A1_ADDR), + .CLK_A1_i(PORT_A1_CLK), + .REN_A1_i(PORT_A1_REN), + .WEN_A1_i(PORT_A1_WEN), + .BE_A1_i(PORT_A1_BE), + + .WDATA_A2_i(PORT_A2_WDATA), + .RDATA_A2_o(PORT_A2_RDATA), + .ADDR_A2_i(PORT_A2_ADDR), + .CLK_A2_i(PORT_A2_CLK), + .REN_A2_i(PORT_A2_REN), + .WEN_A2_i(PORT_A2_WEN), + .BE_A2_i(PORT_A2_BE), + + .WDATA_B1_i(PORT_B1_WDATA), + .RDATA_B1_o(PORT_B1_RDATA), + .ADDR_B1_i(PORT_B1_ADDR), + .CLK_B1_i(PORT_B1_CLK), + .REN_B1_i(PORT_B1_REN), + .WEN_B1_i(PORT_B1_WEN), + .BE_B1_i(PORT_B1_BE), + + .WDATA_B2_i(PORT_B2_WDATA), + .RDATA_B2_o(PORT_B2_RDATA), + .ADDR_B2_i(PORT_B2_ADDR), + .CLK_B2_i(PORT_B2_CLK), + .REN_B2_i(PORT_B2_REN), + .WEN_B2_i(PORT_B2_WEN), + .BE_B2_i(PORT_B2_BE), + + .FLUSH1_i(FLUSH1), + .FLUSH2_i(FLUSH2) + ); +endmodule + +module \_$_mem_v2_asymmetric (RD_ADDR, RD_ARST, RD_CLK, RD_DATA, RD_EN, RD_SRST, WR_ADDR, WR_CLK, WR_DATA, WR_EN); + localparam CFG_ABITS = 10; + localparam CFG_DBITS = 36; + localparam CFG_ENABLE_B = 4; + + localparam CLKPOL2 = 1; + localparam CLKPOL3 = 1; + + parameter READ_ADDR_WIDTH = 11; + parameter READ_DATA_WIDTH = 16; + parameter WRITE_ADDR_WIDTH = 10; + parameter WRITE_DATA_WIDTH = 32; + parameter ABITS = 0; + parameter MEMID = 0; + parameter [36863:0] INIT = 36864'bx; + parameter OFFSET = 0; + parameter RD_ARST_VALUE = 0; + parameter RD_CE_OVER_SRST = 0; + parameter RD_CLK_ENABLE = 0; + parameter RD_CLK_POLARITY = 0; + parameter RD_COLLISION_X_MASK = 0; + parameter RD_INIT_VALUE = 0; + parameter RD_PORTS = 0; + parameter RD_SRST_VALUE = 0; + parameter RD_TRANSPARENCY_MASK = 0; + parameter RD_WIDE_CONTINUATION = 0; + parameter SIZE = 0; + parameter WIDTH = 0; + parameter WR_CLK_ENABLE = 0; + parameter WR_CLK_POLARITY = 0; + parameter WR_PORTS = 0; + parameter WR_PRIORITY_MASK = 0; + parameter WR_WIDE_CONTINUATION = 0; + + localparam MODE_36 = 3'b111; // 36 or 32-bit + localparam MODE_18 = 3'b110; // 18 or 16-bit + localparam MODE_9 = 3'b101; // 9 or 8-bit + localparam MODE_4 = 3'b100; // 4-bit + localparam MODE_2 = 3'b010; // 32-bit + localparam MODE_1 = 3'b001; // 32-bit + + input wire RD_CLK; + input wire WR_CLK; + input wire RD_ARST; + input wire RD_SRST; + + input wire [CFG_ABITS-1:0] RD_ADDR; + output wire [CFG_DBITS-1:0] RD_DATA; + input wire RD_EN; + + input wire [CFG_ABITS-1:0] WR_ADDR; + input wire [CFG_DBITS-1:0] WR_DATA; + input wire [CFG_ENABLE_B-1:0] WR_EN; + + wire [14:0] RD_ADDR_15; + wire [14:0] WR_ADDR_15; + + wire [35:0] DOBDO; + + wire [14:CFG_ABITS] RD_ADDR_CMPL; + wire [14:CFG_ABITS] WR_ADDR_CMPL; + wire [35:CFG_DBITS] RD_DATA_CMPL; + wire [35:CFG_DBITS] WR_DATA_CMPL; + + wire [14:0] RD_ADDR_TOTAL; + wire [14:0] WR_ADDR_TOTAL; + wire [35:0] RD_DATA_TOTAL; + wire [35:0] WR_DATA_TOTAL; + + wire FLUSH1; + wire FLUSH2; + + assign RD_ADDR_CMPL = {15-CFG_ABITS{1'b0}}; + assign WR_ADDR_CMPL = {15-CFG_ABITS{1'b0}}; + + assign RD_ADDR_TOTAL = {RD_ADDR_CMPL, RD_ADDR}; + assign WR_ADDR_TOTAL = {WR_ADDR_CMPL, WR_ADDR}; + + assign RD_DATA_TOTAL = {RD_DATA_CMPL, RD_DATA}; + assign WR_DATA_TOTAL = {WR_DATA_CMPL, WR_DATA}; + + case (CFG_DBITS) + 1: begin + assign RD_ADDR_15 = RD_ADDR_TOTAL; + assign WR_ADDR_15 = WR_ADDR_TOTAL; + defparam bram_asymmetric.MODE_BITS = { 1'b0, + 11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0 + }; + end + + 2: begin + assign RD_ADDR_15 = RD_ADDR_TOTAL << 1; + assign WR_ADDR_15 = WR_ADDR_TOTAL << 1; + defparam bram_asymmetric.MODE_BITS = { 1'b0, + 11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0 + }; + end + + 4: begin + assign RD_ADDR_15 = RD_ADDR_TOTAL << 2; + assign WR_ADDR_15 = WR_ADDR_TOTAL << 2; + defparam bram_asymmetric.MODE_BITS = { 1'b0, + 11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0 + }; + end + 8, 9: begin + assign RD_ADDR_15 = RD_ADDR_TOTAL << 3; + assign WR_ADDR_15 = WR_ADDR_TOTAL << 3; + defparam bram_asymmetric.MODE_BITS = { 1'b0, + 11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0 + }; + end + + 16, 18: begin + assign RD_ADDR_15 = RD_ADDR_TOTAL << 4; + assign WR_ADDR_15 = WR_ADDR_TOTAL << 4; + defparam bram_asymmetric.MODE_BITS = { 1'b0, + 11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0 + }; + end + 32, 36: begin + assign RD_ADDR_15 = RD_ADDR_TOTAL << 5; + assign WR_ADDR_15 = WR_ADDR_TOTAL << 5; + defparam bram_asymmetric.MODE_BITS = { 1'b0, + 11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0 + }; + end + default: begin + assign RD_ADDR_15 = RD_ADDR_TOTAL; + assign WR_ADDR_15 = WR_ADDR_TOTAL; + defparam bram_asymmetric.MODE_BITS = { 1'b0, + 11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0, + 12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0 + }; + end + endcase + + assign FLUSH1 = 1'b0; + assign FLUSH2 = 1'b0; + + TDP36K bram_asymmetric ( + .RESET_ni(1'b1), + .WDATA_A1_i(18'h3FFFF), + .WDATA_A2_i(18'h3FFFF), + .RDATA_A1_o(RD_DATA_TOTAL[17:0]), + .RDATA_A2_o(RD_DATA_TOTAL[35:18]), + .ADDR_A1_i(RD_ADDR_15), + .ADDR_A2_i(RD_ADDR_15), + .CLK_A1_i(RD_CLK), + .CLK_A2_i(RD_CLK), + .REN_A1_i(RD_EN), + .REN_A2_i(RD_EN), + .WEN_A1_i(1'b0), + .WEN_A2_i(1'b0), + .BE_A1_i({RD_EN, RD_EN}), + .BE_A2_i({RD_EN, RD_EN}), + + .WDATA_B1_i(WR_DATA[17:0]), + .WDATA_B2_i(WR_DATA[35:18]), + .RDATA_B1_o(DOBDO[17:0]), + .RDATA_B2_o(DOBDO[35:18]), + .ADDR_B1_i(WR_ADDR_15), + .ADDR_B2_i(WR_ADDR_15), + .CLK_B1_i(WR_CLK), + .CLK_B2_i(WR_CLK), + .REN_B1_i(1'b0), + .REN_B2_i(1'b0), + .WEN_B1_i(WR_EN[0]), + .WEN_B2_i(WR_EN[0]), + .BE_B1_i(WR_EN[1:0]), + .BE_B2_i(WR_EN[3:2]), + + .FLUSH1_i(FLUSH1), + .FLUSH2_i(FLUSH2) + ); +endmodule + +// ============================================================================ +// TDP36K write width 1 functional modes + +module TDP36K_BRAM_WR_X1_RD_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X1_RD_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X1_RD_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X1_RD_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X1_RD_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X1_RD_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +// ============================================================================ +// TDP36K write width 2 functional modes + +module TDP36K_BRAM_WR_X2_RD_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X2_RD_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X2_RD_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X2_RD_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X2_RD_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X2_RD_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +// ============================================================================ +// TDP36K write width 4 functional modes + +module TDP36K_BRAM_WR_X4_RD_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X4_RD_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X4_RD_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X4_RD_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X4_RD_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X4_RD_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +// ============================================================================ +// TDP36K write width 9 functional modes + +module TDP36K_BRAM_WR_X9_RD_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X9_RD_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X9_RD_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X9_RD_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X9_RD_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X9_RD_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +// ============================================================================ +// TDP36K write width 18 functional modes + +module TDP36K_BRAM_WR_X18_RD_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X18_RD_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X18_RD_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X18_RD_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X18_RD_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X18_RD_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +// ============================================================================ +// TDP36K write width 36 functional modes + +module TDP36K_BRAM_WR_X36_RD_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X36_RD_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X36_RD_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X36_RD_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X36_RD_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X36_RD_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +// ============================================================================ +// TDP36K (split mode) write width 1 functional modes + +module TDP36K_BRAM_WR_X1_RD_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X1_RD_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X1_RD_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X1_RD_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X1_RD_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +// ============================================================================ +// TDP36K (split mode) write width 2 functional modes + +module TDP36K_BRAM_WR_X2_RD_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X2_RD_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X2_RD_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X2_RD_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X2_RD_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +// ============================================================================ +// TDP36K (split mode) write width 4 functional modes + +module TDP36K_BRAM_WR_X4_RD_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X4_RD_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X4_RD_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X4_RD_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X4_RD_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +// ============================================================================ +// TDP36K (split mode) write width 9 functional modes + +module TDP36K_BRAM_WR_X9_RD_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X9_RD_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X9_RD_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X9_RD_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X9_RD_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +// ============================================================================ +// TDP36K (split mode) write width 18 functional modes + +module TDP36K_BRAM_WR_X18_RD_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X18_RD_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X18_RD_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X18_RD_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + +module TDP36K_BRAM_WR_X18_RD_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +endmodule + diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v index 26ac9ae..0818d36 100644 --- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v +++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v @@ -27,6 +27,11 @@ module sh_dff( initial Q <= 1'b0; always @(posedge C) Q <= D; + + specify + (posedge C => (Q +: D)) = 0; + $setuphold(posedge C, D, 0, 0); + endspecify endmodule @@ -40,87 +45,15 @@ module adder_carry( ); assign sumout = p ^ cin; assign cout = p ? cin : g; - -endmodule - -(* abc9_box, lib_whitebox *) -module adder_lut5( - output wire lut5_out, - (* abc9_carry *) - output wire cout, - input wire [0:4] in, - (* abc9_carry *) - input wire cin -); - parameter [0:15] LUT=0; - parameter IN2_IS_CIN = 0; - - wire [0:4] li = (IN2_IS_CIN) ? {in[0], in[1], cin, in[3], in[4]} : {in[0], in[1], in[2], in[3],in[4]}; - - // Output function - wire [0:15] s1 = li[0] ? - {LUT[0], LUT[2], LUT[4], LUT[6], LUT[8], LUT[10], LUT[12], LUT[14], LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30]}: - {LUT[1], LUT[3], LUT[5], LUT[7], LUT[9], LUT[11], LUT[13], LUT[15], LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31]}; - - wire [0:7] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6], s1[8], s1[10], s1[12], s1[14]} : - {s1[1], s1[3], s1[5], s1[7], s1[9], s1[11], s1[13], s1[15]}; - - wire [0:3] s3 = li[2] ? {s2[0], s2[2], s2[4], s2[6]} : {s2[1], s2[3], s2[5], s2[7]}; - wire [0:1] s4 = li[3] ? {s3[0], s3[2]} : {s3[1], s3[3]}; - - assign lut5_out = li[4] ? s4[0] : s4[1]; - - // Carry out function - assign cout = (s3[2]) ? cin : s3[3]; - -endmodule - -(* abc9_lut=1, lib_whitebox *) -module frac_lut6( - input wire [0:5] in, - output wire [0:3] lut4_out, - output wire [0:1] lut5_out, - output wire lut6_out -); - parameter [0:63] LUT = 0; - // Effective LUT input - wire [0:5] li = in; - - // Output function - wire [0:31] s1 = li[0] ? - {LUT[0] , LUT[2] , LUT[4] , LUT[6] , LUT[8] , LUT[10], LUT[12], LUT[14], - LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30], - LUT[32], LUT[34], LUT[36], LUT[38], LUT[40], LUT[42], LUT[44], LUT[46], - LUT[48], LUT[50], LUT[52], LUT[54], LUT[56], LUT[58], LUT[60], LUT[62]}: - {LUT[1] , LUT[3] , LUT[5] , LUT[7] , LUT[9] , LUT[11], LUT[13], LUT[15], - LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31], - LUT[33], LUT[35], LUT[37], LUT[39], LUT[41], LUT[43], LUT[45], LUT[47], - LUT[49], LUT[51], LUT[53], LUT[55], LUT[57], LUT[59], LUT[61], LUT[63]}; - - wire [0:15] s2 = li[1] ? - {s1[0] , s1[2] , s1[4] , s1[6] , s1[8] , s1[10], s1[12], s1[14], - s1[16], s1[18], s1[20], s1[22], s1[24], s1[26], s1[28], s1[30]}: - {s1[1] , s1[3] , s1[5] , s1[7] , s1[9] , s1[11], s1[13], s1[15], - s1[17], s1[19], s1[21], s1[23], s1[25], s1[27], s1[29], s1[31]}; - - wire [0:7] s3 = li[2] ? - {s2[0], s2[2], s2[4], s2[6], s2[8], s2[10], s2[12], s2[14]}: - {s2[1], s2[3], s2[5], s2[7], s2[9], s2[11], s2[13], s2[15]}; - - wire [0:3] s4 = li[3] ? {s3[0], s3[2], s3[4], s3[6]}: - {s3[1], s3[3], s3[5], s3[7]}; - - wire [0:1] s5 = li[4] ? {s4[0], s4[2]} : {s4[1], s4[3]}; - - assign lut4_out[0] = s4[0]; - assign lut4_out[1] = s4[1]; - assign lut4_out[2] = s4[2]; - assign lut4_out[3] = s4[3]; - - assign lut5_out[0] = s5[0]; - assign lut5_out[1] = s5[1]; - - assign lut6_out = li[5] ? s5[0] : s5[1]; + + specify + (p => sumout) = 0; + (g => sumout) = 0; + (cin => sumout) = 0; + (p => cout) = 0; + (g => cout) = 0; + (cin => cout) = 0; + endspecify endmodule @@ -136,6 +69,11 @@ module dff( always @(posedge C) Q <= D; + specify + (posedge C=>(Q+:D)) = 0; + $setuphold(posedge C, D, 0, 0); + endspecify + endmodule (* abc9_flop, lib_whitebox *) @@ -149,6 +87,11 @@ module dffn( always @(negedge C) Q <= D; + + specify + (negedge C=>(Q+:D)) = 0; + $setuphold(negedge C, D, 0, 0); + endspecify endmodule @@ -172,6 +115,18 @@ module dffsre( else if (E) Q <= D; + specify + (posedge C => (Q +: D)) = 0; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(posedge C, D, 0, 0); + $setuphold(posedge C, E, 0, 0); + $setuphold(posedge C, R, 0, 0); + $setuphold(posedge C, S, 0, 0); + $recrem(posedge R, posedge C, 0, 0); + $recrem(posedge S, posedge C, 0, 0); + endspecify + endmodule (* abc9_flop, lib_whitebox *) @@ -193,6 +148,18 @@ module dffnsre( Q <= 1'b1; else if (E) Q <= D; + + specify + (negedge C => (Q +: D)) = 0; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(negedge C, D, 0, 0); + $setuphold(negedge C, E, 0, 0); + $setuphold(negedge C, R, 0, 0); + $setuphold(negedge C, S, 0, 0); + $recrem(posedge R, negedge C, 0, 0); + $recrem(posedge S, negedge C, 0, 0); + endspecify endmodule @@ -215,6 +182,14 @@ module sdffsre( Q <= 1'b1; else if (E) Q <= D; + + specify + (posedge C => (Q +: D)) = 0; + $setuphold(posedge C, D, 0, 0); + $setuphold(posedge C, R, 0, 0); + $setuphold(posedge C, S, 0, 0); + $setuphold(posedge C, E, 0, 0); + endspecify endmodule @@ -237,6 +212,14 @@ module sdffnsre( Q <= 1'b1; else if (E) Q <= D; + + specify + (negedge C => (Q +: D)) = 0; + $setuphold(negedge C, D, 0, 0); + $setuphold(negedge C, R, 0, 0); + $setuphold(negedge C, S, 0, 0); + $setuphold(negedge C, E, 0, 0); + endspecify endmodule @@ -260,6 +243,14 @@ module latchsre ( else if (E && G) Q <= D; end + + specify + (posedge G => (Q +: D)) = 0; + $setuphold(posedge G, D, 0, 0); + $setuphold(posedge G, E, 0, 0); + $setuphold(posedge G, R, 0, 0); + $setuphold(posedge G, S, 0, 0); + endspecify endmodule @@ -283,1409 +274,14 @@ module latchnsre ( else if (E && !G) Q <= D; end + + specify + (negedge G => (Q +: D)) = 0; + $setuphold(negedge G, D, 0, 0); + $setuphold(negedge G, E, 0, 0); + $setuphold(negedge G, R, 0, 0); + $setuphold(negedge G, S, 0, 0); + endspecify endmodule - -module TDP_BRAM18 ( - (* clkbuf_sink *) - input wire CLOCKA, - (* clkbuf_sink *) - input wire CLOCKB, - input wire READENABLEA, - input wire READENABLEB, - input wire [13:0] ADDRA, - input wire [13:0] ADDRB, - input wire [15:0] WRITEDATAA, - input wire [15:0] WRITEDATAB, - input wire [1:0] WRITEDATAAP, - input wire [1:0] WRITEDATABP, - input wire WRITEENABLEA, - input wire WRITEENABLEB, - input wire [1:0] BYTEENABLEA, - input wire [1:0] BYTEENABLEB, - //input wire [2:0] WRITEDATAWIDTHA, - //input wire [2:0] WRITEDATAWIDTHB, - //input wire [2:0] READDATAWIDTHA, - //input wire [2:0] READDATAWIDTHB, - output wire [15:0] READDATAA, - output wire [15:0] READDATAB, - output wire [1:0] READDATAAP, - output wire [1:0] READDATABP -); - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - -endmodule - -module TDP36K ( - RESET_ni, - WEN_A1_i, - WEN_B1_i, - REN_A1_i, - REN_B1_i, - CLK_A1_i, - CLK_B1_i, - BE_A1_i, - BE_B1_i, - ADDR_A1_i, - ADDR_B1_i, - WDATA_A1_i, - WDATA_B1_i, - RDATA_A1_o, - RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, - WEN_B2_i, - REN_A2_i, - REN_B2_i, - CLK_A2_i, - CLK_B2_i, - BE_A2_i, - BE_B2_i, - ADDR_A2_i, - ADDR_B2_i, - WDATA_A2_i, - WDATA_B2_i, - RDATA_A2_o, - RDATA_B2_o, - FLUSH2_i -); - parameter [80:0] MODE_BITS = 81'd0; - - // First 18K RAMFIFO (41 bits) - localparam [ 0:0] SYNC_FIFO1_i = MODE_BITS[0]; - localparam [ 2:0] RMODE_A1_i = MODE_BITS[3 : 1]; - localparam [ 2:0] RMODE_B1_i = MODE_BITS[6 : 4]; - localparam [ 2:0] WMODE_A1_i = MODE_BITS[9 : 7]; - localparam [ 2:0] WMODE_B1_i = MODE_BITS[12:10]; - localparam [ 0:0] FMODE1_i = MODE_BITS[13]; - localparam [ 0:0] POWERDN1_i = MODE_BITS[14]; - localparam [ 0:0] SLEEP1_i = MODE_BITS[15]; - localparam [ 0:0] PROTECT1_i = MODE_BITS[16]; - localparam [11:0] UPAE1_i = MODE_BITS[28:17]; - localparam [11:0] UPAF1_i = MODE_BITS[40:29]; - - // Second 18K RAMFIFO (39 bits) - localparam [ 0:0] SYNC_FIFO2_i = MODE_BITS[41]; - localparam [ 2:0] RMODE_A2_i = MODE_BITS[44:42]; - localparam [ 2:0] RMODE_B2_i = MODE_BITS[47:45]; - localparam [ 2:0] WMODE_A2_i = MODE_BITS[50:48]; - localparam [ 2:0] WMODE_B2_i = MODE_BITS[53:51]; - localparam [ 0:0] FMODE2_i = MODE_BITS[54]; - localparam [ 0:0] POWERDN2_i = MODE_BITS[55]; - localparam [ 0:0] SLEEP2_i = MODE_BITS[56]; - localparam [ 0:0] PROTECT2_i = MODE_BITS[57]; - localparam [10:0] UPAE2_i = MODE_BITS[68:58]; - localparam [10:0] UPAF2_i = MODE_BITS[79:69]; - - // Split (1 bit) - localparam [ 0:0] SPLIT_i = MODE_BITS[80]; - - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - input wire RESET_ni; - input wire WEN_A1_i; - input wire WEN_B1_i; - input wire REN_A1_i; - input wire REN_B1_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - input wire [1:0] BE_A1_i; - input wire [1:0] BE_B1_i; - input wire [14:0] ADDR_A1_i; - input wire [14:0] ADDR_B1_i; - input wire [17:0] WDATA_A1_i; - input wire [17:0] WDATA_B1_i; - output reg [17:0] RDATA_A1_o; - output reg [17:0] RDATA_B1_o; - input wire FLUSH1_i; - input wire WEN_A2_i; - input wire WEN_B2_i; - input wire REN_A2_i; - input wire REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - input wire [1:0] BE_A2_i; - input wire [1:0] BE_B2_i; - input wire [13:0] ADDR_A2_i; - input wire [13:0] ADDR_B2_i; - input wire [17:0] WDATA_A2_i; - input wire [17:0] WDATA_B2_i; - output reg [17:0] RDATA_A2_o; - output reg [17:0] RDATA_B2_o; - input wire FLUSH2_i; - wire EMPTY2; - wire EPO2; - wire EWM2; - wire FULL2; - wire FMO2; - wire FWM2; - wire EMPTY1; - wire EPO1; - wire EWM1; - wire FULL1; - wire FMO1; - wire FWM1; - wire UNDERRUN1; - wire OVERRUN1; - wire UNDERRUN2; - wire OVERRUN2; - wire UNDERRUN3; - wire OVERRUN3; - wire EMPTY3; - wire EPO3; - wire EWM3; - wire FULL3; - wire FMO3; - wire FWM3; - wire ram_fmode1; - wire ram_fmode2; - wire [17:0] ram_rdata_a1; - wire [17:0] ram_rdata_b1; - wire [17:0] ram_rdata_a2; - wire [17:0] ram_rdata_b2; - reg [17:0] ram_wdata_a1; - reg [17:0] ram_wdata_b1; - reg [17:0] ram_wdata_a2; - reg [17:0] ram_wdata_b2; - reg [14:0] laddr_a1; - reg [14:0] laddr_b1; - wire [13:0] ram_addr_a1; - wire [13:0] ram_addr_b1; - wire [13:0] ram_addr_a2; - wire [13:0] ram_addr_b2; - wire smux_clk_a1; - wire smux_clk_b1; - wire smux_clk_a2; - wire smux_clk_b2; - reg [1:0] ram_be_a1; - reg [1:0] ram_be_a2; - reg [1:0] ram_be_b1; - reg [1:0] ram_be_b2; - wire [2:0] ram_rmode_a1; - wire [2:0] ram_wmode_a1; - wire [2:0] ram_rmode_b1; - wire [2:0] ram_wmode_b1; - wire [2:0] ram_rmode_a2; - wire [2:0] ram_wmode_a2; - wire [2:0] ram_rmode_b2; - wire [2:0] ram_wmode_b2; - wire ram_ren_a1; - wire ram_ren_b1; - wire ram_ren_a2; - wire ram_ren_b2; - wire ram_wen_a1; - wire ram_wen_b1; - wire ram_wen_a2; - wire ram_wen_b2; - wire ren_o; - wire [11:0] ff_raddr; - wire [11:0] ff_waddr; - reg [35:0] fifo_rdata; - wire [1:0] fifo_rmode; - wire [1:0] fifo_wmode; - wire [1:0] bwl; - wire [17:0] pl_dout0; - wire [17:0] pl_dout1; - wire sclk_a1; - wire sclk_b1; - wire sclk_a2; - wire sclk_b2; - wire sreset; - wire flush1; - wire flush2; - assign sreset = RESET_ni; - assign flush1 = ~FLUSH1_i; - assign flush2 = ~FLUSH2_i; - assign ram_fmode1 = FMODE1_i & SPLIT_i; - assign ram_fmode2 = FMODE2_i & SPLIT_i; - assign smux_clk_a1 = CLK_A1_i; - assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i); - assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i); - assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); - assign sclk_a1 = smux_clk_a1; - assign sclk_a2 = smux_clk_a2; - assign sclk_b1 = smux_clk_b1; - assign sclk_b2 = smux_clk_b2; - assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i)); - assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i)); - assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i)); - assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i)); - localparam MODE_36 = 3'b011; - assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4]))); - assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4]))); - assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4])); - assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4])); - assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); - assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); - assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); - assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); - assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3])); - localparam MODE_18 = 3'b010; - localparam MODE_9 = 3'b001; - always @(*) begin : WDATA_SEL - case (SPLIT_i) - 1: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A2_i; - ram_wdata_b1 = WDATA_B1_i; - ram_wdata_b2 = WDATA_B2_i; - ram_be_a2 = BE_A2_i; - ram_be_b2 = BE_B2_i; - ram_be_a1 = BE_A1_i; - ram_be_b1 = BE_B1_i; - end - 0: begin - case (WMODE_A1_i) - MODE_36: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A2_i; - ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i); - ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); - end - MODE_18: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A1_i; - ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i); - ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i); - end - MODE_9: begin - ram_wdata_a1[7:0] = WDATA_A1_i[7:0]; - ram_wdata_a1[16] = WDATA_A1_i[16]; - ram_wdata_a1[15:8] = WDATA_A1_i[7:0]; - ram_wdata_a1[17] = WDATA_A1_i[16]; - ram_wdata_a2[7:0] = WDATA_A1_i[7:0]; - ram_wdata_a2[16] = WDATA_A1_i[16]; - ram_wdata_a2[15:8] = WDATA_A1_i[7:0]; - ram_wdata_a2[17] = WDATA_A1_i[16]; - case (bwl) - 0: {ram_be_a2, ram_be_a1} = 4'b0001; - 1: {ram_be_a2, ram_be_a1} = 4'b0010; - 2: {ram_be_a2, ram_be_a1} = 4'b0100; - 3: {ram_be_a2, ram_be_a1} = 4'b1000; - endcase - end - default: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A1_i; - ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i); - ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); - end - endcase - case (WMODE_B1_i) - MODE_36: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i); - ram_be_b2 = BE_B2_i; - ram_be_b1 = BE_B1_i; - end - MODE_18: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_be_b1 = BE_B1_i; - ram_be_b2 = BE_B1_i; - end - MODE_9: begin - ram_wdata_b1[7:0] = WDATA_B1_i[7:0]; - ram_wdata_b1[16] = WDATA_B1_i[16]; - ram_wdata_b1[15:8] = WDATA_B1_i[7:0]; - ram_wdata_b1[17] = WDATA_B1_i[16]; - ram_wdata_b2[7:0] = WDATA_B1_i[7:0]; - ram_wdata_b2[16] = WDATA_B1_i[16]; - ram_wdata_b2[15:8] = WDATA_B1_i[7:0]; - ram_wdata_b2[17] = WDATA_B1_i[16]; - case (ADDR_B1_i[4:3]) - 0: {ram_be_b2, ram_be_b1} = 4'b0001; - 1: {ram_be_b2, ram_be_b1} = 4'b0010; - 2: {ram_be_b2, ram_be_b1} = 4'b0100; - 3: {ram_be_b2, ram_be_b1} = 4'b1000; - endcase - end - default: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_be_b2 = BE_B1_i; - ram_be_b1 = BE_B1_i; - end - endcase - end - endcase - end - assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); - assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); - assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); - assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); - assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); - assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); - assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); - assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); - always @(*) begin : FIFO_READ_SEL - case (RMODE_B1_i) - MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; - MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1}); - MODE_9: - case (ff_raddr[1:0]) - 0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}; - 1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]}; - 2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]}; - 3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]}; - endcase - default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1}; - endcase - end - localparam MODE_1 = 3'b101; - localparam MODE_2 = 3'b110; - localparam MODE_4 = 3'b100; - always @(*) begin : RDATA_SEL - case (SPLIT_i) - 1: begin - RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1); - RDATA_B1_o = ram_rdata_b1; - RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2); - RDATA_B2_o = ram_rdata_b2; - end - 0: begin - if (FMODE1_i) begin - RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3}; - RDATA_A2_o = 18'b000000000000000000; - end - else - case (RMODE_A1_i) - MODE_36: begin - RDATA_A1_o = {ram_rdata_a1[17:0]}; - RDATA_A2_o = {ram_rdata_a2[17:0]}; - end - MODE_18: begin - RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1); - RDATA_A2_o = 18'b000000000000000000; - end - MODE_9: begin - RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}}); - RDATA_A2_o = 18'b000000000000000000; - end - MODE_4: begin - RDATA_A2_o = 18'b000000000000000000; - RDATA_A1_o[17:4] = 14'b00000000000000; - RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]); - end - MODE_2: begin - RDATA_A2_o = 18'b000000000000000000; - RDATA_A1_o[17:2] = 16'b0000000000000000; - RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]); - end - MODE_1: begin - RDATA_A2_o = 18'b000000000000000000; - RDATA_A1_o[17:1] = 17'b00000000000000000; - RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]); - end - default: begin - RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]}; - RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]}; - end - endcase - case (RMODE_B1_i) - MODE_36: begin - RDATA_B1_o = {ram_rdata_b1}; - RDATA_B2_o = {ram_rdata_b2}; - end - MODE_18: begin - RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1)); - RDATA_B2_o = 18'b000000000000000000; - end - MODE_9: begin - RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]})); - RDATA_B2_o = 18'b000000000000000000; - end - MODE_4: begin - RDATA_B2_o = 18'b000000000000000000; - RDATA_B1_o[17:4] = 14'b00000000000000; - RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]); - end - MODE_2: begin - RDATA_B2_o = 18'b000000000000000000; - RDATA_B1_o[17:2] = 16'b0000000000000000; - RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]); - end - MODE_1: begin - RDATA_B2_o = 18'b000000000000000000; - RDATA_B1_o[17:1] = 17'b00000000000000000; - RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]); - end - default: begin - RDATA_B1_o = ram_rdata_b1; - RDATA_B2_o = ram_rdata_b2; - end - endcase - end - endcase - end - always @(posedge sclk_a1 or negedge sreset) - if (sreset == 0) - laddr_a1 <= 1'sb0; - else - laddr_a1 <= ADDR_A1_i; - always @(posedge sclk_b1 or negedge sreset) - if (sreset == 0) - laddr_b1 <= 1'sb0; - else - laddr_b1 <= ADDR_B1_i; - assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00))); - assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00))); - fifo_ctl #( - .ADDR_WIDTH(12), - .FIFO_WIDTH(3'd4), - .DEPTH(7) - ) fifo36_ctl( - .rclk(sclk_b1), - .rst_R_n(flush1), - .wclk(sclk_a1), - .rst_W_n(flush1), - .ren(REN_B1_i), - .wen(ram_wen_a1), - .sync(SYNC_FIFO1_i), - .rmode(fifo_rmode), - .wmode(fifo_wmode), - .ren_o(ren_o), - .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}), - .raddr(ff_raddr), - .waddr(ff_waddr), - .upaf(UPAF1_i), - .upae(UPAE1_i) - ); - TDP18K_FIFO #( - .UPAF_i(UPAF1_i[10:0]), - .UPAE_i(UPAE1_i[10:0]), - .SYNC_FIFO_i(SYNC_FIFO1_i), - .POWERDN_i(POWERDN1_i), - .SLEEP_i(SLEEP1_i), - .PROTECT_i(PROTECT1_i) - )u1( - .RMODE_A_i(ram_rmode_a1), - .RMODE_B_i(ram_rmode_b1), - .WMODE_A_i(ram_wmode_a1), - .WMODE_B_i(ram_wmode_b1), - .WEN_A_i(ram_wen_a1), - .WEN_B_i(ram_wen_b1), - .REN_A_i(ram_ren_a1), - .REN_B_i(ram_ren_b1), - .CLK_A_i(sclk_a1), - .CLK_B_i(sclk_b1), - .BE_A_i(ram_be_a1), - .BE_B_i(ram_be_b1), - .ADDR_A_i(ram_addr_a1), - .ADDR_B_i(ram_addr_b1), - .WDATA_A_i(ram_wdata_a1), - .WDATA_B_i(ram_wdata_b1), - .RDATA_A_o(ram_rdata_a1), - .RDATA_B_o(ram_rdata_b1), - .EMPTY_o(EMPTY1), - .EPO_o(EPO1), - .EWM_o(EWM1), - .UNDERRUN_o(UNDERRUN1), - .FULL_o(FULL1), - .FMO_o(FMO1), - .FWM_o(FWM1), - .OVERRUN_o(OVERRUN1), - .FLUSH_ni(flush1), - .FMODE_i(ram_fmode1) - ); - TDP18K_FIFO #( - .UPAF_i(UPAF2_i), - .UPAE_i(UPAE2_i), - .SYNC_FIFO_i(SYNC_FIFO2_i), - .POWERDN_i(POWERDN2_i), - .SLEEP_i(SLEEP2_i), - .PROTECT_i(PROTECT2_i) - )u2( - .RMODE_A_i(ram_rmode_a2), - .RMODE_B_i(ram_rmode_b2), - .WMODE_A_i(ram_wmode_a2), - .WMODE_B_i(ram_wmode_b2), - .WEN_A_i(ram_wen_a2), - .WEN_B_i(ram_wen_b2), - .REN_A_i(ram_ren_a2), - .REN_B_i(ram_ren_b2), - .CLK_A_i(sclk_a2), - .CLK_B_i(sclk_b2), - .BE_A_i(ram_be_a2), - .BE_B_i(ram_be_b2), - .ADDR_A_i(ram_addr_a2), - .ADDR_B_i(ram_addr_b2), - .WDATA_A_i(ram_wdata_a2), - .WDATA_B_i(ram_wdata_b2), - .RDATA_A_o(ram_rdata_a2), - .RDATA_B_o(ram_rdata_b2), - .EMPTY_o(EMPTY2), - .EPO_o(EPO2), - .EWM_o(EWM2), - .UNDERRUN_o(UNDERRUN2), - .FULL_o(FULL2), - .FMO_o(FMO2), - .FWM_o(FWM2), - .OVERRUN_o(OVERRUN2), - .FLUSH_ni(flush2), - .FMODE_i(ram_fmode2) - ); -endmodule - -module BRAM2x18_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, CLK3, CLK4, D1ADDR, D1DATA, D1EN, E1ADDR, E1DATA, E1EN, F1ADDR, F1DATA, F1EN, G1ADDR, G1DATA, G1EN, H1ADDR, H1DATA, H1EN); - parameter CFG_ABITS = 11; - parameter CFG_DBITS = 18; - parameter CFG_ENABLE_B = 4; - parameter CFG_ENABLE_D = 4; - parameter CFG_ENABLE_F = 4; - parameter CFG_ENABLE_H = 4; - - parameter CLKPOL2 = 1; - parameter CLKPOL3 = 1; - parameter [18431:0] INIT0 = 18432'bx; - parameter [18431:0] INIT1 = 18432'bx; - - localparam MODE_36 = 3'b011; // 36- or 32-bit - localparam MODE_18 = 3'b010; // 18- or 16-bit - localparam MODE_9 = 3'b001; // 9- or 8-bit - localparam MODE_4 = 3'b100; // 4-bit - localparam MODE_2 = 3'b110; // 2-bit - localparam MODE_1 = 3'b101; // 1-bit - - input CLK1; - input CLK2; - input CLK3; - input CLK4; - - input [CFG_ABITS-1:0] A1ADDR; - output [CFG_DBITS-1:0] A1DATA; - input A1EN; - - input [CFG_ABITS-1:0] B1ADDR; - input [CFG_DBITS-1:0] B1DATA; - input [CFG_ENABLE_B-1:0] B1EN; - - input [CFG_ABITS-1:0] C1ADDR; - output [CFG_DBITS-1:0] C1DATA; - input C1EN; - - input [CFG_ABITS-1:0] D1ADDR; - input [CFG_DBITS-1:0] D1DATA; - input [CFG_ENABLE_D-1:0] D1EN; - - input [CFG_ABITS-1:0] E1ADDR; - output [CFG_DBITS-1:0] E1DATA; - input E1EN; - - input [CFG_ABITS-1:0] F1ADDR; - input [CFG_DBITS-1:0] F1DATA; - input [CFG_ENABLE_F-1:0] F1EN; - - input [CFG_ABITS-1:0] G1ADDR; - output [CFG_DBITS-1:0] G1DATA; - input G1EN; - - input [CFG_ABITS-1:0] H1ADDR; - input [CFG_DBITS-1:0] H1DATA; - input [CFG_ENABLE_H-1:0] H1EN; - - wire FLUSH1; - wire FLUSH2; - wire SPLIT; - - wire [13:CFG_ABITS] A1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] B1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] C1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] D1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] E1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] F1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] G1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] H1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - - wire [13:0] A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR}; - wire [13:0] B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR}; - wire [13:0] C1ADDR_TOTAL = {C1ADDR_CMPL, C1ADDR}; - wire [13:0] D1ADDR_TOTAL = {D1ADDR_CMPL, D1ADDR}; - wire [13:0] E1ADDR_TOTAL = {E1ADDR_CMPL, E1ADDR}; - wire [13:0] F1ADDR_TOTAL = {F1ADDR_CMPL, F1ADDR}; - wire [13:0] G1ADDR_TOTAL = {G1ADDR_CMPL, G1ADDR}; - wire [13:0] H1ADDR_TOTAL = {H1ADDR_CMPL, H1ADDR}; - - wire [17:CFG_DBITS] A1_RDATA_CMPL; - wire [17:CFG_DBITS] C1_RDATA_CMPL; - wire [17:CFG_DBITS] E1_RDATA_CMPL; - wire [17:CFG_DBITS] G1_RDATA_CMPL; - - wire [17:CFG_DBITS] B1_WDATA_CMPL; - wire [17:CFG_DBITS] D1_WDATA_CMPL; - wire [17:CFG_DBITS] F1_WDATA_CMPL; - wire [17:CFG_DBITS] H1_WDATA_CMPL; - - wire [13:0] PORT_A1_ADDR; - wire [13:0] PORT_A2_ADDR; - wire [13:0] PORT_B1_ADDR; - wire [13:0] PORT_B2_ADDR; - - case (CFG_DBITS) - 1: begin - assign PORT_A1_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 14'd0); - assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0); - assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0); - assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0); - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0 - }; - end - - 2: begin - assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 1) : (B1EN ? (B1ADDR_TOTAL << 1) : 14'd0); - assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 1) : (D1EN ? (D1ADDR_TOTAL << 1) : 14'd0); - assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 1) : (F1EN ? (F1ADDR_TOTAL << 1) : 14'd0); - assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 1) : (H1EN ? (H1ADDR_TOTAL << 1) : 14'd0); - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0 - }; - end - - 4: begin - assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 2) : (B1EN ? (B1ADDR_TOTAL << 2) : 14'd0); - assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 2) : (D1EN ? (D1ADDR_TOTAL << 2) : 14'd0); - assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 2) : (F1EN ? (F1ADDR_TOTAL << 2) : 14'd0); - assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 2) : (H1EN ? (H1ADDR_TOTAL << 2) : 14'd0); - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0 - }; - end - - 8, 9: begin - assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 3) : (B1EN ? (B1ADDR_TOTAL << 3) : 14'd0); - assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 3) : (D1EN ? (D1ADDR_TOTAL << 3) : 14'd0); - assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 3) : (F1EN ? (F1ADDR_TOTAL << 3) : 14'd0); - assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 3) : (H1EN ? (H1ADDR_TOTAL << 3) : 14'd0); - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0 - }; - end - - 16, 18: begin - assign PORT_A1_ADDR = A1EN ? (A1ADDR_TOTAL << 4) : (B1EN ? (B1ADDR_TOTAL << 4) : 14'd0); - assign PORT_B1_ADDR = C1EN ? (C1ADDR_TOTAL << 4) : (D1EN ? (D1ADDR_TOTAL << 4) : 14'd0); - assign PORT_A2_ADDR = E1EN ? (E1ADDR_TOTAL << 4) : (F1EN ? (F1ADDR_TOTAL << 4) : 14'd0); - assign PORT_B2_ADDR = G1EN ? (G1ADDR_TOTAL << 4) : (H1EN ? (H1ADDR_TOTAL << 4) : 14'd0); - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0 - }; - end - - default: begin - assign PORT_A1_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 14'd0); - assign PORT_B1_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 14'd0); - assign PORT_A2_ADDR = E1EN ? E1ADDR_TOTAL : (F1EN ? F1ADDR_TOTAL : 14'd0); - assign PORT_B2_ADDR = G1EN ? G1ADDR_TOTAL : (H1EN ? H1ADDR_TOTAL : 14'd0); - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0 - }; - end - endcase - - assign FLUSH1 = 1'b0; - assign FLUSH2 = 1'b0; - - wire [17:0] PORT_A1_RDATA = {A1_RDATA_CMPL, A1DATA}; - wire [17:0] PORT_B1_RDATA = {C1_RDATA_CMPL, C1DATA}; - wire [17:0] PORT_A2_RDATA = {E1_RDATA_CMPL, E1DATA}; - wire [17:0] PORT_B2_RDATA = {G1_RDATA_CMPL, G1DATA}; - - wire [17:0] PORT_A1_WDATA = {B1_WDATA_CMPL, B1DATA}; - wire [17:0] PORT_B1_WDATA = {D1_WDATA_CMPL, D1DATA}; - wire [17:0] PORT_A2_WDATA = {F1_WDATA_CMPL, F1DATA}; - wire [17:0] PORT_B2_WDATA = {H1_WDATA_CMPL, H1DATA}; - - wire PORT_A1_CLK = CLK1; - wire PORT_A2_CLK = CLK3; - wire PORT_B1_CLK = CLK2; - wire PORT_B2_CLK = CLK4; - - wire PORT_A1_REN = A1EN; - wire PORT_A1_WEN = B1EN[0]; - wire [CFG_ENABLE_B-1:0] PORT_A1_BE = {B1EN[1],B1EN[0]}; - - wire PORT_A2_REN = E1EN; - wire PORT_A2_WEN = F1EN[0]; - wire [CFG_ENABLE_F-1:0] PORT_A2_BE = {F1EN[1],F1EN[0]}; - - wire PORT_B1_REN = C1EN; - wire PORT_B1_WEN = D1EN[0]; - wire [CFG_ENABLE_D-1:0] PORT_B1_BE = {D1EN[1],D1EN[0]}; - - wire PORT_B2_REN = G1EN; - wire PORT_B2_WEN = H1EN[0]; - wire [CFG_ENABLE_H-1:0] PORT_B2_BE = {H1EN[1],H1EN[0]}; - - TDP36K bram_2x18k ( - .WDATA_A1_i(PORT_A1_WDATA), - .RDATA_A1_o(PORT_A1_RDATA), - .ADDR_A1_i(PORT_A1_ADDR), - .CLK_A1_i(PORT_A1_CLK), - .REN_A1_i(PORT_A1_REN), - .WEN_A1_i(PORT_A1_WEN), - .BE_A1_i(PORT_A1_BE), - - .WDATA_A2_i(PORT_A2_WDATA), - .RDATA_A2_o(PORT_A2_RDATA), - .ADDR_A2_i(PORT_A2_ADDR), - .CLK_A2_i(PORT_A2_CLK), - .REN_A2_i(PORT_A2_REN), - .WEN_A2_i(PORT_A2_WEN), - .BE_A2_i(PORT_A2_BE), - - .WDATA_B1_i(PORT_B1_WDATA), - .RDATA_B1_o(PORT_B1_RDATA), - .ADDR_B1_i(PORT_B1_ADDR), - .CLK_B1_i(PORT_B1_CLK), - .REN_B1_i(PORT_B1_REN), - .WEN_B1_i(PORT_B1_WEN), - .BE_B1_i(PORT_B1_BE), - - .WDATA_B2_i(PORT_B2_WDATA), - .RDATA_B2_o(PORT_B2_RDATA), - .ADDR_B2_i(PORT_B2_ADDR), - .CLK_B2_i(PORT_B2_CLK), - .REN_B2_i(PORT_B2_REN), - .WEN_B2_i(PORT_B2_WEN), - .BE_B2_i(PORT_B2_BE), - - .FLUSH1_i(FLUSH1), - .FLUSH2_i(FLUSH2) - ); -endmodule - -module BRAM2x18_SDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, D1ADDR, D1DATA, D1EN); - parameter CFG_ABITS = 11; - parameter CFG_DBITS = 18; - parameter CFG_ENABLE_B = 4; - parameter CFG_ENABLE_D = 4; - - parameter CLKPOL2 = 1; - parameter CLKPOL3 = 1; - parameter [18431:0] INIT0 = 18432'bx; - parameter [18431:0] INIT1 = 18432'bx; - - localparam MODE_36 = 3'b011; // 36- or 32-bit - localparam MODE_18 = 3'b010; // 18- or 16-bit - localparam MODE_9 = 3'b001; // 9- or 8-bit - localparam MODE_4 = 3'b100; // 4-bit - localparam MODE_2 = 3'b110; // 2-bit - localparam MODE_1 = 3'b101; // 1-bit - - input CLK1; - input CLK2; - - input [CFG_ABITS-1:0] A1ADDR; - output [CFG_DBITS-1:0] A1DATA; - input A1EN; - - input [CFG_ABITS-1:0] B1ADDR; - input [CFG_DBITS-1:0] B1DATA; - input [CFG_ENABLE_B-1:0] B1EN; - - input [CFG_ABITS-1:0] C1ADDR; - output [CFG_DBITS-1:0] C1DATA; - input C1EN; - - input [CFG_ABITS-1:0] D1ADDR; - input [CFG_DBITS-1:0] D1DATA; - input [CFG_ENABLE_D-1:0] D1EN; - - wire FLUSH1; - wire FLUSH2; - - wire [13:CFG_ABITS] A1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] B1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] C1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - wire [13:CFG_ABITS] D1ADDR_CMPL = {14-CFG_ABITS{1'b0}}; - - wire [13:0] A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR}; - wire [13:0] B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR}; - wire [13:0] C1ADDR_TOTAL = {C1ADDR_CMPL, C1ADDR}; - wire [13:0] D1ADDR_TOTAL = {D1ADDR_CMPL, D1ADDR}; - - wire [17:CFG_DBITS] A1_RDATA_CMPL; - wire [17:CFG_DBITS] C1_RDATA_CMPL; - - wire [17:CFG_DBITS] B1_WDATA_CMPL; - wire [17:CFG_DBITS] D1_WDATA_CMPL; - - wire [13:0] PORT_A1_ADDR; - wire [13:0] PORT_A2_ADDR; - wire [13:0] PORT_B1_ADDR; - wire [13:0] PORT_B2_ADDR; - - case (CFG_DBITS) - 1: begin - assign PORT_A1_ADDR = A1ADDR_TOTAL; - assign PORT_B1_ADDR = B1ADDR_TOTAL; - assign PORT_A2_ADDR = C1ADDR_TOTAL; - assign PORT_B2_ADDR = D1ADDR_TOTAL; - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0 - }; - end - - 2: begin - assign PORT_A1_ADDR = A1ADDR_TOTAL << 1; - assign PORT_B1_ADDR = B1ADDR_TOTAL << 1; - assign PORT_A2_ADDR = C1ADDR_TOTAL << 1; - assign PORT_B2_ADDR = D1ADDR_TOTAL << 1; - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0 - }; - end - - 4: begin - assign PORT_A1_ADDR = A1ADDR_TOTAL << 2; - assign PORT_B1_ADDR = B1ADDR_TOTAL << 2; - assign PORT_A2_ADDR = C1ADDR_TOTAL << 2; - assign PORT_B2_ADDR = D1ADDR_TOTAL << 2; - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0 - }; - end - - 8, 9: begin - assign PORT_A1_ADDR = A1ADDR_TOTAL << 3; - assign PORT_B1_ADDR = B1ADDR_TOTAL << 3; - assign PORT_A2_ADDR = C1ADDR_TOTAL << 3; - assign PORT_B2_ADDR = D1ADDR_TOTAL << 3; - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0 - }; - end - - 16, 18: begin - assign PORT_A1_ADDR = A1ADDR_TOTAL << 4; - assign PORT_B1_ADDR = B1ADDR_TOTAL << 4; - assign PORT_A2_ADDR = C1ADDR_TOTAL << 4; - assign PORT_B2_ADDR = D1ADDR_TOTAL << 4; - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0 - }; - end - - default: begin - assign PORT_A1_ADDR = A1ADDR_TOTAL; - assign PORT_B1_ADDR = B1ADDR_TOTAL; - assign PORT_A2_ADDR = D1ADDR_TOTAL; - assign PORT_B2_ADDR = C1ADDR_TOTAL; - defparam bram_2x18k.MODE_BITS = { 1'b1, - 11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0 - }; - end - endcase - - assign FLUSH1 = 1'b0; - assign FLUSH2 = 1'b0; - - wire [17:0] PORT_A1_RDATA; - wire [17:0] PORT_B1_RDATA; - wire [17:0] PORT_A2_RDATA; - wire [17:0] PORT_B2_RDATA; - - wire [17:0] PORT_A1_WDATA; - wire [17:0] PORT_B1_WDATA; - wire [17:0] PORT_A2_WDATA; - wire [17:0] PORT_B2_WDATA; - - // Assign read/write data - handle special case for 9bit mode - // parity bit for 9bit mode is placed in R/W port on bit #16 - case (CFG_DBITS) - 9: begin - assign A1DATA = {PORT_A1_RDATA[16], PORT_A1_RDATA[7:0]}; - assign C1DATA = {PORT_A2_RDATA[16], PORT_A2_RDATA[7:0]}; - assign PORT_A1_WDATA = {18{1'b0}}; - assign PORT_B1_WDATA = {B1_WDATA_CMPL[17], B1DATA[8], B1_WDATA_CMPL[16:9], B1DATA[7:0]}; - assign PORT_A2_WDATA = {18{1'b0}}; - assign PORT_B2_WDATA = {D1_WDATA_CMPL[17], D1DATA[8], D1_WDATA_CMPL[16:9], D1DATA[7:0]}; - end - default: begin - assign A1DATA = PORT_A1_RDATA[CFG_DBITS-1:0]; - assign C1DATA = PORT_A2_RDATA[CFG_DBITS-1:0]; - assign PORT_A1_WDATA = {18{1'b1}}; - assign PORT_B1_WDATA = {B1_WDATA_CMPL, B1DATA}; - assign PORT_A2_WDATA = {18{1'b1}}; - assign PORT_B2_WDATA = {D1_WDATA_CMPL, D1DATA}; - - end - endcase - - wire PORT_A1_CLK = CLK1; - wire PORT_A2_CLK = CLK2; - wire PORT_B1_CLK = CLK1; - wire PORT_B2_CLK = CLK2; - - wire PORT_A1_REN = A1EN; - wire PORT_A1_WEN = 1'b0; - wire [CFG_ENABLE_B-1:0] PORT_A1_BE = {PORT_A1_WEN,PORT_A1_WEN}; - - wire PORT_A2_REN = C1EN; - wire PORT_A2_WEN = 1'b0; - wire [CFG_ENABLE_D-1:0] PORT_A2_BE = {PORT_A2_WEN,PORT_A2_WEN}; - - wire PORT_B1_REN = 1'b0; - wire PORT_B1_WEN = B1EN[0]; - wire [CFG_ENABLE_B-1:0] PORT_B1_BE = {B1EN[1],B1EN[0]}; - - wire PORT_B2_REN = 1'b0; - wire PORT_B2_WEN = D1EN[0]; - wire [CFG_ENABLE_D-1:0] PORT_B2_BE = {D1EN[1],D1EN[0]}; - - TDP36K bram_2x18k ( - .WDATA_A1_i(PORT_A1_WDATA), - .RDATA_A1_o(PORT_A1_RDATA), - .ADDR_A1_i(PORT_A1_ADDR), - .CLK_A1_i(PORT_A1_CLK), - .REN_A1_i(PORT_A1_REN), - .WEN_A1_i(PORT_A1_WEN), - .BE_A1_i(PORT_A1_BE), - - .WDATA_A2_i(PORT_A2_WDATA), - .RDATA_A2_o(PORT_A2_RDATA), - .ADDR_A2_i(PORT_A2_ADDR), - .CLK_A2_i(PORT_A2_CLK), - .REN_A2_i(PORT_A2_REN), - .WEN_A2_i(PORT_A2_WEN), - .BE_A2_i(PORT_A2_BE), - - .WDATA_B1_i(PORT_B1_WDATA), - .RDATA_B1_o(PORT_B1_RDATA), - .ADDR_B1_i(PORT_B1_ADDR), - .CLK_B1_i(PORT_B1_CLK), - .REN_B1_i(PORT_B1_REN), - .WEN_B1_i(PORT_B1_WEN), - .BE_B1_i(PORT_B1_BE), - - .WDATA_B2_i(PORT_B2_WDATA), - .RDATA_B2_o(PORT_B2_RDATA), - .ADDR_B2_i(PORT_B2_ADDR), - .CLK_B2_i(PORT_B2_CLK), - .REN_B2_i(PORT_B2_REN), - .WEN_B2_i(PORT_B2_WEN), - .BE_B2_i(PORT_B2_BE), - - .FLUSH1_i(FLUSH1), - .FLUSH2_i(FLUSH2) - ); -endmodule - -module \_$_mem_v2_asymmetric (RD_ADDR, RD_ARST, RD_CLK, RD_DATA, RD_EN, RD_SRST, WR_ADDR, WR_CLK, WR_DATA, WR_EN); - localparam CFG_ABITS = 10; - localparam CFG_DBITS = 36; - localparam CFG_ENABLE_B = 4; - - localparam CLKPOL2 = 1; - localparam CLKPOL3 = 1; - - parameter READ_ADDR_WIDTH = 11; - parameter READ_DATA_WIDTH = 16; - parameter WRITE_ADDR_WIDTH = 10; - parameter WRITE_DATA_WIDTH = 32; - parameter ABITS = 0; - parameter MEMID = 0; - parameter [36863:0] INIT = 36864'bx; - parameter OFFSET = 0; - parameter RD_ARST_VALUE = 0; - parameter RD_CE_OVER_SRST = 0; - parameter RD_CLK_ENABLE = 0; - parameter RD_CLK_POLARITY = 0; - parameter RD_COLLISION_X_MASK = 0; - parameter RD_INIT_VALUE = 0; - parameter RD_PORTS = 0; - parameter RD_SRST_VALUE = 0; - parameter RD_TRANSPARENCY_MASK = 0; - parameter RD_WIDE_CONTINUATION = 0; - parameter SIZE = 0; - parameter WIDTH = 0; - parameter WR_CLK_ENABLE = 0; - parameter WR_CLK_POLARITY = 0; - parameter WR_PORTS = 0; - parameter WR_PRIORITY_MASK = 0; - parameter WR_WIDE_CONTINUATION = 0; - - localparam MODE_36 = 3'b111; // 36 or 32-bit - localparam MODE_18 = 3'b110; // 18 or 16-bit - localparam MODE_9 = 3'b101; // 9 or 8-bit - localparam MODE_4 = 3'b100; // 4-bit - localparam MODE_2 = 3'b010; // 32-bit - localparam MODE_1 = 3'b001; // 32-bit - - input RD_CLK; - input WR_CLK; - input RD_ARST; - input RD_SRST; - - input [CFG_ABITS-1:0] RD_ADDR; - output [CFG_DBITS-1:0] RD_DATA; - input RD_EN; - - input [CFG_ABITS-1:0] WR_ADDR; - input [CFG_DBITS-1:0] WR_DATA; - input [CFG_ENABLE_B-1:0] WR_EN; - - wire [14:0] RD_ADDR_15; - wire [14:0] WR_ADDR_15; - - wire [35:0] DOBDO; - - wire [14:CFG_ABITS] RD_ADDR_CMPL; - wire [14:CFG_ABITS] WR_ADDR_CMPL; - wire [35:CFG_DBITS] RD_DATA_CMPL; - wire [35:CFG_DBITS] WR_DATA_CMPL; - - wire [14:0] RD_ADDR_TOTAL; - wire [14:0] WR_ADDR_TOTAL; - wire [35:0] RD_DATA_TOTAL; - wire [35:0] WR_DATA_TOTAL; - - wire FLUSH1; - wire FLUSH2; - - assign RD_ADDR_CMPL = {15-CFG_ABITS{1'b0}}; - assign WR_ADDR_CMPL = {15-CFG_ABITS{1'b0}}; - - assign RD_ADDR_TOTAL = {RD_ADDR_CMPL, RD_ADDR}; - assign WR_ADDR_TOTAL = {WR_ADDR_CMPL, WR_ADDR}; - - assign RD_DATA_TOTAL = {RD_DATA_CMPL, RD_DATA}; - assign WR_DATA_TOTAL = {WR_DATA_CMPL, WR_DATA}; - - case (CFG_DBITS) - 1: begin - assign RD_ADDR_15 = RD_ADDR_TOTAL; - assign WR_ADDR_15 = WR_ADDR_TOTAL; - defparam bram_asymmetric.MODE_BITS = { 1'b0, - 11'd10, 11'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_1, MODE_1, MODE_1, MODE_1, 1'd0 - }; - end - - 2: begin - assign RD_ADDR_15 = RD_ADDR_TOTAL << 1; - assign WR_ADDR_15 = WR_ADDR_TOTAL << 1; - defparam bram_asymmetric.MODE_BITS = { 1'b0, - 11'd10, 11'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_2, MODE_2, MODE_2, MODE_2, 1'd0 - }; - end - - 4: begin - assign RD_ADDR_15 = RD_ADDR_TOTAL << 2; - assign WR_ADDR_15 = WR_ADDR_TOTAL << 2; - defparam bram_asymmetric.MODE_BITS = { 1'b0, - 11'd10, 11'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_4, MODE_4, MODE_4, MODE_4, 1'd0 - }; - end - 8, 9: begin - assign RD_ADDR_15 = RD_ADDR_TOTAL << 3; - assign WR_ADDR_15 = WR_ADDR_TOTAL << 3; - defparam bram_asymmetric.MODE_BITS = { 1'b0, - 11'd10, 11'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_9, MODE_9, MODE_9, MODE_9, 1'd0 - }; - end - - 16, 18: begin - assign RD_ADDR_15 = RD_ADDR_TOTAL << 4; - assign WR_ADDR_15 = WR_ADDR_TOTAL << 4; - defparam bram_asymmetric.MODE_BITS = { 1'b0, - 11'd10, 11'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_18, MODE_18, MODE_18, MODE_18, 1'd0 - }; - end - 32, 36: begin - assign RD_ADDR_15 = RD_ADDR_TOTAL << 5; - assign WR_ADDR_15 = WR_ADDR_TOTAL << 5; - defparam bram_asymmetric.MODE_BITS = { 1'b0, - 11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0 - }; - end - default: begin - assign RD_ADDR_15 = RD_ADDR_TOTAL; - assign WR_ADDR_15 = WR_ADDR_TOTAL; - defparam bram_asymmetric.MODE_BITS = { 1'b0, - 11'd10, 11'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0, - 12'd10, 12'd10, 4'd0, MODE_36, MODE_36, MODE_36, MODE_36, 1'd0 - }; - end - endcase - - assign FLUSH1 = 1'b0; - assign FLUSH2 = 1'b0; - - TDP36K bram_asymmetric ( - .RESET_ni(1'b1), - .WDATA_A1_i(18'h3FFFF), - .WDATA_A2_i(18'h3FFFF), - .RDATA_A1_o(RD_DATA_TOTAL[17:0]), - .RDATA_A2_o(RD_DATA_TOTAL[35:18]), - .ADDR_A1_i(RD_ADDR_15), - .ADDR_A2_i(RD_ADDR_15), - .CLK_A1_i(RD_CLK), - .CLK_A2_i(RD_CLK), - .REN_A1_i(RD_EN), - .REN_A2_i(RD_EN), - .WEN_A1_i(1'b0), - .WEN_A2_i(1'b0), - .BE_A1_i({RD_EN, RD_EN}), - .BE_A2_i({RD_EN, RD_EN}), - - .WDATA_B1_i(WR_DATA[17:0]), - .WDATA_B2_i(WR_DATA[35:18]), - .RDATA_B1_o(DOBDO[17:0]), - .RDATA_B2_o(DOBDO[35:18]), - .ADDR_B1_i(WR_ADDR_15), - .ADDR_B2_i(WR_ADDR_15), - .CLK_B1_i(WR_CLK), - .CLK_B2_i(WR_CLK), - .REN_B1_i(1'b0), - .REN_B2_i(1'b0), - .WEN_B1_i(WR_EN[0]), - .WEN_B2_i(WR_EN[0]), - .BE_B1_i(WR_EN[1:0]), - .BE_B2_i(WR_EN[3:2]), - - .FLUSH1_i(FLUSH1), - .FLUSH2_i(FLUSH2) - ); -endmodule diff --git a/ql-qlf-plugin/qlf_k6n10f/dsp_sim.v b/ql-qlf-plugin/qlf_k6n10f/dsp_sim.v index 14ec751..cdaa81b 100644 --- a/ql-qlf-plugin/qlf_k6n10f/dsp_sim.v +++ b/ql-qlf-plugin/qlf_k6n10f/dsp_sim.v @@ -14,6 +14,8 @@ // // SPDX-License-Identifier: Apache-2.0 +`timescale 1ps/1ps + `default_nettype none (* blackbox *) @@ -221,20 +223,1478 @@ module QL_DSP2_MULT ( // TODO: Name subject to change ) dsp ( .a(a), .b(b), + .acc_fir(6'b0), .z(z), + .dly_b(), + .clk(1'b0), .reset(reset), .f_mode(f_mode), .feedback(feedback), + .load_acc(1'b0), .unsigned_a(unsigned_a), .unsigned_b(unsigned_b), .output_select(output_select), // unregistered output: a * b (0) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), .register_inputs(register_inputs) // unregistered inputs ); + +`ifdef SDF_SIM + specify + (a[0] => z[0]) = 0; + (a[1] => z[0]) = 0; + (a[2] => z[0]) = 0; + (a[3] => z[0]) = 0; + (a[4] => z[0]) = 0; + (a[5] => z[0]) = 0; + (a[6] => z[0]) = 0; + (a[7] => z[0]) = 0; + (a[8] => z[0]) = 0; + (a[9] => z[0]) = 0; + (a[10] => z[0]) = 0; + (a[11] => z[0]) = 0; + (a[12] => z[0]) = 0; + (a[13] => z[0]) = 0; + (a[14] => z[0]) = 0; + (a[15] => z[0]) = 0; + (a[16] => z[0]) = 0; + (a[17] => z[0]) = 0; + (a[18] => z[0]) = 0; + (a[19] => z[0]) = 0; + (b[0] => z[0]) = 0; + (b[1] => z[0]) = 0; + (b[2] => z[0]) = 0; + (b[3] => z[0]) = 0; + (b[4] => z[0]) = 0; + (b[5] => z[0]) = 0; + (b[6] => z[0]) = 0; + (b[7] => z[0]) = 0; + (b[8] => z[0]) = 0; + (b[9] => z[0]) = 0; + (b[10] => z[0]) = 0; + (b[11] => z[0]) = 0; + (b[12] => z[0]) = 0; + (b[13] => z[0]) = 0; + (b[14] => z[0]) = 0; + (b[15] => z[0]) = 0; + (b[16] => z[0]) = 0; + (b[17] => z[0]) = 0; + (a[0] => z[1]) = 0; + (a[1] => z[1]) = 0; + (a[2] => z[1]) = 0; + (a[3] => z[1]) = 0; + (a[4] => z[1]) = 0; + (a[5] => z[1]) = 0; + (a[6] => z[1]) = 0; + (a[7] => z[1]) = 0; + (a[8] => z[1]) = 0; + (a[9] => z[1]) = 0; + (a[10] => z[1]) = 0; + (a[11] => z[1]) = 0; + (a[12] => z[1]) = 0; + (a[13] => z[1]) = 0; + (a[14] => z[1]) = 0; + (a[15] => z[1]) = 0; + (a[16] => z[1]) = 0; + (a[17] => z[1]) = 0; + (a[18] => z[1]) = 0; + (a[19] => z[1]) = 0; + (b[0] => z[1]) = 0; + (b[1] => z[1]) = 0; + (b[2] => z[1]) = 0; + (b[3] => z[1]) = 0; + (b[4] => z[1]) = 0; + (b[5] => z[1]) = 0; + (b[6] => z[1]) = 0; + (b[7] => z[1]) = 0; + (b[8] => z[1]) = 0; + (b[9] => z[1]) = 0; + (b[10] => z[1]) = 0; + (b[11] => z[1]) = 0; + (b[12] => z[1]) = 0; + (b[13] => z[1]) = 0; + (b[14] => z[1]) = 0; + (b[15] => z[1]) = 0; + (b[16] => z[1]) = 0; + (b[17] => z[1]) = 0; + (a[0] => z[2]) = 0; + (a[1] => z[2]) = 0; + (a[2] => z[2]) = 0; + (a[3] => z[2]) = 0; + (a[4] => z[2]) = 0; + (a[5] => z[2]) = 0; + (a[6] => z[2]) = 0; + (a[7] => z[2]) = 0; + (a[8] => z[2]) = 0; + (a[9] => z[2]) = 0; + (a[10] => z[2]) = 0; + (a[11] => z[2]) = 0; + (a[12] => z[2]) = 0; + (a[13] => z[2]) = 0; + (a[14] => z[2]) = 0; + (a[15] => z[2]) = 0; + (a[16] => z[2]) = 0; + (a[17] => z[2]) = 0; + (a[18] => z[2]) = 0; + (a[19] => z[2]) = 0; + (b[0] => z[2]) = 0; + (b[1] => z[2]) = 0; + (b[2] => z[2]) = 0; + (b[3] => z[2]) = 0; + (b[4] => z[2]) = 0; + (b[5] => z[2]) = 0; + (b[6] => z[2]) = 0; + (b[7] => z[2]) = 0; + (b[8] => z[2]) = 0; + (b[9] => z[2]) = 0; + (b[10] => z[2]) = 0; + (b[11] => z[2]) = 0; + (b[12] => z[2]) = 0; + (b[13] => z[2]) = 0; + (b[14] => z[2]) = 0; + (b[15] => z[2]) = 0; + (b[16] => z[2]) = 0; + (b[17] => z[2]) = 0; + (a[0] => z[3]) = 0; + (a[1] => z[3]) = 0; + (a[2] => z[3]) = 0; + (a[3] => z[3]) = 0; + (a[4] => z[3]) = 0; + (a[5] => z[3]) = 0; + (a[6] => z[3]) = 0; + (a[7] => z[3]) = 0; + (a[8] => z[3]) = 0; + (a[9] => z[3]) = 0; + (a[10] => z[3]) = 0; + (a[11] => z[3]) = 0; + (a[12] => z[3]) = 0; + (a[13] => z[3]) = 0; + (a[14] => z[3]) = 0; + (a[15] => z[3]) = 0; + (a[16] => z[3]) = 0; + (a[17] => z[3]) = 0; + (a[18] => z[3]) = 0; + (a[19] => z[3]) = 0; + (b[0] => z[3]) = 0; + (b[1] => z[3]) = 0; + (b[2] => z[3]) = 0; + (b[3] => z[3]) = 0; + (b[4] => z[3]) = 0; + (b[5] => z[3]) = 0; + (b[6] => z[3]) = 0; + (b[7] => z[3]) = 0; + (b[8] => z[3]) = 0; + (b[9] => z[3]) = 0; + (b[10] => z[3]) = 0; + (b[11] => z[3]) = 0; + (b[12] => z[3]) = 0; + (b[13] => z[3]) = 0; + (b[14] => z[3]) = 0; + (b[15] => z[3]) = 0; + (b[16] => z[3]) = 0; + (b[17] => z[3]) = 0; + (a[0] => z[4]) = 0; + (a[1] => z[4]) = 0; + (a[2] => z[4]) = 0; + (a[3] => z[4]) = 0; + (a[4] => z[4]) = 0; + (a[5] => z[4]) = 0; + (a[6] => z[4]) = 0; + (a[7] => z[4]) = 0; + (a[8] => z[4]) = 0; + (a[9] => z[4]) = 0; + (a[10] => z[4]) = 0; + (a[11] => z[4]) = 0; + (a[12] => z[4]) = 0; + (a[13] => z[4]) = 0; + (a[14] => z[4]) = 0; + (a[15] => z[4]) = 0; + (a[16] => z[4]) = 0; + (a[17] => z[4]) = 0; + (a[18] => z[4]) = 0; + (a[19] => z[4]) = 0; + (b[0] => z[4]) = 0; + (b[1] => z[4]) = 0; + (b[2] => z[4]) = 0; + (b[3] => z[4]) = 0; + (b[4] => z[4]) = 0; + (b[5] => z[4]) = 0; + (b[6] => z[4]) = 0; + (b[7] => z[4]) = 0; + (b[8] => z[4]) = 0; + (b[9] => z[4]) = 0; + (b[10] => z[4]) = 0; + (b[11] => z[4]) = 0; + (b[12] => z[4]) = 0; + (b[13] => z[4]) = 0; + (b[14] => z[4]) = 0; + (b[15] => z[4]) = 0; + (b[16] => z[4]) = 0; + (b[17] => z[4]) = 0; + (a[0] => z[5]) = 0; + (a[1] => z[5]) = 0; + (a[2] => z[5]) = 0; + (a[3] => z[5]) = 0; + (a[4] => z[5]) = 0; + (a[5] => z[5]) = 0; + (a[6] => z[5]) = 0; + (a[7] => z[5]) = 0; + (a[8] => z[5]) = 0; + (a[9] => z[5]) = 0; + (a[10] => z[5]) = 0; + (a[11] => z[5]) = 0; + (a[12] => z[5]) = 0; + (a[13] => z[5]) = 0; + (a[14] => z[5]) = 0; + (a[15] => z[5]) = 0; + (a[16] => z[5]) = 0; + (a[17] => z[5]) = 0; + (a[18] => z[5]) = 0; + (a[19] => z[5]) = 0; + (b[0] => z[5]) = 0; + (b[1] => z[5]) = 0; + (b[2] => z[5]) = 0; + (b[3] => z[5]) = 0; + (b[4] => z[5]) = 0; + (b[5] => z[5]) = 0; + (b[6] => z[5]) = 0; + (b[7] => z[5]) = 0; + (b[8] => z[5]) = 0; + (b[9] => z[5]) = 0; + (b[10] => z[5]) = 0; + (b[11] => z[5]) = 0; + (b[12] => z[5]) = 0; + (b[13] => z[5]) = 0; + (b[14] => z[5]) = 0; + (b[15] => z[5]) = 0; + (b[16] => z[5]) = 0; + (b[17] => z[5]) = 0; + (a[0] => z[6]) = 0; + (a[1] => z[6]) = 0; + (a[2] => z[6]) = 0; + (a[3] => z[6]) = 0; + (a[4] => z[6]) = 0; + (a[5] => z[6]) = 0; + (a[6] => z[6]) = 0; + (a[7] => z[6]) = 0; + (a[8] => z[6]) = 0; + (a[9] => z[6]) = 0; + (a[10] => z[6]) = 0; + (a[11] => z[6]) = 0; + (a[12] => z[6]) = 0; + (a[13] => z[6]) = 0; + (a[14] => z[6]) = 0; + (a[15] => z[6]) = 0; + (a[16] => z[6]) = 0; + (a[17] => z[6]) = 0; + (a[18] => z[6]) = 0; + (a[19] => z[6]) = 0; + (b[0] => z[6]) = 0; + (b[1] => z[6]) = 0; + (b[2] => z[6]) = 0; + (b[3] => z[6]) = 0; + (b[4] => z[6]) = 0; + (b[5] => z[6]) = 0; + (b[6] => z[6]) = 0; + (b[7] => z[6]) = 0; + (b[8] => z[6]) = 0; + (b[9] => z[6]) = 0; + (b[10] => z[6]) = 0; + (b[11] => z[6]) = 0; + (b[12] => z[6]) = 0; + (b[13] => z[6]) = 0; + (b[14] => z[6]) = 0; + (b[15] => z[6]) = 0; + (b[16] => z[6]) = 0; + (b[17] => z[6]) = 0; + (a[0] => z[7]) = 0; + (a[1] => z[7]) = 0; + (a[2] => z[7]) = 0; + (a[3] => z[7]) = 0; + (a[4] => z[7]) = 0; + (a[5] => z[7]) = 0; + (a[6] => z[7]) = 0; + (a[7] => z[7]) = 0; + (a[8] => z[7]) = 0; + (a[9] => z[7]) = 0; + (a[10] => z[7]) = 0; + (a[11] => z[7]) = 0; + (a[12] => z[7]) = 0; + (a[13] => z[7]) = 0; + (a[14] => z[7]) = 0; + (a[15] => z[7]) = 0; + (a[16] => z[7]) = 0; + (a[17] => z[7]) = 0; + (a[18] => z[7]) = 0; + (a[19] => z[7]) = 0; + (b[0] => z[7]) = 0; + (b[1] => z[7]) = 0; + (b[2] => z[7]) = 0; + (b[3] => z[7]) = 0; + (b[4] => z[7]) = 0; + (b[5] => z[7]) = 0; + (b[6] => z[7]) = 0; + (b[7] => z[7]) = 0; + (b[8] => z[7]) = 0; + (b[9] => z[7]) = 0; + (b[10] => z[7]) = 0; + (b[11] => z[7]) = 0; + (b[12] => z[7]) = 0; + (b[13] => z[7]) = 0; + (b[14] => z[7]) = 0; + (b[15] => z[7]) = 0; + (b[16] => z[7]) = 0; + (b[17] => z[7]) = 0; + (a[0] => z[8]) = 0; + (a[1] => z[8]) = 0; + (a[2] => z[8]) = 0; + (a[3] => z[8]) = 0; + (a[4] => z[8]) = 0; + (a[5] => z[8]) = 0; + (a[6] => z[8]) = 0; + (a[7] => z[8]) = 0; + (a[8] => z[8]) = 0; + (a[9] => z[8]) = 0; + (a[10] => z[8]) = 0; + (a[11] => z[8]) = 0; + (a[12] => z[8]) = 0; + (a[13] => z[8]) = 0; + (a[14] => z[8]) = 0; + (a[15] => z[8]) = 0; + (a[16] => z[8]) = 0; + (a[17] => z[8]) = 0; + (a[18] => z[8]) = 0; + (a[19] => z[8]) = 0; + (b[0] => z[8]) = 0; + (b[1] => z[8]) = 0; + (b[2] => z[8]) = 0; + (b[3] => z[8]) = 0; + (b[4] => z[8]) = 0; + (b[5] => z[8]) = 0; + (b[6] => z[8]) = 0; + (b[7] => z[8]) = 0; + (b[8] => z[8]) = 0; + (b[9] => z[8]) = 0; + (b[10] => z[8]) = 0; + (b[11] => z[8]) = 0; + (b[12] => z[8]) = 0; + (b[13] => z[8]) = 0; + (b[14] => z[8]) = 0; + (b[15] => z[8]) = 0; + (b[16] => z[8]) = 0; + (b[17] => z[8]) = 0; + (a[0] => z[9]) = 0; + (a[1] => z[9]) = 0; + (a[2] => z[9]) = 0; + (a[3] => z[9]) = 0; + (a[4] => z[9]) = 0; + (a[5] => z[9]) = 0; + (a[6] => z[9]) = 0; + (a[7] => z[9]) = 0; + (a[8] => z[9]) = 0; + (a[9] => z[9]) = 0; + (a[10] => z[9]) = 0; + (a[11] => z[9]) = 0; + (a[12] => z[9]) = 0; + (a[13] => z[9]) = 0; + (a[14] => z[9]) = 0; + (a[15] => z[9]) = 0; + (a[16] => z[9]) = 0; + (a[17] => z[9]) = 0; + (a[18] => z[9]) = 0; + (a[19] => z[9]) = 0; + (b[0] => z[9]) = 0; + (b[1] => z[9]) = 0; + (b[2] => z[9]) = 0; + (b[3] => z[9]) = 0; + (b[4] => z[9]) = 0; + (b[5] => z[9]) = 0; + (b[6] => z[9]) = 0; + (b[7] => z[9]) = 0; + (b[8] => z[9]) = 0; + (b[9] => z[9]) = 0; + (b[10] => z[9]) = 0; + (b[11] => z[9]) = 0; + (b[12] => z[9]) = 0; + (b[13] => z[9]) = 0; + (b[14] => z[9]) = 0; + (b[15] => z[9]) = 0; + (b[16] => z[9]) = 0; + (b[17] => z[9]) = 0; + (a[0] => z[10]) = 0; + (a[1] => z[10]) = 0; + (a[2] => z[10]) = 0; + (a[3] => z[10]) = 0; + (a[4] => z[10]) = 0; + (a[5] => z[10]) = 0; + (a[6] => z[10]) = 0; + (a[7] => z[10]) = 0; + (a[8] => z[10]) = 0; + (a[9] => z[10]) = 0; + (a[10] => z[10]) = 0; + (a[11] => z[10]) = 0; + (a[12] => z[10]) = 0; + (a[13] => z[10]) = 0; + (a[14] => z[10]) = 0; + (a[15] => z[10]) = 0; + (a[16] => z[10]) = 0; + (a[17] => z[10]) = 0; + (a[18] => z[10]) = 0; + (a[19] => z[10]) = 0; + (b[0] => z[10]) = 0; + (b[1] => z[10]) = 0; + (b[2] => z[10]) = 0; + (b[3] => z[10]) = 0; + (b[4] => z[10]) = 0; + (b[5] => z[10]) = 0; + (b[6] => z[10]) = 0; + (b[7] => z[10]) = 0; + (b[8] => z[10]) = 0; + (b[9] => z[10]) = 0; + (b[10] => z[10]) = 0; + (b[11] => z[10]) = 0; + (b[12] => z[10]) = 0; + (b[13] => z[10]) = 0; + (b[14] => z[10]) = 0; + (b[15] => z[10]) = 0; + (b[16] => z[10]) = 0; + (b[17] => z[10]) = 0; + (a[0] => z[11]) = 0; + (a[1] => z[11]) = 0; + (a[2] => z[11]) = 0; + (a[3] => z[11]) = 0; + (a[4] => z[11]) = 0; + (a[5] => z[11]) = 0; + (a[6] => z[11]) = 0; + (a[7] => z[11]) = 0; + (a[8] => z[11]) = 0; + (a[9] => z[11]) = 0; + (a[10] => z[11]) = 0; + (a[11] => z[11]) = 0; + (a[12] => z[11]) = 0; + (a[13] => z[11]) = 0; + (a[14] => z[11]) = 0; + (a[15] => z[11]) = 0; + (a[16] => z[11]) = 0; + (a[17] => z[11]) = 0; + (a[18] => z[11]) = 0; + (a[19] => z[11]) = 0; + (b[0] => z[11]) = 0; + (b[1] => z[11]) = 0; + (b[2] => z[11]) = 0; + (b[3] => z[11]) = 0; + (b[4] => z[11]) = 0; + (b[5] => z[11]) = 0; + (b[6] => z[11]) = 0; + (b[7] => z[11]) = 0; + (b[8] => z[11]) = 0; + (b[9] => z[11]) = 0; + (b[10] => z[11]) = 0; + (b[11] => z[11]) = 0; + (b[12] => z[11]) = 0; + (b[13] => z[11]) = 0; + (b[14] => z[11]) = 0; + (b[15] => z[11]) = 0; + (b[16] => z[11]) = 0; + (b[17] => z[11]) = 0; + (a[0] => z[12]) = 0; + (a[1] => z[12]) = 0; + (a[2] => z[12]) = 0; + (a[3] => z[12]) = 0; + (a[4] => z[12]) = 0; + (a[5] => z[12]) = 0; + (a[6] => z[12]) = 0; + (a[7] => z[12]) = 0; + (a[8] => z[12]) = 0; + (a[9] => z[12]) = 0; + (a[10] => z[12]) = 0; + (a[11] => z[12]) = 0; + (a[12] => z[12]) = 0; + (a[13] => z[12]) = 0; + (a[14] => z[12]) = 0; + (a[15] => z[12]) = 0; + (a[16] => z[12]) = 0; + (a[17] => z[12]) = 0; + (a[18] => z[12]) = 0; + (a[19] => z[12]) = 0; + (b[0] => z[12]) = 0; + (b[1] => z[12]) = 0; + (b[2] => z[12]) = 0; + (b[3] => z[12]) = 0; + (b[4] => z[12]) = 0; + (b[5] => z[12]) = 0; + (b[6] => z[12]) = 0; + (b[7] => z[12]) = 0; + (b[8] => z[12]) = 0; + (b[9] => z[12]) = 0; + (b[10] => z[12]) = 0; + (b[11] => z[12]) = 0; + (b[12] => z[12]) = 0; + (b[13] => z[12]) = 0; + (b[14] => z[12]) = 0; + (b[15] => z[12]) = 0; + (b[16] => z[12]) = 0; + (b[17] => z[12]) = 0; + (a[0] => z[13]) = 0; + (a[1] => z[13]) = 0; + (a[2] => z[13]) = 0; + (a[3] => z[13]) = 0; + (a[4] => z[13]) = 0; + (a[5] => z[13]) = 0; + (a[6] => z[13]) = 0; + (a[7] => z[13]) = 0; + (a[8] => z[13]) = 0; + (a[9] => z[13]) = 0; + (a[10] => z[13]) = 0; + (a[11] => z[13]) = 0; + (a[12] => z[13]) = 0; + (a[13] => z[13]) = 0; + (a[14] => z[13]) = 0; + (a[15] => z[13]) = 0; + (a[16] => z[13]) = 0; + (a[17] => z[13]) = 0; + (a[18] => z[13]) = 0; + (a[19] => z[13]) = 0; + (b[0] => z[13]) = 0; + (b[1] => z[13]) = 0; + (b[2] => z[13]) = 0; + (b[3] => z[13]) = 0; + (b[4] => z[13]) = 0; + (b[5] => z[13]) = 0; + (b[6] => z[13]) = 0; + (b[7] => z[13]) = 0; + (b[8] => z[13]) = 0; + (b[9] => z[13]) = 0; + (b[10] => z[13]) = 0; + (b[11] => z[13]) = 0; + (b[12] => z[13]) = 0; + (b[13] => z[13]) = 0; + (b[14] => z[13]) = 0; + (b[15] => z[13]) = 0; + (b[16] => z[13]) = 0; + (b[17] => z[13]) = 0; + (a[0] => z[14]) = 0; + (a[1] => z[14]) = 0; + (a[2] => z[14]) = 0; + (a[3] => z[14]) = 0; + (a[4] => z[14]) = 0; + (a[5] => z[14]) = 0; + (a[6] => z[14]) = 0; + (a[7] => z[14]) = 0; + (a[8] => z[14]) = 0; + (a[9] => z[14]) = 0; + (a[10] => z[14]) = 0; + (a[11] => z[14]) = 0; + (a[12] => z[14]) = 0; + (a[13] => z[14]) = 0; + (a[14] => z[14]) = 0; + (a[15] => z[14]) = 0; + (a[16] => z[14]) = 0; + (a[17] => z[14]) = 0; + (a[18] => z[14]) = 0; + (a[19] => z[14]) = 0; + (b[0] => z[14]) = 0; + (b[1] => z[14]) = 0; + (b[2] => z[14]) = 0; + (b[3] => z[14]) = 0; + (b[4] => z[14]) = 0; + (b[5] => z[14]) = 0; + (b[6] => z[14]) = 0; + (b[7] => z[14]) = 0; + (b[8] => z[14]) = 0; + (b[9] => z[14]) = 0; + (b[10] => z[14]) = 0; + (b[11] => z[14]) = 0; + (b[12] => z[14]) = 0; + (b[13] => z[14]) = 0; + (b[14] => z[14]) = 0; + (b[15] => z[14]) = 0; + (b[16] => z[14]) = 0; + (b[17] => z[14]) = 0; + (a[0] => z[15]) = 0; + (a[1] => z[15]) = 0; + (a[2] => z[15]) = 0; + (a[3] => z[15]) = 0; + (a[4] => z[15]) = 0; + (a[5] => z[15]) = 0; + (a[6] => z[15]) = 0; + (a[7] => z[15]) = 0; + (a[8] => z[15]) = 0; + (a[9] => z[15]) = 0; + (a[10] => z[15]) = 0; + (a[11] => z[15]) = 0; + (a[12] => z[15]) = 0; + (a[13] => z[15]) = 0; + (a[14] => z[15]) = 0; + (a[15] => z[15]) = 0; + (a[16] => z[15]) = 0; + (a[17] => z[15]) = 0; + (a[18] => z[15]) = 0; + (a[19] => z[15]) = 0; + (b[0] => z[15]) = 0; + (b[1] => z[15]) = 0; + (b[2] => z[15]) = 0; + (b[3] => z[15]) = 0; + (b[4] => z[15]) = 0; + (b[5] => z[15]) = 0; + (b[6] => z[15]) = 0; + (b[7] => z[15]) = 0; + (b[8] => z[15]) = 0; + (b[9] => z[15]) = 0; + (b[10] => z[15]) = 0; + (b[11] => z[15]) = 0; + (b[12] => z[15]) = 0; + (b[13] => z[15]) = 0; + (b[14] => z[15]) = 0; + (b[15] => z[15]) = 0; + (b[16] => z[15]) = 0; + (b[17] => z[15]) = 0; + (a[0] => z[16]) = 0; + (a[1] => z[16]) = 0; + (a[2] => z[16]) = 0; + (a[3] => z[16]) = 0; + (a[4] => z[16]) = 0; + (a[5] => z[16]) = 0; + (a[6] => z[16]) = 0; + (a[7] => z[16]) = 0; + (a[8] => z[16]) = 0; + (a[9] => z[16]) = 0; + (a[10] => z[16]) = 0; + (a[11] => z[16]) = 0; + (a[12] => z[16]) = 0; + (a[13] => z[16]) = 0; + (a[14] => z[16]) = 0; + (a[15] => z[16]) = 0; + (a[16] => z[16]) = 0; + (a[17] => z[16]) = 0; + (a[18] => z[16]) = 0; + (a[19] => z[16]) = 0; + (b[0] => z[16]) = 0; + (b[1] => z[16]) = 0; + (b[2] => z[16]) = 0; + (b[3] => z[16]) = 0; + (b[4] => z[16]) = 0; + (b[5] => z[16]) = 0; + (b[6] => z[16]) = 0; + (b[7] => z[16]) = 0; + (b[8] => z[16]) = 0; + (b[9] => z[16]) = 0; + (b[10] => z[16]) = 0; + (b[11] => z[16]) = 0; + (b[12] => z[16]) = 0; + (b[13] => z[16]) = 0; + (b[14] => z[16]) = 0; + (b[15] => z[16]) = 0; + (b[16] => z[16]) = 0; + (b[17] => z[16]) = 0; + (a[0] => z[17]) = 0; + (a[1] => z[17]) = 0; + (a[2] => z[17]) = 0; + (a[3] => z[17]) = 0; + (a[4] => z[17]) = 0; + (a[5] => z[17]) = 0; + (a[6] => z[17]) = 0; + (a[7] => z[17]) = 0; + (a[8] => z[17]) = 0; + (a[9] => z[17]) = 0; + (a[10] => z[17]) = 0; + (a[11] => z[17]) = 0; + (a[12] => z[17]) = 0; + (a[13] => z[17]) = 0; + (a[14] => z[17]) = 0; + (a[15] => z[17]) = 0; + (a[16] => z[17]) = 0; + (a[17] => z[17]) = 0; + (a[18] => z[17]) = 0; + (a[19] => z[17]) = 0; + (b[0] => z[17]) = 0; + (b[1] => z[17]) = 0; + (b[2] => z[17]) = 0; + (b[3] => z[17]) = 0; + (b[4] => z[17]) = 0; + (b[5] => z[17]) = 0; + (b[6] => z[17]) = 0; + (b[7] => z[17]) = 0; + (b[8] => z[17]) = 0; + (b[9] => z[17]) = 0; + (b[10] => z[17]) = 0; + (b[11] => z[17]) = 0; + (b[12] => z[17]) = 0; + (b[13] => z[17]) = 0; + (b[14] => z[17]) = 0; + (b[15] => z[17]) = 0; + (b[16] => z[17]) = 0; + (b[17] => z[17]) = 0; + (a[0] => z[18]) = 0; + (a[1] => z[18]) = 0; + (a[2] => z[18]) = 0; + (a[3] => z[18]) = 0; + (a[4] => z[18]) = 0; + (a[5] => z[18]) = 0; + (a[6] => z[18]) = 0; + (a[7] => z[18]) = 0; + (a[8] => z[18]) = 0; + (a[9] => z[18]) = 0; + (a[10] => z[18]) = 0; + (a[11] => z[18]) = 0; + (a[12] => z[18]) = 0; + (a[13] => z[18]) = 0; + (a[14] => z[18]) = 0; + (a[15] => z[18]) = 0; + (a[16] => z[18]) = 0; + (a[17] => z[18]) = 0; + (a[18] => z[18]) = 0; + (a[19] => z[18]) = 0; + (b[0] => z[18]) = 0; + (b[1] => z[18]) = 0; + (b[2] => z[18]) = 0; + (b[3] => z[18]) = 0; + (b[4] => z[18]) = 0; + (b[5] => z[18]) = 0; + (b[6] => z[18]) = 0; + (b[7] => z[18]) = 0; + (b[8] => z[18]) = 0; + (b[9] => z[18]) = 0; + (b[10] => z[18]) = 0; + (b[11] => z[18]) = 0; + (b[12] => z[18]) = 0; + (b[13] => z[18]) = 0; + (b[14] => z[18]) = 0; + (b[15] => z[18]) = 0; + (b[16] => z[18]) = 0; + (b[17] => z[18]) = 0; + (a[0] => z[19]) = 0; + (a[1] => z[19]) = 0; + (a[2] => z[19]) = 0; + (a[3] => z[19]) = 0; + (a[4] => z[19]) = 0; + (a[5] => z[19]) = 0; + (a[6] => z[19]) = 0; + (a[7] => z[19]) = 0; + (a[8] => z[19]) = 0; + (a[9] => z[19]) = 0; + (a[10] => z[19]) = 0; + (a[11] => z[19]) = 0; + (a[12] => z[19]) = 0; + (a[13] => z[19]) = 0; + (a[14] => z[19]) = 0; + (a[15] => z[19]) = 0; + (a[16] => z[19]) = 0; + (a[17] => z[19]) = 0; + (a[18] => z[19]) = 0; + (a[19] => z[19]) = 0; + (b[0] => z[19]) = 0; + (b[1] => z[19]) = 0; + (b[2] => z[19]) = 0; + (b[3] => z[19]) = 0; + (b[4] => z[19]) = 0; + (b[5] => z[19]) = 0; + (b[6] => z[19]) = 0; + (b[7] => z[19]) = 0; + (b[8] => z[19]) = 0; + (b[9] => z[19]) = 0; + (b[10] => z[19]) = 0; + (b[11] => z[19]) = 0; + (b[12] => z[19]) = 0; + (b[13] => z[19]) = 0; + (b[14] => z[19]) = 0; + (b[15] => z[19]) = 0; + (b[16] => z[19]) = 0; + (b[17] => z[19]) = 0; + (a[0] => z[20]) = 0; + (a[1] => z[20]) = 0; + (a[2] => z[20]) = 0; + (a[3] => z[20]) = 0; + (a[4] => z[20]) = 0; + (a[5] => z[20]) = 0; + (a[6] => z[20]) = 0; + (a[7] => z[20]) = 0; + (a[8] => z[20]) = 0; + (a[9] => z[20]) = 0; + (a[10] => z[20]) = 0; + (a[11] => z[20]) = 0; + (a[12] => z[20]) = 0; + (a[13] => z[20]) = 0; + (a[14] => z[20]) = 0; + (a[15] => z[20]) = 0; + (a[16] => z[20]) = 0; + (a[17] => z[20]) = 0; + (a[18] => z[20]) = 0; + (a[19] => z[20]) = 0; + (b[0] => z[20]) = 0; + (b[1] => z[20]) = 0; + (b[2] => z[20]) = 0; + (b[3] => z[20]) = 0; + (b[4] => z[20]) = 0; + (b[5] => z[20]) = 0; + (b[6] => z[20]) = 0; + (b[7] => z[20]) = 0; + (b[8] => z[20]) = 0; + (b[9] => z[20]) = 0; + (b[10] => z[20]) = 0; + (b[11] => z[20]) = 0; + (b[12] => z[20]) = 0; + (b[13] => z[20]) = 0; + (b[14] => z[20]) = 0; + (b[15] => z[20]) = 0; + (b[16] => z[20]) = 0; + (b[17] => z[20]) = 0; + (a[0] => z[21]) = 0; + (a[1] => z[21]) = 0; + (a[2] => z[21]) = 0; + (a[3] => z[21]) = 0; + (a[4] => z[21]) = 0; + (a[5] => z[21]) = 0; + (a[6] => z[21]) = 0; + (a[7] => z[21]) = 0; + (a[8] => z[21]) = 0; + (a[9] => z[21]) = 0; + (a[10] => z[21]) = 0; + (a[11] => z[21]) = 0; + (a[12] => z[21]) = 0; + (a[13] => z[21]) = 0; + (a[14] => z[21]) = 0; + (a[15] => z[21]) = 0; + (a[16] => z[21]) = 0; + (a[17] => z[21]) = 0; + (a[18] => z[21]) = 0; + (a[19] => z[21]) = 0; + (b[0] => z[21]) = 0; + (b[1] => z[21]) = 0; + (b[2] => z[21]) = 0; + (b[3] => z[21]) = 0; + (b[4] => z[21]) = 0; + (b[5] => z[21]) = 0; + (b[6] => z[21]) = 0; + (b[7] => z[21]) = 0; + (b[8] => z[21]) = 0; + (b[9] => z[21]) = 0; + (b[10] => z[21]) = 0; + (b[11] => z[21]) = 0; + (b[12] => z[21]) = 0; + (b[13] => z[21]) = 0; + (b[14] => z[21]) = 0; + (b[15] => z[21]) = 0; + (b[16] => z[21]) = 0; + (b[17] => z[21]) = 0; + (a[0] => z[22]) = 0; + (a[1] => z[22]) = 0; + (a[2] => z[22]) = 0; + (a[3] => z[22]) = 0; + (a[4] => z[22]) = 0; + (a[5] => z[22]) = 0; + (a[6] => z[22]) = 0; + (a[7] => z[22]) = 0; + (a[8] => z[22]) = 0; + (a[9] => z[22]) = 0; + (a[10] => z[22]) = 0; + (a[11] => z[22]) = 0; + (a[12] => z[22]) = 0; + (a[13] => z[22]) = 0; + (a[14] => z[22]) = 0; + (a[15] => z[22]) = 0; + (a[16] => z[22]) = 0; + (a[17] => z[22]) = 0; + (a[18] => z[22]) = 0; + (a[19] => z[22]) = 0; + (b[0] => z[22]) = 0; + (b[1] => z[22]) = 0; + (b[2] => z[22]) = 0; + (b[3] => z[22]) = 0; + (b[4] => z[22]) = 0; + (b[5] => z[22]) = 0; + (b[6] => z[22]) = 0; + (b[7] => z[22]) = 0; + (b[8] => z[22]) = 0; + (b[9] => z[22]) = 0; + (b[10] => z[22]) = 0; + (b[11] => z[22]) = 0; + (b[12] => z[22]) = 0; + (b[13] => z[22]) = 0; + (b[14] => z[22]) = 0; + (b[15] => z[22]) = 0; + (b[16] => z[22]) = 0; + (b[17] => z[22]) = 0; + (a[0] => z[23]) = 0; + (a[1] => z[23]) = 0; + (a[2] => z[23]) = 0; + (a[3] => z[23]) = 0; + (a[4] => z[23]) = 0; + (a[5] => z[23]) = 0; + (a[6] => z[23]) = 0; + (a[7] => z[23]) = 0; + (a[8] => z[23]) = 0; + (a[9] => z[23]) = 0; + (a[10] => z[23]) = 0; + (a[11] => z[23]) = 0; + (a[12] => z[23]) = 0; + (a[13] => z[23]) = 0; + (a[14] => z[23]) = 0; + (a[15] => z[23]) = 0; + (a[16] => z[23]) = 0; + (a[17] => z[23]) = 0; + (a[18] => z[23]) = 0; + (a[19] => z[23]) = 0; + (b[0] => z[23]) = 0; + (b[1] => z[23]) = 0; + (b[2] => z[23]) = 0; + (b[3] => z[23]) = 0; + (b[4] => z[23]) = 0; + (b[5] => z[23]) = 0; + (b[6] => z[23]) = 0; + (b[7] => z[23]) = 0; + (b[8] => z[23]) = 0; + (b[9] => z[23]) = 0; + (b[10] => z[23]) = 0; + (b[11] => z[23]) = 0; + (b[12] => z[23]) = 0; + (b[13] => z[23]) = 0; + (b[14] => z[23]) = 0; + (b[15] => z[23]) = 0; + (b[16] => z[23]) = 0; + (b[17] => z[23]) = 0; + (a[0] => z[24]) = 0; + (a[1] => z[24]) = 0; + (a[2] => z[24]) = 0; + (a[3] => z[24]) = 0; + (a[4] => z[24]) = 0; + (a[5] => z[24]) = 0; + (a[6] => z[24]) = 0; + (a[7] => z[24]) = 0; + (a[8] => z[24]) = 0; + (a[9] => z[24]) = 0; + (a[10] => z[24]) = 0; + (a[11] => z[24]) = 0; + (a[12] => z[24]) = 0; + (a[13] => z[24]) = 0; + (a[14] => z[24]) = 0; + (a[15] => z[24]) = 0; + (a[16] => z[24]) = 0; + (a[17] => z[24]) = 0; + (a[18] => z[24]) = 0; + (a[19] => z[24]) = 0; + (b[0] => z[24]) = 0; + (b[1] => z[24]) = 0; + (b[2] => z[24]) = 0; + (b[3] => z[24]) = 0; + (b[4] => z[24]) = 0; + (b[5] => z[24]) = 0; + (b[6] => z[24]) = 0; + (b[7] => z[24]) = 0; + (b[8] => z[24]) = 0; + (b[9] => z[24]) = 0; + (b[10] => z[24]) = 0; + (b[11] => z[24]) = 0; + (b[12] => z[24]) = 0; + (b[13] => z[24]) = 0; + (b[14] => z[24]) = 0; + (b[15] => z[24]) = 0; + (b[16] => z[24]) = 0; + (b[17] => z[24]) = 0; + (a[0] => z[25]) = 0; + (a[1] => z[25]) = 0; + (a[2] => z[25]) = 0; + (a[3] => z[25]) = 0; + (a[4] => z[25]) = 0; + (a[5] => z[25]) = 0; + (a[6] => z[25]) = 0; + (a[7] => z[25]) = 0; + (a[8] => z[25]) = 0; + (a[9] => z[25]) = 0; + (a[10] => z[25]) = 0; + (a[11] => z[25]) = 0; + (a[12] => z[25]) = 0; + (a[13] => z[25]) = 0; + (a[14] => z[25]) = 0; + (a[15] => z[25]) = 0; + (a[16] => z[25]) = 0; + (a[17] => z[25]) = 0; + (a[18] => z[25]) = 0; + (a[19] => z[25]) = 0; + (b[0] => z[25]) = 0; + (b[1] => z[25]) = 0; + (b[2] => z[25]) = 0; + (b[3] => z[25]) = 0; + (b[4] => z[25]) = 0; + (b[5] => z[25]) = 0; + (b[6] => z[25]) = 0; + (b[7] => z[25]) = 0; + (b[8] => z[25]) = 0; + (b[9] => z[25]) = 0; + (b[10] => z[25]) = 0; + (b[11] => z[25]) = 0; + (b[12] => z[25]) = 0; + (b[13] => z[25]) = 0; + (b[14] => z[25]) = 0; + (b[15] => z[25]) = 0; + (b[16] => z[25]) = 0; + (b[17] => z[25]) = 0; + (a[0] => z[26]) = 0; + (a[1] => z[26]) = 0; + (a[2] => z[26]) = 0; + (a[3] => z[26]) = 0; + (a[4] => z[26]) = 0; + (a[5] => z[26]) = 0; + (a[6] => z[26]) = 0; + (a[7] => z[26]) = 0; + (a[8] => z[26]) = 0; + (a[9] => z[26]) = 0; + (a[10] => z[26]) = 0; + (a[11] => z[26]) = 0; + (a[12] => z[26]) = 0; + (a[13] => z[26]) = 0; + (a[14] => z[26]) = 0; + (a[15] => z[26]) = 0; + (a[16] => z[26]) = 0; + (a[17] => z[26]) = 0; + (a[18] => z[26]) = 0; + (a[19] => z[26]) = 0; + (b[0] => z[26]) = 0; + (b[1] => z[26]) = 0; + (b[2] => z[26]) = 0; + (b[3] => z[26]) = 0; + (b[4] => z[26]) = 0; + (b[5] => z[26]) = 0; + (b[6] => z[26]) = 0; + (b[7] => z[26]) = 0; + (b[8] => z[26]) = 0; + (b[9] => z[26]) = 0; + (b[10] => z[26]) = 0; + (b[11] => z[26]) = 0; + (b[12] => z[26]) = 0; + (b[13] => z[26]) = 0; + (b[14] => z[26]) = 0; + (b[15] => z[26]) = 0; + (b[16] => z[26]) = 0; + (b[17] => z[26]) = 0; + (a[0] => z[27]) = 0; + (a[1] => z[27]) = 0; + (a[2] => z[27]) = 0; + (a[3] => z[27]) = 0; + (a[4] => z[27]) = 0; + (a[5] => z[27]) = 0; + (a[6] => z[27]) = 0; + (a[7] => z[27]) = 0; + (a[8] => z[27]) = 0; + (a[9] => z[27]) = 0; + (a[10] => z[27]) = 0; + (a[11] => z[27]) = 0; + (a[12] => z[27]) = 0; + (a[13] => z[27]) = 0; + (a[14] => z[27]) = 0; + (a[15] => z[27]) = 0; + (a[16] => z[27]) = 0; + (a[17] => z[27]) = 0; + (a[18] => z[27]) = 0; + (a[19] => z[27]) = 0; + (b[0] => z[27]) = 0; + (b[1] => z[27]) = 0; + (b[2] => z[27]) = 0; + (b[3] => z[27]) = 0; + (b[4] => z[27]) = 0; + (b[5] => z[27]) = 0; + (b[6] => z[27]) = 0; + (b[7] => z[27]) = 0; + (b[8] => z[27]) = 0; + (b[9] => z[27]) = 0; + (b[10] => z[27]) = 0; + (b[11] => z[27]) = 0; + (b[12] => z[27]) = 0; + (b[13] => z[27]) = 0; + (b[14] => z[27]) = 0; + (b[15] => z[27]) = 0; + (b[16] => z[27]) = 0; + (b[17] => z[27]) = 0; + (a[0] => z[28]) = 0; + (a[1] => z[28]) = 0; + (a[2] => z[28]) = 0; + (a[3] => z[28]) = 0; + (a[4] => z[28]) = 0; + (a[5] => z[28]) = 0; + (a[6] => z[28]) = 0; + (a[7] => z[28]) = 0; + (a[8] => z[28]) = 0; + (a[9] => z[28]) = 0; + (a[10] => z[28]) = 0; + (a[11] => z[28]) = 0; + (a[12] => z[28]) = 0; + (a[13] => z[28]) = 0; + (a[14] => z[28]) = 0; + (a[15] => z[28]) = 0; + (a[16] => z[28]) = 0; + (a[17] => z[28]) = 0; + (a[18] => z[28]) = 0; + (a[19] => z[28]) = 0; + (b[0] => z[28]) = 0; + (b[1] => z[28]) = 0; + (b[2] => z[28]) = 0; + (b[3] => z[28]) = 0; + (b[4] => z[28]) = 0; + (b[5] => z[28]) = 0; + (b[6] => z[28]) = 0; + (b[7] => z[28]) = 0; + (b[8] => z[28]) = 0; + (b[9] => z[28]) = 0; + (b[10] => z[28]) = 0; + (b[11] => z[28]) = 0; + (b[12] => z[28]) = 0; + (b[13] => z[28]) = 0; + (b[14] => z[28]) = 0; + (b[15] => z[28]) = 0; + (b[16] => z[28]) = 0; + (b[17] => z[28]) = 0; + (a[0] => z[29]) = 0; + (a[1] => z[29]) = 0; + (a[2] => z[29]) = 0; + (a[3] => z[29]) = 0; + (a[4] => z[29]) = 0; + (a[5] => z[29]) = 0; + (a[6] => z[29]) = 0; + (a[7] => z[29]) = 0; + (a[8] => z[29]) = 0; + (a[9] => z[29]) = 0; + (a[10] => z[29]) = 0; + (a[11] => z[29]) = 0; + (a[12] => z[29]) = 0; + (a[13] => z[29]) = 0; + (a[14] => z[29]) = 0; + (a[15] => z[29]) = 0; + (a[16] => z[29]) = 0; + (a[17] => z[29]) = 0; + (a[18] => z[29]) = 0; + (a[19] => z[29]) = 0; + (b[0] => z[29]) = 0; + (b[1] => z[29]) = 0; + (b[2] => z[29]) = 0; + (b[3] => z[29]) = 0; + (b[4] => z[29]) = 0; + (b[5] => z[29]) = 0; + (b[6] => z[29]) = 0; + (b[7] => z[29]) = 0; + (b[8] => z[29]) = 0; + (b[9] => z[29]) = 0; + (b[10] => z[29]) = 0; + (b[11] => z[29]) = 0; + (b[12] => z[29]) = 0; + (b[13] => z[29]) = 0; + (b[14] => z[29]) = 0; + (b[15] => z[29]) = 0; + (b[16] => z[29]) = 0; + (b[17] => z[29]) = 0; + (a[0] => z[30]) = 0; + (a[1] => z[30]) = 0; + (a[2] => z[30]) = 0; + (a[3] => z[30]) = 0; + (a[4] => z[30]) = 0; + (a[5] => z[30]) = 0; + (a[6] => z[30]) = 0; + (a[7] => z[30]) = 0; + (a[8] => z[30]) = 0; + (a[9] => z[30]) = 0; + (a[10] => z[30]) = 0; + (a[11] => z[30]) = 0; + (a[12] => z[30]) = 0; + (a[13] => z[30]) = 0; + (a[14] => z[30]) = 0; + (a[15] => z[30]) = 0; + (a[16] => z[30]) = 0; + (a[17] => z[30]) = 0; + (a[18] => z[30]) = 0; + (a[19] => z[30]) = 0; + (b[0] => z[30]) = 0; + (b[1] => z[30]) = 0; + (b[2] => z[30]) = 0; + (b[3] => z[30]) = 0; + (b[4] => z[30]) = 0; + (b[5] => z[30]) = 0; + (b[6] => z[30]) = 0; + (b[7] => z[30]) = 0; + (b[8] => z[30]) = 0; + (b[9] => z[30]) = 0; + (b[10] => z[30]) = 0; + (b[11] => z[30]) = 0; + (b[12] => z[30]) = 0; + (b[13] => z[30]) = 0; + (b[14] => z[30]) = 0; + (b[15] => z[30]) = 0; + (b[16] => z[30]) = 0; + (b[17] => z[30]) = 0; + (a[0] => z[31]) = 0; + (a[1] => z[31]) = 0; + (a[2] => z[31]) = 0; + (a[3] => z[31]) = 0; + (a[4] => z[31]) = 0; + (a[5] => z[31]) = 0; + (a[6] => z[31]) = 0; + (a[7] => z[31]) = 0; + (a[8] => z[31]) = 0; + (a[9] => z[31]) = 0; + (a[10] => z[31]) = 0; + (a[11] => z[31]) = 0; + (a[12] => z[31]) = 0; + (a[13] => z[31]) = 0; + (a[14] => z[31]) = 0; + (a[15] => z[31]) = 0; + (a[16] => z[31]) = 0; + (a[17] => z[31]) = 0; + (a[18] => z[31]) = 0; + (a[19] => z[31]) = 0; + (b[0] => z[31]) = 0; + (b[1] => z[31]) = 0; + (b[2] => z[31]) = 0; + (b[3] => z[31]) = 0; + (b[4] => z[31]) = 0; + (b[5] => z[31]) = 0; + (b[6] => z[31]) = 0; + (b[7] => z[31]) = 0; + (b[8] => z[31]) = 0; + (b[9] => z[31]) = 0; + (b[10] => z[31]) = 0; + (b[11] => z[31]) = 0; + (b[12] => z[31]) = 0; + (b[13] => z[31]) = 0; + (b[14] => z[31]) = 0; + (b[15] => z[31]) = 0; + (b[16] => z[31]) = 0; + (b[17] => z[31]) = 0; + (a[0] => z[32]) = 0; + (a[1] => z[32]) = 0; + (a[2] => z[32]) = 0; + (a[3] => z[32]) = 0; + (a[4] => z[32]) = 0; + (a[5] => z[32]) = 0; + (a[6] => z[32]) = 0; + (a[7] => z[32]) = 0; + (a[8] => z[32]) = 0; + (a[9] => z[32]) = 0; + (a[10] => z[32]) = 0; + (a[11] => z[32]) = 0; + (a[12] => z[32]) = 0; + (a[13] => z[32]) = 0; + (a[14] => z[32]) = 0; + (a[15] => z[32]) = 0; + (a[16] => z[32]) = 0; + (a[17] => z[32]) = 0; + (a[18] => z[32]) = 0; + (a[19] => z[32]) = 0; + (b[0] => z[32]) = 0; + (b[1] => z[32]) = 0; + (b[2] => z[32]) = 0; + (b[3] => z[32]) = 0; + (b[4] => z[32]) = 0; + (b[5] => z[32]) = 0; + (b[6] => z[32]) = 0; + (b[7] => z[32]) = 0; + (b[8] => z[32]) = 0; + (b[9] => z[32]) = 0; + (b[10] => z[32]) = 0; + (b[11] => z[32]) = 0; + (b[12] => z[32]) = 0; + (b[13] => z[32]) = 0; + (b[14] => z[32]) = 0; + (b[15] => z[32]) = 0; + (b[16] => z[32]) = 0; + (b[17] => z[32]) = 0; + (a[0] => z[33]) = 0; + (a[1] => z[33]) = 0; + (a[2] => z[33]) = 0; + (a[3] => z[33]) = 0; + (a[4] => z[33]) = 0; + (a[5] => z[33]) = 0; + (a[6] => z[33]) = 0; + (a[7] => z[33]) = 0; + (a[8] => z[33]) = 0; + (a[9] => z[33]) = 0; + (a[10] => z[33]) = 0; + (a[11] => z[33]) = 0; + (a[12] => z[33]) = 0; + (a[13] => z[33]) = 0; + (a[14] => z[33]) = 0; + (a[15] => z[33]) = 0; + (a[16] => z[33]) = 0; + (a[17] => z[33]) = 0; + (a[18] => z[33]) = 0; + (a[19] => z[33]) = 0; + (b[0] => z[33]) = 0; + (b[1] => z[33]) = 0; + (b[2] => z[33]) = 0; + (b[3] => z[33]) = 0; + (b[4] => z[33]) = 0; + (b[5] => z[33]) = 0; + (b[6] => z[33]) = 0; + (b[7] => z[33]) = 0; + (b[8] => z[33]) = 0; + (b[9] => z[33]) = 0; + (b[10] => z[33]) = 0; + (b[11] => z[33]) = 0; + (b[12] => z[33]) = 0; + (b[13] => z[33]) = 0; + (b[14] => z[33]) = 0; + (b[15] => z[33]) = 0; + (b[16] => z[33]) = 0; + (b[17] => z[33]) = 0; + (a[0] => z[34]) = 0; + (a[1] => z[34]) = 0; + (a[2] => z[34]) = 0; + (a[3] => z[34]) = 0; + (a[4] => z[34]) = 0; + (a[5] => z[34]) = 0; + (a[6] => z[34]) = 0; + (a[7] => z[34]) = 0; + (a[8] => z[34]) = 0; + (a[9] => z[34]) = 0; + (a[10] => z[34]) = 0; + (a[11] => z[34]) = 0; + (a[12] => z[34]) = 0; + (a[13] => z[34]) = 0; + (a[14] => z[34]) = 0; + (a[15] => z[34]) = 0; + (a[16] => z[34]) = 0; + (a[17] => z[34]) = 0; + (a[18] => z[34]) = 0; + (a[19] => z[34]) = 0; + (b[0] => z[34]) = 0; + (b[1] => z[34]) = 0; + (b[2] => z[34]) = 0; + (b[3] => z[34]) = 0; + (b[4] => z[34]) = 0; + (b[5] => z[34]) = 0; + (b[6] => z[34]) = 0; + (b[7] => z[34]) = 0; + (b[8] => z[34]) = 0; + (b[9] => z[34]) = 0; + (b[10] => z[34]) = 0; + (b[11] => z[34]) = 0; + (b[12] => z[34]) = 0; + (b[13] => z[34]) = 0; + (b[14] => z[34]) = 0; + (b[15] => z[34]) = 0; + (b[16] => z[34]) = 0; + (b[17] => z[34]) = 0; + (a[0] => z[35]) = 0; + (a[1] => z[35]) = 0; + (a[2] => z[35]) = 0; + (a[3] => z[35]) = 0; + (a[4] => z[35]) = 0; + (a[5] => z[35]) = 0; + (a[6] => z[35]) = 0; + (a[7] => z[35]) = 0; + (a[8] => z[35]) = 0; + (a[9] => z[35]) = 0; + (a[10] => z[35]) = 0; + (a[11] => z[35]) = 0; + (a[12] => z[35]) = 0; + (a[13] => z[35]) = 0; + (a[14] => z[35]) = 0; + (a[15] => z[35]) = 0; + (a[16] => z[35]) = 0; + (a[17] => z[35]) = 0; + (a[18] => z[35]) = 0; + (a[19] => z[35]) = 0; + (b[0] => z[35]) = 0; + (b[1] => z[35]) = 0; + (b[2] => z[35]) = 0; + (b[3] => z[35]) = 0; + (b[4] => z[35]) = 0; + (b[5] => z[35]) = 0; + (b[6] => z[35]) = 0; + (b[7] => z[35]) = 0; + (b[8] => z[35]) = 0; + (b[9] => z[35]) = 0; + (b[10] => z[35]) = 0; + (b[11] => z[35]) = 0; + (b[12] => z[35]) = 0; + (b[13] => z[35]) = 0; + (b[14] => z[35]) = 0; + (b[15] => z[35]) = 0; + (b[16] => z[35]) = 0; + (b[17] => z[35]) = 0; + (a[0] => z[36]) = 0; + (a[1] => z[36]) = 0; + (a[2] => z[36]) = 0; + (a[3] => z[36]) = 0; + (a[4] => z[36]) = 0; + (a[5] => z[36]) = 0; + (a[6] => z[36]) = 0; + (a[7] => z[36]) = 0; + (a[8] => z[36]) = 0; + (a[9] => z[36]) = 0; + (a[10] => z[36]) = 0; + (a[11] => z[36]) = 0; + (a[12] => z[36]) = 0; + (a[13] => z[36]) = 0; + (a[14] => z[36]) = 0; + (a[15] => z[36]) = 0; + (a[16] => z[36]) = 0; + (a[17] => z[36]) = 0; + (a[18] => z[36]) = 0; + (a[19] => z[36]) = 0; + (b[0] => z[36]) = 0; + (b[1] => z[36]) = 0; + (b[2] => z[36]) = 0; + (b[3] => z[36]) = 0; + (b[4] => z[36]) = 0; + (b[5] => z[36]) = 0; + (b[6] => z[36]) = 0; + (b[7] => z[36]) = 0; + (b[8] => z[36]) = 0; + (b[9] => z[36]) = 0; + (b[10] => z[36]) = 0; + (b[11] => z[36]) = 0; + (b[12] => z[36]) = 0; + (b[13] => z[36]) = 0; + (b[14] => z[36]) = 0; + (b[15] => z[36]) = 0; + (b[16] => z[36]) = 0; + (b[17] => z[36]) = 0; + (a[0] => z[37]) = 0; + (a[1] => z[37]) = 0; + (a[2] => z[37]) = 0; + (a[3] => z[37]) = 0; + (a[4] => z[37]) = 0; + (a[5] => z[37]) = 0; + (a[6] => z[37]) = 0; + (a[7] => z[37]) = 0; + (a[8] => z[37]) = 0; + (a[9] => z[37]) = 0; + (a[10] => z[37]) = 0; + (a[11] => z[37]) = 0; + (a[12] => z[37]) = 0; + (a[13] => z[37]) = 0; + (a[14] => z[37]) = 0; + (a[15] => z[37]) = 0; + (a[16] => z[37]) = 0; + (a[17] => z[37]) = 0; + (a[18] => z[37]) = 0; + (a[19] => z[37]) = 0; + (b[0] => z[37]) = 0; + (b[1] => z[37]) = 0; + (b[2] => z[37]) = 0; + (b[3] => z[37]) = 0; + (b[4] => z[37]) = 0; + (b[5] => z[37]) = 0; + (b[6] => z[37]) = 0; + (b[7] => z[37]) = 0; + (b[8] => z[37]) = 0; + (b[9] => z[37]) = 0; + (b[10] => z[37]) = 0; + (b[11] => z[37]) = 0; + (b[12] => z[37]) = 0; + (b[13] => z[37]) = 0; + (b[14] => z[37]) = 0; + (b[15] => z[37]) = 0; + (b[16] => z[37]) = 0; + (b[17] => z[37]) = 0; + endspecify +`endif + endmodule module QL_DSP2_MULT_REGIN ( // TODO: Name subject to change @@ -267,11 +1727,14 @@ module QL_DSP2_MULT_REGIN ( // TODO: Name subject to change ) dsp ( .a(a), .b(b), + .acc_fir(6'b0), .z(z), + .dly_b(), .f_mode(f_mode), .feedback(feedback), + .load_acc(1'b0), .unsigned_a(unsigned_a), .unsigned_b(unsigned_b), @@ -280,8 +1743,23 @@ module QL_DSP2_MULT_REGIN ( // TODO: Name subject to change .reset(reset), .output_select(output_select), // unregistered output: a * b (0) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), .register_inputs(register_inputs) // registered inputs ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + endmodule module QL_DSP2_MULT_REGOUT ( // TODO: Name subject to change @@ -313,11 +1791,14 @@ module QL_DSP2_MULT_REGOUT ( // TODO: Name subject to change ) dsp ( .a(a), .b(b), + .acc_fir(6'b0), .z(z), + .dly_b(), .f_mode(f_mode), .feedback(feedback), + .load_acc(1'b0), .unsigned_a(unsigned_a), .unsigned_b(unsigned_b), @@ -326,8 +1807,23 @@ module QL_DSP2_MULT_REGOUT ( // TODO: Name subject to change .reset(reset), .output_select(output_select), // registered output: a * b (4) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), .register_inputs(register_inputs) // unregistered inputs ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + endmodule module QL_DSP2_MULT_REGIN_REGOUT ( // TODO: Name subject to change @@ -359,11 +1855,14 @@ module QL_DSP2_MULT_REGIN_REGOUT ( // TODO: Name subject to change ) dsp ( .a(a), .b(b), + .acc_fir(6'b0), .z(z), + .dly_b(), .f_mode(f_mode), .feedback(feedback), + .load_acc(1'b0), .unsigned_a(unsigned_a), .unsigned_b(unsigned_b), @@ -372,8 +1871,23 @@ module QL_DSP2_MULT_REGIN_REGOUT ( // TODO: Name subject to change .reset(reset), .output_select(output_select), // registered output: a * b (4) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), .register_inputs(register_inputs) // registered inputs ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + endmodule module QL_DSP2_MULTADD ( @@ -410,6 +1924,7 @@ module QL_DSP2_MULTADD ( ) dsp ( .a(a), .b(b), + .dly_b(), .z(z), .f_mode(f_mode), @@ -421,6 +1936,7 @@ module QL_DSP2_MULTADD ( .unsigned_a(unsigned_a), .unsigned_b(unsigned_b), + //.clk(1'b0), .reset(reset), .output_select(output_select), // unregistered output: ACCin (2, 3) @@ -430,6 +1946,1722 @@ module QL_DSP2_MULTADD ( .subtract(subtract), .register_inputs(register_inputs) // unregistered inputs ); + +`ifdef SDF_SIM + specify + (a[0] => z[0]) = 0; + (a[1] => z[0]) = 0; + (a[2] => z[0]) = 0; + (a[3] => z[0]) = 0; + (a[4] => z[0]) = 0; + (a[5] => z[0]) = 0; + (a[6] => z[0]) = 0; + (a[7] => z[0]) = 0; + (a[8] => z[0]) = 0; + (a[9] => z[0]) = 0; + (a[10] => z[0]) = 0; + (a[11] => z[0]) = 0; + (a[12] => z[0]) = 0; + (a[13] => z[0]) = 0; + (a[14] => z[0]) = 0; + (a[15] => z[0]) = 0; + (a[16] => z[0]) = 0; + (a[17] => z[0]) = 0; + (a[18] => z[0]) = 0; + (a[19] => z[0]) = 0; + (b[0] => z[0]) = 0; + (b[1] => z[0]) = 0; + (b[2] => z[0]) = 0; + (b[3] => z[0]) = 0; + (b[4] => z[0]) = 0; + (b[5] => z[0]) = 0; + (b[6] => z[0]) = 0; + (b[7] => z[0]) = 0; + (b[8] => z[0]) = 0; + (b[9] => z[0]) = 0; + (b[10] => z[0]) = 0; + (b[11] => z[0]) = 0; + (b[12] => z[0]) = 0; + (b[13] => z[0]) = 0; + (b[14] => z[0]) = 0; + (b[15] => z[0]) = 0; + (b[16] => z[0]) = 0; + (b[17] => z[0]) = 0; + (a[0] => z[1]) = 0; + (a[1] => z[1]) = 0; + (a[2] => z[1]) = 0; + (a[3] => z[1]) = 0; + (a[4] => z[1]) = 0; + (a[5] => z[1]) = 0; + (a[6] => z[1]) = 0; + (a[7] => z[1]) = 0; + (a[8] => z[1]) = 0; + (a[9] => z[1]) = 0; + (a[10] => z[1]) = 0; + (a[11] => z[1]) = 0; + (a[12] => z[1]) = 0; + (a[13] => z[1]) = 0; + (a[14] => z[1]) = 0; + (a[15] => z[1]) = 0; + (a[16] => z[1]) = 0; + (a[17] => z[1]) = 0; + (a[18] => z[1]) = 0; + (a[19] => z[1]) = 0; + (b[0] => z[1]) = 0; + (b[1] => z[1]) = 0; + (b[2] => z[1]) = 0; + (b[3] => z[1]) = 0; + (b[4] => z[1]) = 0; + (b[5] => z[1]) = 0; + (b[6] => z[1]) = 0; + (b[7] => z[1]) = 0; + (b[8] => z[1]) = 0; + (b[9] => z[1]) = 0; + (b[10] => z[1]) = 0; + (b[11] => z[1]) = 0; + (b[12] => z[1]) = 0; + (b[13] => z[1]) = 0; + (b[14] => z[1]) = 0; + (b[15] => z[1]) = 0; + (b[16] => z[1]) = 0; + (b[17] => z[1]) = 0; + (a[0] => z[2]) = 0; + (a[1] => z[2]) = 0; + (a[2] => z[2]) = 0; + (a[3] => z[2]) = 0; + (a[4] => z[2]) = 0; + (a[5] => z[2]) = 0; + (a[6] => z[2]) = 0; + (a[7] => z[2]) = 0; + (a[8] => z[2]) = 0; + (a[9] => z[2]) = 0; + (a[10] => z[2]) = 0; + (a[11] => z[2]) = 0; + (a[12] => z[2]) = 0; + (a[13] => z[2]) = 0; + (a[14] => z[2]) = 0; + (a[15] => z[2]) = 0; + (a[16] => z[2]) = 0; + (a[17] => z[2]) = 0; + (a[18] => z[2]) = 0; + (a[19] => z[2]) = 0; + (b[0] => z[2]) = 0; + (b[1] => z[2]) = 0; + (b[2] => z[2]) = 0; + (b[3] => z[2]) = 0; + (b[4] => z[2]) = 0; + (b[5] => z[2]) = 0; + (b[6] => z[2]) = 0; + (b[7] => z[2]) = 0; + (b[8] => z[2]) = 0; + (b[9] => z[2]) = 0; + (b[10] => z[2]) = 0; + (b[11] => z[2]) = 0; + (b[12] => z[2]) = 0; + (b[13] => z[2]) = 0; + (b[14] => z[2]) = 0; + (b[15] => z[2]) = 0; + (b[16] => z[2]) = 0; + (b[17] => z[2]) = 0; + (a[0] => z[3]) = 0; + (a[1] => z[3]) = 0; + (a[2] => z[3]) = 0; + (a[3] => z[3]) = 0; + (a[4] => z[3]) = 0; + (a[5] => z[3]) = 0; + (a[6] => z[3]) = 0; + (a[7] => z[3]) = 0; + (a[8] => z[3]) = 0; + (a[9] => z[3]) = 0; + (a[10] => z[3]) = 0; + (a[11] => z[3]) = 0; + (a[12] => z[3]) = 0; + (a[13] => z[3]) = 0; + (a[14] => z[3]) = 0; + (a[15] => z[3]) = 0; + (a[16] => z[3]) = 0; + (a[17] => z[3]) = 0; + (a[18] => z[3]) = 0; + (a[19] => z[3]) = 0; + (b[0] => z[3]) = 0; + (b[1] => z[3]) = 0; + (b[2] => z[3]) = 0; + (b[3] => z[3]) = 0; + (b[4] => z[3]) = 0; + (b[5] => z[3]) = 0; + (b[6] => z[3]) = 0; + (b[7] => z[3]) = 0; + (b[8] => z[3]) = 0; + (b[9] => z[3]) = 0; + (b[10] => z[3]) = 0; + (b[11] => z[3]) = 0; + (b[12] => z[3]) = 0; + (b[13] => z[3]) = 0; + (b[14] => z[3]) = 0; + (b[15] => z[3]) = 0; + (b[16] => z[3]) = 0; + (b[17] => z[3]) = 0; + (a[0] => z[4]) = 0; + (a[1] => z[4]) = 0; + (a[2] => z[4]) = 0; + (a[3] => z[4]) = 0; + (a[4] => z[4]) = 0; + (a[5] => z[4]) = 0; + (a[6] => z[4]) = 0; + (a[7] => z[4]) = 0; + (a[8] => z[4]) = 0; + (a[9] => z[4]) = 0; + (a[10] => z[4]) = 0; + (a[11] => z[4]) = 0; + (a[12] => z[4]) = 0; + (a[13] => z[4]) = 0; + (a[14] => z[4]) = 0; + (a[15] => z[4]) = 0; + (a[16] => z[4]) = 0; + (a[17] => z[4]) = 0; + (a[18] => z[4]) = 0; + (a[19] => z[4]) = 0; + (b[0] => z[4]) = 0; + (b[1] => z[4]) = 0; + (b[2] => z[4]) = 0; + (b[3] => z[4]) = 0; + (b[4] => z[4]) = 0; + (b[5] => z[4]) = 0; + (b[6] => z[4]) = 0; + (b[7] => z[4]) = 0; + (b[8] => z[4]) = 0; + (b[9] => z[4]) = 0; + (b[10] => z[4]) = 0; + (b[11] => z[4]) = 0; + (b[12] => z[4]) = 0; + (b[13] => z[4]) = 0; + (b[14] => z[4]) = 0; + (b[15] => z[4]) = 0; + (b[16] => z[4]) = 0; + (b[17] => z[4]) = 0; + (a[0] => z[5]) = 0; + (a[1] => z[5]) = 0; + (a[2] => z[5]) = 0; + (a[3] => z[5]) = 0; + (a[4] => z[5]) = 0; + (a[5] => z[5]) = 0; + (a[6] => z[5]) = 0; + (a[7] => z[5]) = 0; + (a[8] => z[5]) = 0; + (a[9] => z[5]) = 0; + (a[10] => z[5]) = 0; + (a[11] => z[5]) = 0; + (a[12] => z[5]) = 0; + (a[13] => z[5]) = 0; + (a[14] => z[5]) = 0; + (a[15] => z[5]) = 0; + (a[16] => z[5]) = 0; + (a[17] => z[5]) = 0; + (a[18] => z[5]) = 0; + (a[19] => z[5]) = 0; + (b[0] => z[5]) = 0; + (b[1] => z[5]) = 0; + (b[2] => z[5]) = 0; + (b[3] => z[5]) = 0; + (b[4] => z[5]) = 0; + (b[5] => z[5]) = 0; + (b[6] => z[5]) = 0; + (b[7] => z[5]) = 0; + (b[8] => z[5]) = 0; + (b[9] => z[5]) = 0; + (b[10] => z[5]) = 0; + (b[11] => z[5]) = 0; + (b[12] => z[5]) = 0; + (b[13] => z[5]) = 0; + (b[14] => z[5]) = 0; + (b[15] => z[5]) = 0; + (b[16] => z[5]) = 0; + (b[17] => z[5]) = 0; + (a[0] => z[6]) = 0; + (a[1] => z[6]) = 0; + (a[2] => z[6]) = 0; + (a[3] => z[6]) = 0; + (a[4] => z[6]) = 0; + (a[5] => z[6]) = 0; + (a[6] => z[6]) = 0; + (a[7] => z[6]) = 0; + (a[8] => z[6]) = 0; + (a[9] => z[6]) = 0; + (a[10] => z[6]) = 0; + (a[11] => z[6]) = 0; + (a[12] => z[6]) = 0; + (a[13] => z[6]) = 0; + (a[14] => z[6]) = 0; + (a[15] => z[6]) = 0; + (a[16] => z[6]) = 0; + (a[17] => z[6]) = 0; + (a[18] => z[6]) = 0; + (a[19] => z[6]) = 0; + (b[0] => z[6]) = 0; + (b[1] => z[6]) = 0; + (b[2] => z[6]) = 0; + (b[3] => z[6]) = 0; + (b[4] => z[6]) = 0; + (b[5] => z[6]) = 0; + (b[6] => z[6]) = 0; + (b[7] => z[6]) = 0; + (b[8] => z[6]) = 0; + (b[9] => z[6]) = 0; + (b[10] => z[6]) = 0; + (b[11] => z[6]) = 0; + (b[12] => z[6]) = 0; + (b[13] => z[6]) = 0; + (b[14] => z[6]) = 0; + (b[15] => z[6]) = 0; + (b[16] => z[6]) = 0; + (b[17] => z[6]) = 0; + (a[0] => z[7]) = 0; + (a[1] => z[7]) = 0; + (a[2] => z[7]) = 0; + (a[3] => z[7]) = 0; + (a[4] => z[7]) = 0; + (a[5] => z[7]) = 0; + (a[6] => z[7]) = 0; + (a[7] => z[7]) = 0; + (a[8] => z[7]) = 0; + (a[9] => z[7]) = 0; + (a[10] => z[7]) = 0; + (a[11] => z[7]) = 0; + (a[12] => z[7]) = 0; + (a[13] => z[7]) = 0; + (a[14] => z[7]) = 0; + (a[15] => z[7]) = 0; + (a[16] => z[7]) = 0; + (a[17] => z[7]) = 0; + (a[18] => z[7]) = 0; + (a[19] => z[7]) = 0; + (b[0] => z[7]) = 0; + (b[1] => z[7]) = 0; + (b[2] => z[7]) = 0; + (b[3] => z[7]) = 0; + (b[4] => z[7]) = 0; + (b[5] => z[7]) = 0; + (b[6] => z[7]) = 0; + (b[7] => z[7]) = 0; + (b[8] => z[7]) = 0; + (b[9] => z[7]) = 0; + (b[10] => z[7]) = 0; + (b[11] => z[7]) = 0; + (b[12] => z[7]) = 0; + (b[13] => z[7]) = 0; + (b[14] => z[7]) = 0; + (b[15] => z[7]) = 0; + (b[16] => z[7]) = 0; + (b[17] => z[7]) = 0; + (a[0] => z[8]) = 0; + (a[1] => z[8]) = 0; + (a[2] => z[8]) = 0; + (a[3] => z[8]) = 0; + (a[4] => z[8]) = 0; + (a[5] => z[8]) = 0; + (a[6] => z[8]) = 0; + (a[7] => z[8]) = 0; + (a[8] => z[8]) = 0; + (a[9] => z[8]) = 0; + (a[10] => z[8]) = 0; + (a[11] => z[8]) = 0; + (a[12] => z[8]) = 0; + (a[13] => z[8]) = 0; + (a[14] => z[8]) = 0; + (a[15] => z[8]) = 0; + (a[16] => z[8]) = 0; + (a[17] => z[8]) = 0; + (a[18] => z[8]) = 0; + (a[19] => z[8]) = 0; + (b[0] => z[8]) = 0; + (b[1] => z[8]) = 0; + (b[2] => z[8]) = 0; + (b[3] => z[8]) = 0; + (b[4] => z[8]) = 0; + (b[5] => z[8]) = 0; + (b[6] => z[8]) = 0; + (b[7] => z[8]) = 0; + (b[8] => z[8]) = 0; + (b[9] => z[8]) = 0; + (b[10] => z[8]) = 0; + (b[11] => z[8]) = 0; + (b[12] => z[8]) = 0; + (b[13] => z[8]) = 0; + (b[14] => z[8]) = 0; + (b[15] => z[8]) = 0; + (b[16] => z[8]) = 0; + (b[17] => z[8]) = 0; + (a[0] => z[9]) = 0; + (a[1] => z[9]) = 0; + (a[2] => z[9]) = 0; + (a[3] => z[9]) = 0; + (a[4] => z[9]) = 0; + (a[5] => z[9]) = 0; + (a[6] => z[9]) = 0; + (a[7] => z[9]) = 0; + (a[8] => z[9]) = 0; + (a[9] => z[9]) = 0; + (a[10] => z[9]) = 0; + (a[11] => z[9]) = 0; + (a[12] => z[9]) = 0; + (a[13] => z[9]) = 0; + (a[14] => z[9]) = 0; + (a[15] => z[9]) = 0; + (a[16] => z[9]) = 0; + (a[17] => z[9]) = 0; + (a[18] => z[9]) = 0; + (a[19] => z[9]) = 0; + (b[0] => z[9]) = 0; + (b[1] => z[9]) = 0; + (b[2] => z[9]) = 0; + (b[3] => z[9]) = 0; + (b[4] => z[9]) = 0; + (b[5] => z[9]) = 0; + (b[6] => z[9]) = 0; + (b[7] => z[9]) = 0; + (b[8] => z[9]) = 0; + (b[9] => z[9]) = 0; + (b[10] => z[9]) = 0; + (b[11] => z[9]) = 0; + (b[12] => z[9]) = 0; + (b[13] => z[9]) = 0; + (b[14] => z[9]) = 0; + (b[15] => z[9]) = 0; + (b[16] => z[9]) = 0; + (b[17] => z[9]) = 0; + (a[0] => z[10]) = 0; + (a[1] => z[10]) = 0; + (a[2] => z[10]) = 0; + (a[3] => z[10]) = 0; + (a[4] => z[10]) = 0; + (a[5] => z[10]) = 0; + (a[6] => z[10]) = 0; + (a[7] => z[10]) = 0; + (a[8] => z[10]) = 0; + (a[9] => z[10]) = 0; + (a[10] => z[10]) = 0; + (a[11] => z[10]) = 0; + (a[12] => z[10]) = 0; + (a[13] => z[10]) = 0; + (a[14] => z[10]) = 0; + (a[15] => z[10]) = 0; + (a[16] => z[10]) = 0; + (a[17] => z[10]) = 0; + (a[18] => z[10]) = 0; + (a[19] => z[10]) = 0; + (b[0] => z[10]) = 0; + (b[1] => z[10]) = 0; + (b[2] => z[10]) = 0; + (b[3] => z[10]) = 0; + (b[4] => z[10]) = 0; + (b[5] => z[10]) = 0; + (b[6] => z[10]) = 0; + (b[7] => z[10]) = 0; + (b[8] => z[10]) = 0; + (b[9] => z[10]) = 0; + (b[10] => z[10]) = 0; + (b[11] => z[10]) = 0; + (b[12] => z[10]) = 0; + (b[13] => z[10]) = 0; + (b[14] => z[10]) = 0; + (b[15] => z[10]) = 0; + (b[16] => z[10]) = 0; + (b[17] => z[10]) = 0; + (a[0] => z[11]) = 0; + (a[1] => z[11]) = 0; + (a[2] => z[11]) = 0; + (a[3] => z[11]) = 0; + (a[4] => z[11]) = 0; + (a[5] => z[11]) = 0; + (a[6] => z[11]) = 0; + (a[7] => z[11]) = 0; + (a[8] => z[11]) = 0; + (a[9] => z[11]) = 0; + (a[10] => z[11]) = 0; + (a[11] => z[11]) = 0; + (a[12] => z[11]) = 0; + (a[13] => z[11]) = 0; + (a[14] => z[11]) = 0; + (a[15] => z[11]) = 0; + (a[16] => z[11]) = 0; + (a[17] => z[11]) = 0; + (a[18] => z[11]) = 0; + (a[19] => z[11]) = 0; + (b[0] => z[11]) = 0; + (b[1] => z[11]) = 0; + (b[2] => z[11]) = 0; + (b[3] => z[11]) = 0; + (b[4] => z[11]) = 0; + (b[5] => z[11]) = 0; + (b[6] => z[11]) = 0; + (b[7] => z[11]) = 0; + (b[8] => z[11]) = 0; + (b[9] => z[11]) = 0; + (b[10] => z[11]) = 0; + (b[11] => z[11]) = 0; + (b[12] => z[11]) = 0; + (b[13] => z[11]) = 0; + (b[14] => z[11]) = 0; + (b[15] => z[11]) = 0; + (b[16] => z[11]) = 0; + (b[17] => z[11]) = 0; + (a[0] => z[12]) = 0; + (a[1] => z[12]) = 0; + (a[2] => z[12]) = 0; + (a[3] => z[12]) = 0; + (a[4] => z[12]) = 0; + (a[5] => z[12]) = 0; + (a[6] => z[12]) = 0; + (a[7] => z[12]) = 0; + (a[8] => z[12]) = 0; + (a[9] => z[12]) = 0; + (a[10] => z[12]) = 0; + (a[11] => z[12]) = 0; + (a[12] => z[12]) = 0; + (a[13] => z[12]) = 0; + (a[14] => z[12]) = 0; + (a[15] => z[12]) = 0; + (a[16] => z[12]) = 0; + (a[17] => z[12]) = 0; + (a[18] => z[12]) = 0; + (a[19] => z[12]) = 0; + (b[0] => z[12]) = 0; + (b[1] => z[12]) = 0; + (b[2] => z[12]) = 0; + (b[3] => z[12]) = 0; + (b[4] => z[12]) = 0; + (b[5] => z[12]) = 0; + (b[6] => z[12]) = 0; + (b[7] => z[12]) = 0; + (b[8] => z[12]) = 0; + (b[9] => z[12]) = 0; + (b[10] => z[12]) = 0; + (b[11] => z[12]) = 0; + (b[12] => z[12]) = 0; + (b[13] => z[12]) = 0; + (b[14] => z[12]) = 0; + (b[15] => z[12]) = 0; + (b[16] => z[12]) = 0; + (b[17] => z[12]) = 0; + (a[0] => z[13]) = 0; + (a[1] => z[13]) = 0; + (a[2] => z[13]) = 0; + (a[3] => z[13]) = 0; + (a[4] => z[13]) = 0; + (a[5] => z[13]) = 0; + (a[6] => z[13]) = 0; + (a[7] => z[13]) = 0; + (a[8] => z[13]) = 0; + (a[9] => z[13]) = 0; + (a[10] => z[13]) = 0; + (a[11] => z[13]) = 0; + (a[12] => z[13]) = 0; + (a[13] => z[13]) = 0; + (a[14] => z[13]) = 0; + (a[15] => z[13]) = 0; + (a[16] => z[13]) = 0; + (a[17] => z[13]) = 0; + (a[18] => z[13]) = 0; + (a[19] => z[13]) = 0; + (b[0] => z[13]) = 0; + (b[1] => z[13]) = 0; + (b[2] => z[13]) = 0; + (b[3] => z[13]) = 0; + (b[4] => z[13]) = 0; + (b[5] => z[13]) = 0; + (b[6] => z[13]) = 0; + (b[7] => z[13]) = 0; + (b[8] => z[13]) = 0; + (b[9] => z[13]) = 0; + (b[10] => z[13]) = 0; + (b[11] => z[13]) = 0; + (b[12] => z[13]) = 0; + (b[13] => z[13]) = 0; + (b[14] => z[13]) = 0; + (b[15] => z[13]) = 0; + (b[16] => z[13]) = 0; + (b[17] => z[13]) = 0; + (a[0] => z[14]) = 0; + (a[1] => z[14]) = 0; + (a[2] => z[14]) = 0; + (a[3] => z[14]) = 0; + (a[4] => z[14]) = 0; + (a[5] => z[14]) = 0; + (a[6] => z[14]) = 0; + (a[7] => z[14]) = 0; + (a[8] => z[14]) = 0; + (a[9] => z[14]) = 0; + (a[10] => z[14]) = 0; + (a[11] => z[14]) = 0; + (a[12] => z[14]) = 0; + (a[13] => z[14]) = 0; + (a[14] => z[14]) = 0; + (a[15] => z[14]) = 0; + (a[16] => z[14]) = 0; + (a[17] => z[14]) = 0; + (a[18] => z[14]) = 0; + (a[19] => z[14]) = 0; + (b[0] => z[14]) = 0; + (b[1] => z[14]) = 0; + (b[2] => z[14]) = 0; + (b[3] => z[14]) = 0; + (b[4] => z[14]) = 0; + (b[5] => z[14]) = 0; + (b[6] => z[14]) = 0; + (b[7] => z[14]) = 0; + (b[8] => z[14]) = 0; + (b[9] => z[14]) = 0; + (b[10] => z[14]) = 0; + (b[11] => z[14]) = 0; + (b[12] => z[14]) = 0; + (b[13] => z[14]) = 0; + (b[14] => z[14]) = 0; + (b[15] => z[14]) = 0; + (b[16] => z[14]) = 0; + (b[17] => z[14]) = 0; + (a[0] => z[15]) = 0; + (a[1] => z[15]) = 0; + (a[2] => z[15]) = 0; + (a[3] => z[15]) = 0; + (a[4] => z[15]) = 0; + (a[5] => z[15]) = 0; + (a[6] => z[15]) = 0; + (a[7] => z[15]) = 0; + (a[8] => z[15]) = 0; + (a[9] => z[15]) = 0; + (a[10] => z[15]) = 0; + (a[11] => z[15]) = 0; + (a[12] => z[15]) = 0; + (a[13] => z[15]) = 0; + (a[14] => z[15]) = 0; + (a[15] => z[15]) = 0; + (a[16] => z[15]) = 0; + (a[17] => z[15]) = 0; + (a[18] => z[15]) = 0; + (a[19] => z[15]) = 0; + (b[0] => z[15]) = 0; + (b[1] => z[15]) = 0; + (b[2] => z[15]) = 0; + (b[3] => z[15]) = 0; + (b[4] => z[15]) = 0; + (b[5] => z[15]) = 0; + (b[6] => z[15]) = 0; + (b[7] => z[15]) = 0; + (b[8] => z[15]) = 0; + (b[9] => z[15]) = 0; + (b[10] => z[15]) = 0; + (b[11] => z[15]) = 0; + (b[12] => z[15]) = 0; + (b[13] => z[15]) = 0; + (b[14] => z[15]) = 0; + (b[15] => z[15]) = 0; + (b[16] => z[15]) = 0; + (b[17] => z[15]) = 0; + (a[0] => z[16]) = 0; + (a[1] => z[16]) = 0; + (a[2] => z[16]) = 0; + (a[3] => z[16]) = 0; + (a[4] => z[16]) = 0; + (a[5] => z[16]) = 0; + (a[6] => z[16]) = 0; + (a[7] => z[16]) = 0; + (a[8] => z[16]) = 0; + (a[9] => z[16]) = 0; + (a[10] => z[16]) = 0; + (a[11] => z[16]) = 0; + (a[12] => z[16]) = 0; + (a[13] => z[16]) = 0; + (a[14] => z[16]) = 0; + (a[15] => z[16]) = 0; + (a[16] => z[16]) = 0; + (a[17] => z[16]) = 0; + (a[18] => z[16]) = 0; + (a[19] => z[16]) = 0; + (b[0] => z[16]) = 0; + (b[1] => z[16]) = 0; + (b[2] => z[16]) = 0; + (b[3] => z[16]) = 0; + (b[4] => z[16]) = 0; + (b[5] => z[16]) = 0; + (b[6] => z[16]) = 0; + (b[7] => z[16]) = 0; + (b[8] => z[16]) = 0; + (b[9] => z[16]) = 0; + (b[10] => z[16]) = 0; + (b[11] => z[16]) = 0; + (b[12] => z[16]) = 0; + (b[13] => z[16]) = 0; + (b[14] => z[16]) = 0; + (b[15] => z[16]) = 0; + (b[16] => z[16]) = 0; + (b[17] => z[16]) = 0; + (a[0] => z[17]) = 0; + (a[1] => z[17]) = 0; + (a[2] => z[17]) = 0; + (a[3] => z[17]) = 0; + (a[4] => z[17]) = 0; + (a[5] => z[17]) = 0; + (a[6] => z[17]) = 0; + (a[7] => z[17]) = 0; + (a[8] => z[17]) = 0; + (a[9] => z[17]) = 0; + (a[10] => z[17]) = 0; + (a[11] => z[17]) = 0; + (a[12] => z[17]) = 0; + (a[13] => z[17]) = 0; + (a[14] => z[17]) = 0; + (a[15] => z[17]) = 0; + (a[16] => z[17]) = 0; + (a[17] => z[17]) = 0; + (a[18] => z[17]) = 0; + (a[19] => z[17]) = 0; + (b[0] => z[17]) = 0; + (b[1] => z[17]) = 0; + (b[2] => z[17]) = 0; + (b[3] => z[17]) = 0; + (b[4] => z[17]) = 0; + (b[5] => z[17]) = 0; + (b[6] => z[17]) = 0; + (b[7] => z[17]) = 0; + (b[8] => z[17]) = 0; + (b[9] => z[17]) = 0; + (b[10] => z[17]) = 0; + (b[11] => z[17]) = 0; + (b[12] => z[17]) = 0; + (b[13] => z[17]) = 0; + (b[14] => z[17]) = 0; + (b[15] => z[17]) = 0; + (b[16] => z[17]) = 0; + (b[17] => z[17]) = 0; + (a[0] => z[18]) = 0; + (a[1] => z[18]) = 0; + (a[2] => z[18]) = 0; + (a[3] => z[18]) = 0; + (a[4] => z[18]) = 0; + (a[5] => z[18]) = 0; + (a[6] => z[18]) = 0; + (a[7] => z[18]) = 0; + (a[8] => z[18]) = 0; + (a[9] => z[18]) = 0; + (a[10] => z[18]) = 0; + (a[11] => z[18]) = 0; + (a[12] => z[18]) = 0; + (a[13] => z[18]) = 0; + (a[14] => z[18]) = 0; + (a[15] => z[18]) = 0; + (a[16] => z[18]) = 0; + (a[17] => z[18]) = 0; + (a[18] => z[18]) = 0; + (a[19] => z[18]) = 0; + (b[0] => z[18]) = 0; + (b[1] => z[18]) = 0; + (b[2] => z[18]) = 0; + (b[3] => z[18]) = 0; + (b[4] => z[18]) = 0; + (b[5] => z[18]) = 0; + (b[6] => z[18]) = 0; + (b[7] => z[18]) = 0; + (b[8] => z[18]) = 0; + (b[9] => z[18]) = 0; + (b[10] => z[18]) = 0; + (b[11] => z[18]) = 0; + (b[12] => z[18]) = 0; + (b[13] => z[18]) = 0; + (b[14] => z[18]) = 0; + (b[15] => z[18]) = 0; + (b[16] => z[18]) = 0; + (b[17] => z[18]) = 0; + (a[0] => z[19]) = 0; + (a[1] => z[19]) = 0; + (a[2] => z[19]) = 0; + (a[3] => z[19]) = 0; + (a[4] => z[19]) = 0; + (a[5] => z[19]) = 0; + (a[6] => z[19]) = 0; + (a[7] => z[19]) = 0; + (a[8] => z[19]) = 0; + (a[9] => z[19]) = 0; + (a[10] => z[19]) = 0; + (a[11] => z[19]) = 0; + (a[12] => z[19]) = 0; + (a[13] => z[19]) = 0; + (a[14] => z[19]) = 0; + (a[15] => z[19]) = 0; + (a[16] => z[19]) = 0; + (a[17] => z[19]) = 0; + (a[18] => z[19]) = 0; + (a[19] => z[19]) = 0; + (b[0] => z[19]) = 0; + (b[1] => z[19]) = 0; + (b[2] => z[19]) = 0; + (b[3] => z[19]) = 0; + (b[4] => z[19]) = 0; + (b[5] => z[19]) = 0; + (b[6] => z[19]) = 0; + (b[7] => z[19]) = 0; + (b[8] => z[19]) = 0; + (b[9] => z[19]) = 0; + (b[10] => z[19]) = 0; + (b[11] => z[19]) = 0; + (b[12] => z[19]) = 0; + (b[13] => z[19]) = 0; + (b[14] => z[19]) = 0; + (b[15] => z[19]) = 0; + (b[16] => z[19]) = 0; + (b[17] => z[19]) = 0; + (a[0] => z[20]) = 0; + (a[1] => z[20]) = 0; + (a[2] => z[20]) = 0; + (a[3] => z[20]) = 0; + (a[4] => z[20]) = 0; + (a[5] => z[20]) = 0; + (a[6] => z[20]) = 0; + (a[7] => z[20]) = 0; + (a[8] => z[20]) = 0; + (a[9] => z[20]) = 0; + (a[10] => z[20]) = 0; + (a[11] => z[20]) = 0; + (a[12] => z[20]) = 0; + (a[13] => z[20]) = 0; + (a[14] => z[20]) = 0; + (a[15] => z[20]) = 0; + (a[16] => z[20]) = 0; + (a[17] => z[20]) = 0; + (a[18] => z[20]) = 0; + (a[19] => z[20]) = 0; + (b[0] => z[20]) = 0; + (b[1] => z[20]) = 0; + (b[2] => z[20]) = 0; + (b[3] => z[20]) = 0; + (b[4] => z[20]) = 0; + (b[5] => z[20]) = 0; + (b[6] => z[20]) = 0; + (b[7] => z[20]) = 0; + (b[8] => z[20]) = 0; + (b[9] => z[20]) = 0; + (b[10] => z[20]) = 0; + (b[11] => z[20]) = 0; + (b[12] => z[20]) = 0; + (b[13] => z[20]) = 0; + (b[14] => z[20]) = 0; + (b[15] => z[20]) = 0; + (b[16] => z[20]) = 0; + (b[17] => z[20]) = 0; + (a[0] => z[21]) = 0; + (a[1] => z[21]) = 0; + (a[2] => z[21]) = 0; + (a[3] => z[21]) = 0; + (a[4] => z[21]) = 0; + (a[5] => z[21]) = 0; + (a[6] => z[21]) = 0; + (a[7] => z[21]) = 0; + (a[8] => z[21]) = 0; + (a[9] => z[21]) = 0; + (a[10] => z[21]) = 0; + (a[11] => z[21]) = 0; + (a[12] => z[21]) = 0; + (a[13] => z[21]) = 0; + (a[14] => z[21]) = 0; + (a[15] => z[21]) = 0; + (a[16] => z[21]) = 0; + (a[17] => z[21]) = 0; + (a[18] => z[21]) = 0; + (a[19] => z[21]) = 0; + (b[0] => z[21]) = 0; + (b[1] => z[21]) = 0; + (b[2] => z[21]) = 0; + (b[3] => z[21]) = 0; + (b[4] => z[21]) = 0; + (b[5] => z[21]) = 0; + (b[6] => z[21]) = 0; + (b[7] => z[21]) = 0; + (b[8] => z[21]) = 0; + (b[9] => z[21]) = 0; + (b[10] => z[21]) = 0; + (b[11] => z[21]) = 0; + (b[12] => z[21]) = 0; + (b[13] => z[21]) = 0; + (b[14] => z[21]) = 0; + (b[15] => z[21]) = 0; + (b[16] => z[21]) = 0; + (b[17] => z[21]) = 0; + (a[0] => z[22]) = 0; + (a[1] => z[22]) = 0; + (a[2] => z[22]) = 0; + (a[3] => z[22]) = 0; + (a[4] => z[22]) = 0; + (a[5] => z[22]) = 0; + (a[6] => z[22]) = 0; + (a[7] => z[22]) = 0; + (a[8] => z[22]) = 0; + (a[9] => z[22]) = 0; + (a[10] => z[22]) = 0; + (a[11] => z[22]) = 0; + (a[12] => z[22]) = 0; + (a[13] => z[22]) = 0; + (a[14] => z[22]) = 0; + (a[15] => z[22]) = 0; + (a[16] => z[22]) = 0; + (a[17] => z[22]) = 0; + (a[18] => z[22]) = 0; + (a[19] => z[22]) = 0; + (b[0] => z[22]) = 0; + (b[1] => z[22]) = 0; + (b[2] => z[22]) = 0; + (b[3] => z[22]) = 0; + (b[4] => z[22]) = 0; + (b[5] => z[22]) = 0; + (b[6] => z[22]) = 0; + (b[7] => z[22]) = 0; + (b[8] => z[22]) = 0; + (b[9] => z[22]) = 0; + (b[10] => z[22]) = 0; + (b[11] => z[22]) = 0; + (b[12] => z[22]) = 0; + (b[13] => z[22]) = 0; + (b[14] => z[22]) = 0; + (b[15] => z[22]) = 0; + (b[16] => z[22]) = 0; + (b[17] => z[22]) = 0; + (a[0] => z[23]) = 0; + (a[1] => z[23]) = 0; + (a[2] => z[23]) = 0; + (a[3] => z[23]) = 0; + (a[4] => z[23]) = 0; + (a[5] => z[23]) = 0; + (a[6] => z[23]) = 0; + (a[7] => z[23]) = 0; + (a[8] => z[23]) = 0; + (a[9] => z[23]) = 0; + (a[10] => z[23]) = 0; + (a[11] => z[23]) = 0; + (a[12] => z[23]) = 0; + (a[13] => z[23]) = 0; + (a[14] => z[23]) = 0; + (a[15] => z[23]) = 0; + (a[16] => z[23]) = 0; + (a[17] => z[23]) = 0; + (a[18] => z[23]) = 0; + (a[19] => z[23]) = 0; + (b[0] => z[23]) = 0; + (b[1] => z[23]) = 0; + (b[2] => z[23]) = 0; + (b[3] => z[23]) = 0; + (b[4] => z[23]) = 0; + (b[5] => z[23]) = 0; + (b[6] => z[23]) = 0; + (b[7] => z[23]) = 0; + (b[8] => z[23]) = 0; + (b[9] => z[23]) = 0; + (b[10] => z[23]) = 0; + (b[11] => z[23]) = 0; + (b[12] => z[23]) = 0; + (b[13] => z[23]) = 0; + (b[14] => z[23]) = 0; + (b[15] => z[23]) = 0; + (b[16] => z[23]) = 0; + (b[17] => z[23]) = 0; + (a[0] => z[24]) = 0; + (a[1] => z[24]) = 0; + (a[2] => z[24]) = 0; + (a[3] => z[24]) = 0; + (a[4] => z[24]) = 0; + (a[5] => z[24]) = 0; + (a[6] => z[24]) = 0; + (a[7] => z[24]) = 0; + (a[8] => z[24]) = 0; + (a[9] => z[24]) = 0; + (a[10] => z[24]) = 0; + (a[11] => z[24]) = 0; + (a[12] => z[24]) = 0; + (a[13] => z[24]) = 0; + (a[14] => z[24]) = 0; + (a[15] => z[24]) = 0; + (a[16] => z[24]) = 0; + (a[17] => z[24]) = 0; + (a[18] => z[24]) = 0; + (a[19] => z[24]) = 0; + (b[0] => z[24]) = 0; + (b[1] => z[24]) = 0; + (b[2] => z[24]) = 0; + (b[3] => z[24]) = 0; + (b[4] => z[24]) = 0; + (b[5] => z[24]) = 0; + (b[6] => z[24]) = 0; + (b[7] => z[24]) = 0; + (b[8] => z[24]) = 0; + (b[9] => z[24]) = 0; + (b[10] => z[24]) = 0; + (b[11] => z[24]) = 0; + (b[12] => z[24]) = 0; + (b[13] => z[24]) = 0; + (b[14] => z[24]) = 0; + (b[15] => z[24]) = 0; + (b[16] => z[24]) = 0; + (b[17] => z[24]) = 0; + (a[0] => z[25]) = 0; + (a[1] => z[25]) = 0; + (a[2] => z[25]) = 0; + (a[3] => z[25]) = 0; + (a[4] => z[25]) = 0; + (a[5] => z[25]) = 0; + (a[6] => z[25]) = 0; + (a[7] => z[25]) = 0; + (a[8] => z[25]) = 0; + (a[9] => z[25]) = 0; + (a[10] => z[25]) = 0; + (a[11] => z[25]) = 0; + (a[12] => z[25]) = 0; + (a[13] => z[25]) = 0; + (a[14] => z[25]) = 0; + (a[15] => z[25]) = 0; + (a[16] => z[25]) = 0; + (a[17] => z[25]) = 0; + (a[18] => z[25]) = 0; + (a[19] => z[25]) = 0; + (b[0] => z[25]) = 0; + (b[1] => z[25]) = 0; + (b[2] => z[25]) = 0; + (b[3] => z[25]) = 0; + (b[4] => z[25]) = 0; + (b[5] => z[25]) = 0; + (b[6] => z[25]) = 0; + (b[7] => z[25]) = 0; + (b[8] => z[25]) = 0; + (b[9] => z[25]) = 0; + (b[10] => z[25]) = 0; + (b[11] => z[25]) = 0; + (b[12] => z[25]) = 0; + (b[13] => z[25]) = 0; + (b[14] => z[25]) = 0; + (b[15] => z[25]) = 0; + (b[16] => z[25]) = 0; + (b[17] => z[25]) = 0; + (a[0] => z[26]) = 0; + (a[1] => z[26]) = 0; + (a[2] => z[26]) = 0; + (a[3] => z[26]) = 0; + (a[4] => z[26]) = 0; + (a[5] => z[26]) = 0; + (a[6] => z[26]) = 0; + (a[7] => z[26]) = 0; + (a[8] => z[26]) = 0; + (a[9] => z[26]) = 0; + (a[10] => z[26]) = 0; + (a[11] => z[26]) = 0; + (a[12] => z[26]) = 0; + (a[13] => z[26]) = 0; + (a[14] => z[26]) = 0; + (a[15] => z[26]) = 0; + (a[16] => z[26]) = 0; + (a[17] => z[26]) = 0; + (a[18] => z[26]) = 0; + (a[19] => z[26]) = 0; + (b[0] => z[26]) = 0; + (b[1] => z[26]) = 0; + (b[2] => z[26]) = 0; + (b[3] => z[26]) = 0; + (b[4] => z[26]) = 0; + (b[5] => z[26]) = 0; + (b[6] => z[26]) = 0; + (b[7] => z[26]) = 0; + (b[8] => z[26]) = 0; + (b[9] => z[26]) = 0; + (b[10] => z[26]) = 0; + (b[11] => z[26]) = 0; + (b[12] => z[26]) = 0; + (b[13] => z[26]) = 0; + (b[14] => z[26]) = 0; + (b[15] => z[26]) = 0; + (b[16] => z[26]) = 0; + (b[17] => z[26]) = 0; + (a[0] => z[27]) = 0; + (a[1] => z[27]) = 0; + (a[2] => z[27]) = 0; + (a[3] => z[27]) = 0; + (a[4] => z[27]) = 0; + (a[5] => z[27]) = 0; + (a[6] => z[27]) = 0; + (a[7] => z[27]) = 0; + (a[8] => z[27]) = 0; + (a[9] => z[27]) = 0; + (a[10] => z[27]) = 0; + (a[11] => z[27]) = 0; + (a[12] => z[27]) = 0; + (a[13] => z[27]) = 0; + (a[14] => z[27]) = 0; + (a[15] => z[27]) = 0; + (a[16] => z[27]) = 0; + (a[17] => z[27]) = 0; + (a[18] => z[27]) = 0; + (a[19] => z[27]) = 0; + (b[0] => z[27]) = 0; + (b[1] => z[27]) = 0; + (b[2] => z[27]) = 0; + (b[3] => z[27]) = 0; + (b[4] => z[27]) = 0; + (b[5] => z[27]) = 0; + (b[6] => z[27]) = 0; + (b[7] => z[27]) = 0; + (b[8] => z[27]) = 0; + (b[9] => z[27]) = 0; + (b[10] => z[27]) = 0; + (b[11] => z[27]) = 0; + (b[12] => z[27]) = 0; + (b[13] => z[27]) = 0; + (b[14] => z[27]) = 0; + (b[15] => z[27]) = 0; + (b[16] => z[27]) = 0; + (b[17] => z[27]) = 0; + (a[0] => z[28]) = 0; + (a[1] => z[28]) = 0; + (a[2] => z[28]) = 0; + (a[3] => z[28]) = 0; + (a[4] => z[28]) = 0; + (a[5] => z[28]) = 0; + (a[6] => z[28]) = 0; + (a[7] => z[28]) = 0; + (a[8] => z[28]) = 0; + (a[9] => z[28]) = 0; + (a[10] => z[28]) = 0; + (a[11] => z[28]) = 0; + (a[12] => z[28]) = 0; + (a[13] => z[28]) = 0; + (a[14] => z[28]) = 0; + (a[15] => z[28]) = 0; + (a[16] => z[28]) = 0; + (a[17] => z[28]) = 0; + (a[18] => z[28]) = 0; + (a[19] => z[28]) = 0; + (b[0] => z[28]) = 0; + (b[1] => z[28]) = 0; + (b[2] => z[28]) = 0; + (b[3] => z[28]) = 0; + (b[4] => z[28]) = 0; + (b[5] => z[28]) = 0; + (b[6] => z[28]) = 0; + (b[7] => z[28]) = 0; + (b[8] => z[28]) = 0; + (b[9] => z[28]) = 0; + (b[10] => z[28]) = 0; + (b[11] => z[28]) = 0; + (b[12] => z[28]) = 0; + (b[13] => z[28]) = 0; + (b[14] => z[28]) = 0; + (b[15] => z[28]) = 0; + (b[16] => z[28]) = 0; + (b[17] => z[28]) = 0; + (a[0] => z[29]) = 0; + (a[1] => z[29]) = 0; + (a[2] => z[29]) = 0; + (a[3] => z[29]) = 0; + (a[4] => z[29]) = 0; + (a[5] => z[29]) = 0; + (a[6] => z[29]) = 0; + (a[7] => z[29]) = 0; + (a[8] => z[29]) = 0; + (a[9] => z[29]) = 0; + (a[10] => z[29]) = 0; + (a[11] => z[29]) = 0; + (a[12] => z[29]) = 0; + (a[13] => z[29]) = 0; + (a[14] => z[29]) = 0; + (a[15] => z[29]) = 0; + (a[16] => z[29]) = 0; + (a[17] => z[29]) = 0; + (a[18] => z[29]) = 0; + (a[19] => z[29]) = 0; + (b[0] => z[29]) = 0; + (b[1] => z[29]) = 0; + (b[2] => z[29]) = 0; + (b[3] => z[29]) = 0; + (b[4] => z[29]) = 0; + (b[5] => z[29]) = 0; + (b[6] => z[29]) = 0; + (b[7] => z[29]) = 0; + (b[8] => z[29]) = 0; + (b[9] => z[29]) = 0; + (b[10] => z[29]) = 0; + (b[11] => z[29]) = 0; + (b[12] => z[29]) = 0; + (b[13] => z[29]) = 0; + (b[14] => z[29]) = 0; + (b[15] => z[29]) = 0; + (b[16] => z[29]) = 0; + (b[17] => z[29]) = 0; + (a[0] => z[30]) = 0; + (a[1] => z[30]) = 0; + (a[2] => z[30]) = 0; + (a[3] => z[30]) = 0; + (a[4] => z[30]) = 0; + (a[5] => z[30]) = 0; + (a[6] => z[30]) = 0; + (a[7] => z[30]) = 0; + (a[8] => z[30]) = 0; + (a[9] => z[30]) = 0; + (a[10] => z[30]) = 0; + (a[11] => z[30]) = 0; + (a[12] => z[30]) = 0; + (a[13] => z[30]) = 0; + (a[14] => z[30]) = 0; + (a[15] => z[30]) = 0; + (a[16] => z[30]) = 0; + (a[17] => z[30]) = 0; + (a[18] => z[30]) = 0; + (a[19] => z[30]) = 0; + (b[0] => z[30]) = 0; + (b[1] => z[30]) = 0; + (b[2] => z[30]) = 0; + (b[3] => z[30]) = 0; + (b[4] => z[30]) = 0; + (b[5] => z[30]) = 0; + (b[6] => z[30]) = 0; + (b[7] => z[30]) = 0; + (b[8] => z[30]) = 0; + (b[9] => z[30]) = 0; + (b[10] => z[30]) = 0; + (b[11] => z[30]) = 0; + (b[12] => z[30]) = 0; + (b[13] => z[30]) = 0; + (b[14] => z[30]) = 0; + (b[15] => z[30]) = 0; + (b[16] => z[30]) = 0; + (b[17] => z[30]) = 0; + (a[0] => z[31]) = 0; + (a[1] => z[31]) = 0; + (a[2] => z[31]) = 0; + (a[3] => z[31]) = 0; + (a[4] => z[31]) = 0; + (a[5] => z[31]) = 0; + (a[6] => z[31]) = 0; + (a[7] => z[31]) = 0; + (a[8] => z[31]) = 0; + (a[9] => z[31]) = 0; + (a[10] => z[31]) = 0; + (a[11] => z[31]) = 0; + (a[12] => z[31]) = 0; + (a[13] => z[31]) = 0; + (a[14] => z[31]) = 0; + (a[15] => z[31]) = 0; + (a[16] => z[31]) = 0; + (a[17] => z[31]) = 0; + (a[18] => z[31]) = 0; + (a[19] => z[31]) = 0; + (b[0] => z[31]) = 0; + (b[1] => z[31]) = 0; + (b[2] => z[31]) = 0; + (b[3] => z[31]) = 0; + (b[4] => z[31]) = 0; + (b[5] => z[31]) = 0; + (b[6] => z[31]) = 0; + (b[7] => z[31]) = 0; + (b[8] => z[31]) = 0; + (b[9] => z[31]) = 0; + (b[10] => z[31]) = 0; + (b[11] => z[31]) = 0; + (b[12] => z[31]) = 0; + (b[13] => z[31]) = 0; + (b[14] => z[31]) = 0; + (b[15] => z[31]) = 0; + (b[16] => z[31]) = 0; + (b[17] => z[31]) = 0; + (a[0] => z[32]) = 0; + (a[1] => z[32]) = 0; + (a[2] => z[32]) = 0; + (a[3] => z[32]) = 0; + (a[4] => z[32]) = 0; + (a[5] => z[32]) = 0; + (a[6] => z[32]) = 0; + (a[7] => z[32]) = 0; + (a[8] => z[32]) = 0; + (a[9] => z[32]) = 0; + (a[10] => z[32]) = 0; + (a[11] => z[32]) = 0; + (a[12] => z[32]) = 0; + (a[13] => z[32]) = 0; + (a[14] => z[32]) = 0; + (a[15] => z[32]) = 0; + (a[16] => z[32]) = 0; + (a[17] => z[32]) = 0; + (a[18] => z[32]) = 0; + (a[19] => z[32]) = 0; + (b[0] => z[32]) = 0; + (b[1] => z[32]) = 0; + (b[2] => z[32]) = 0; + (b[3] => z[32]) = 0; + (b[4] => z[32]) = 0; + (b[5] => z[32]) = 0; + (b[6] => z[32]) = 0; + (b[7] => z[32]) = 0; + (b[8] => z[32]) = 0; + (b[9] => z[32]) = 0; + (b[10] => z[32]) = 0; + (b[11] => z[32]) = 0; + (b[12] => z[32]) = 0; + (b[13] => z[32]) = 0; + (b[14] => z[32]) = 0; + (b[15] => z[32]) = 0; + (b[16] => z[32]) = 0; + (b[17] => z[32]) = 0; + (a[0] => z[33]) = 0; + (a[1] => z[33]) = 0; + (a[2] => z[33]) = 0; + (a[3] => z[33]) = 0; + (a[4] => z[33]) = 0; + (a[5] => z[33]) = 0; + (a[6] => z[33]) = 0; + (a[7] => z[33]) = 0; + (a[8] => z[33]) = 0; + (a[9] => z[33]) = 0; + (a[10] => z[33]) = 0; + (a[11] => z[33]) = 0; + (a[12] => z[33]) = 0; + (a[13] => z[33]) = 0; + (a[14] => z[33]) = 0; + (a[15] => z[33]) = 0; + (a[16] => z[33]) = 0; + (a[17] => z[33]) = 0; + (a[18] => z[33]) = 0; + (a[19] => z[33]) = 0; + (b[0] => z[33]) = 0; + (b[1] => z[33]) = 0; + (b[2] => z[33]) = 0; + (b[3] => z[33]) = 0; + (b[4] => z[33]) = 0; + (b[5] => z[33]) = 0; + (b[6] => z[33]) = 0; + (b[7] => z[33]) = 0; + (b[8] => z[33]) = 0; + (b[9] => z[33]) = 0; + (b[10] => z[33]) = 0; + (b[11] => z[33]) = 0; + (b[12] => z[33]) = 0; + (b[13] => z[33]) = 0; + (b[14] => z[33]) = 0; + (b[15] => z[33]) = 0; + (b[16] => z[33]) = 0; + (b[17] => z[33]) = 0; + (a[0] => z[34]) = 0; + (a[1] => z[34]) = 0; + (a[2] => z[34]) = 0; + (a[3] => z[34]) = 0; + (a[4] => z[34]) = 0; + (a[5] => z[34]) = 0; + (a[6] => z[34]) = 0; + (a[7] => z[34]) = 0; + (a[8] => z[34]) = 0; + (a[9] => z[34]) = 0; + (a[10] => z[34]) = 0; + (a[11] => z[34]) = 0; + (a[12] => z[34]) = 0; + (a[13] => z[34]) = 0; + (a[14] => z[34]) = 0; + (a[15] => z[34]) = 0; + (a[16] => z[34]) = 0; + (a[17] => z[34]) = 0; + (a[18] => z[34]) = 0; + (a[19] => z[34]) = 0; + (b[0] => z[34]) = 0; + (b[1] => z[34]) = 0; + (b[2] => z[34]) = 0; + (b[3] => z[34]) = 0; + (b[4] => z[34]) = 0; + (b[5] => z[34]) = 0; + (b[6] => z[34]) = 0; + (b[7] => z[34]) = 0; + (b[8] => z[34]) = 0; + (b[9] => z[34]) = 0; + (b[10] => z[34]) = 0; + (b[11] => z[34]) = 0; + (b[12] => z[34]) = 0; + (b[13] => z[34]) = 0; + (b[14] => z[34]) = 0; + (b[15] => z[34]) = 0; + (b[16] => z[34]) = 0; + (b[17] => z[34]) = 0; + (a[0] => z[35]) = 0; + (a[1] => z[35]) = 0; + (a[2] => z[35]) = 0; + (a[3] => z[35]) = 0; + (a[4] => z[35]) = 0; + (a[5] => z[35]) = 0; + (a[6] => z[35]) = 0; + (a[7] => z[35]) = 0; + (a[8] => z[35]) = 0; + (a[9] => z[35]) = 0; + (a[10] => z[35]) = 0; + (a[11] => z[35]) = 0; + (a[12] => z[35]) = 0; + (a[13] => z[35]) = 0; + (a[14] => z[35]) = 0; + (a[15] => z[35]) = 0; + (a[16] => z[35]) = 0; + (a[17] => z[35]) = 0; + (a[18] => z[35]) = 0; + (a[19] => z[35]) = 0; + (b[0] => z[35]) = 0; + (b[1] => z[35]) = 0; + (b[2] => z[35]) = 0; + (b[3] => z[35]) = 0; + (b[4] => z[35]) = 0; + (b[5] => z[35]) = 0; + (b[6] => z[35]) = 0; + (b[7] => z[35]) = 0; + (b[8] => z[35]) = 0; + (b[9] => z[35]) = 0; + (b[10] => z[35]) = 0; + (b[11] => z[35]) = 0; + (b[12] => z[35]) = 0; + (b[13] => z[35]) = 0; + (b[14] => z[35]) = 0; + (b[15] => z[35]) = 0; + (b[16] => z[35]) = 0; + (b[17] => z[35]) = 0; + (a[0] => z[36]) = 0; + (a[1] => z[36]) = 0; + (a[2] => z[36]) = 0; + (a[3] => z[36]) = 0; + (a[4] => z[36]) = 0; + (a[5] => z[36]) = 0; + (a[6] => z[36]) = 0; + (a[7] => z[36]) = 0; + (a[8] => z[36]) = 0; + (a[9] => z[36]) = 0; + (a[10] => z[36]) = 0; + (a[11] => z[36]) = 0; + (a[12] => z[36]) = 0; + (a[13] => z[36]) = 0; + (a[14] => z[36]) = 0; + (a[15] => z[36]) = 0; + (a[16] => z[36]) = 0; + (a[17] => z[36]) = 0; + (a[18] => z[36]) = 0; + (a[19] => z[36]) = 0; + (b[0] => z[36]) = 0; + (b[1] => z[36]) = 0; + (b[2] => z[36]) = 0; + (b[3] => z[36]) = 0; + (b[4] => z[36]) = 0; + (b[5] => z[36]) = 0; + (b[6] => z[36]) = 0; + (b[7] => z[36]) = 0; + (b[8] => z[36]) = 0; + (b[9] => z[36]) = 0; + (b[10] => z[36]) = 0; + (b[11] => z[36]) = 0; + (b[12] => z[36]) = 0; + (b[13] => z[36]) = 0; + (b[14] => z[36]) = 0; + (b[15] => z[36]) = 0; + (b[16] => z[36]) = 0; + (b[17] => z[36]) = 0; + (a[0] => z[37]) = 0; + (a[1] => z[37]) = 0; + (a[2] => z[37]) = 0; + (a[3] => z[37]) = 0; + (a[4] => z[37]) = 0; + (a[5] => z[37]) = 0; + (a[6] => z[37]) = 0; + (a[7] => z[37]) = 0; + (a[8] => z[37]) = 0; + (a[9] => z[37]) = 0; + (a[10] => z[37]) = 0; + (a[11] => z[37]) = 0; + (a[12] => z[37]) = 0; + (a[13] => z[37]) = 0; + (a[14] => z[37]) = 0; + (a[15] => z[37]) = 0; + (a[16] => z[37]) = 0; + (a[17] => z[37]) = 0; + (a[18] => z[37]) = 0; + (a[19] => z[37]) = 0; + (b[0] => z[37]) = 0; + (b[1] => z[37]) = 0; + (b[2] => z[37]) = 0; + (b[3] => z[37]) = 0; + (b[4] => z[37]) = 0; + (b[5] => z[37]) = 0; + (b[6] => z[37]) = 0; + (b[7] => z[37]) = 0; + (b[8] => z[37]) = 0; + (b[9] => z[37]) = 0; + (b[10] => z[37]) = 0; + (b[11] => z[37]) = 0; + (b[12] => z[37]) = 0; + (b[13] => z[37]) = 0; + (b[14] => z[37]) = 0; + (b[15] => z[37]) = 0; + (b[16] => z[37]) = 0; + (b[17] => z[37]) = 0; + (subtract => z[0]) = 0; + (subtract => z[1]) = 0; + (subtract => z[2]) = 0; + (subtract => z[3]) = 0; + (subtract => z[4]) = 0; + (subtract => z[5]) = 0; + (subtract => z[6]) = 0; + (subtract => z[7]) = 0; + (subtract => z[8]) = 0; + (subtract => z[9]) = 0; + (subtract => z[10]) = 0; + (subtract => z[11]) = 0; + (subtract => z[12]) = 0; + (subtract => z[13]) = 0; + (subtract => z[14]) = 0; + (subtract => z[15]) = 0; + (subtract => z[16]) = 0; + (subtract => z[17]) = 0; + (subtract => z[18]) = 0; + (subtract => z[19]) = 0; + (subtract => z[20]) = 0; + (subtract => z[21]) = 0; + (subtract => z[22]) = 0; + (subtract => z[23]) = 0; + (subtract => z[24]) = 0; + (subtract => z[25]) = 0; + (subtract => z[26]) = 0; + (subtract => z[27]) = 0; + (subtract => z[28]) = 0; + (subtract => z[29]) = 0; + (subtract => z[30]) = 0; + (subtract => z[31]) = 0; + (subtract => z[32]) = 0; + (subtract => z[33]) = 0; + (subtract => z[34]) = 0; + (subtract => z[35]) = 0; + (subtract => z[36]) = 0; + (subtract => z[37]) = 0; + (acc_fir[0] => z[0]) = 0; + (acc_fir[1] => z[0]) = 0; + (acc_fir[2] => z[0]) = 0; + (acc_fir[3] => z[0]) = 0; + (acc_fir[4] => z[0]) = 0; + (acc_fir[5] => z[0]) = 0; + (acc_fir[0] => z[1]) = 0; + (acc_fir[1] => z[1]) = 0; + (acc_fir[2] => z[1]) = 0; + (acc_fir[3] => z[1]) = 0; + (acc_fir[4] => z[1]) = 0; + (acc_fir[5] => z[1]) = 0; + (acc_fir[0] => z[2]) = 0; + (acc_fir[1] => z[2]) = 0; + (acc_fir[2] => z[2]) = 0; + (acc_fir[3] => z[2]) = 0; + (acc_fir[4] => z[2]) = 0; + (acc_fir[5] => z[2]) = 0; + (acc_fir[0] => z[3]) = 0; + (acc_fir[1] => z[3]) = 0; + (acc_fir[2] => z[3]) = 0; + (acc_fir[3] => z[3]) = 0; + (acc_fir[4] => z[3]) = 0; + (acc_fir[5] => z[3]) = 0; + (acc_fir[0] => z[4]) = 0; + (acc_fir[1] => z[4]) = 0; + (acc_fir[2] => z[4]) = 0; + (acc_fir[3] => z[4]) = 0; + (acc_fir[4] => z[4]) = 0; + (acc_fir[5] => z[4]) = 0; + (acc_fir[0] => z[5]) = 0; + (acc_fir[1] => z[5]) = 0; + (acc_fir[2] => z[5]) = 0; + (acc_fir[3] => z[5]) = 0; + (acc_fir[4] => z[5]) = 0; + (acc_fir[5] => z[5]) = 0; + (acc_fir[0] => z[6]) = 0; + (acc_fir[1] => z[6]) = 0; + (acc_fir[2] => z[6]) = 0; + (acc_fir[3] => z[6]) = 0; + (acc_fir[4] => z[6]) = 0; + (acc_fir[5] => z[6]) = 0; + (acc_fir[0] => z[7]) = 0; + (acc_fir[1] => z[7]) = 0; + (acc_fir[2] => z[7]) = 0; + (acc_fir[3] => z[7]) = 0; + (acc_fir[4] => z[7]) = 0; + (acc_fir[5] => z[7]) = 0; + (acc_fir[0] => z[8]) = 0; + (acc_fir[1] => z[8]) = 0; + (acc_fir[2] => z[8]) = 0; + (acc_fir[3] => z[8]) = 0; + (acc_fir[4] => z[8]) = 0; + (acc_fir[5] => z[8]) = 0; + (acc_fir[0] => z[9]) = 0; + (acc_fir[1] => z[9]) = 0; + (acc_fir[2] => z[9]) = 0; + (acc_fir[3] => z[9]) = 0; + (acc_fir[4] => z[9]) = 0; + (acc_fir[5] => z[9]) = 0; + (acc_fir[0] => z[10]) = 0; + (acc_fir[1] => z[10]) = 0; + (acc_fir[2] => z[10]) = 0; + (acc_fir[3] => z[10]) = 0; + (acc_fir[4] => z[10]) = 0; + (acc_fir[5] => z[10]) = 0; + (acc_fir[0] => z[11]) = 0; + (acc_fir[1] => z[11]) = 0; + (acc_fir[2] => z[11]) = 0; + (acc_fir[3] => z[11]) = 0; + (acc_fir[4] => z[11]) = 0; + (acc_fir[5] => z[11]) = 0; + (acc_fir[0] => z[12]) = 0; + (acc_fir[1] => z[12]) = 0; + (acc_fir[2] => z[12]) = 0; + (acc_fir[3] => z[12]) = 0; + (acc_fir[4] => z[12]) = 0; + (acc_fir[5] => z[12]) = 0; + (acc_fir[0] => z[13]) = 0; + (acc_fir[1] => z[13]) = 0; + (acc_fir[2] => z[13]) = 0; + (acc_fir[3] => z[13]) = 0; + (acc_fir[4] => z[13]) = 0; + (acc_fir[5] => z[13]) = 0; + (acc_fir[0] => z[14]) = 0; + (acc_fir[1] => z[14]) = 0; + (acc_fir[2] => z[14]) = 0; + (acc_fir[3] => z[14]) = 0; + (acc_fir[4] => z[14]) = 0; + (acc_fir[5] => z[14]) = 0; + (acc_fir[0] => z[15]) = 0; + (acc_fir[1] => z[15]) = 0; + (acc_fir[2] => z[15]) = 0; + (acc_fir[3] => z[15]) = 0; + (acc_fir[4] => z[15]) = 0; + (acc_fir[5] => z[15]) = 0; + (acc_fir[0] => z[16]) = 0; + (acc_fir[1] => z[16]) = 0; + (acc_fir[2] => z[16]) = 0; + (acc_fir[3] => z[16]) = 0; + (acc_fir[4] => z[16]) = 0; + (acc_fir[5] => z[16]) = 0; + (acc_fir[0] => z[17]) = 0; + (acc_fir[1] => z[17]) = 0; + (acc_fir[2] => z[17]) = 0; + (acc_fir[3] => z[17]) = 0; + (acc_fir[4] => z[17]) = 0; + (acc_fir[5] => z[17]) = 0; + (acc_fir[0] => z[18]) = 0; + (acc_fir[1] => z[18]) = 0; + (acc_fir[2] => z[18]) = 0; + (acc_fir[3] => z[18]) = 0; + (acc_fir[4] => z[18]) = 0; + (acc_fir[5] => z[18]) = 0; + (acc_fir[0] => z[19]) = 0; + (acc_fir[1] => z[19]) = 0; + (acc_fir[2] => z[19]) = 0; + (acc_fir[3] => z[19]) = 0; + (acc_fir[4] => z[19]) = 0; + (acc_fir[5] => z[19]) = 0; + (acc_fir[0] => z[20]) = 0; + (acc_fir[1] => z[20]) = 0; + (acc_fir[2] => z[20]) = 0; + (acc_fir[3] => z[20]) = 0; + (acc_fir[4] => z[20]) = 0; + (acc_fir[5] => z[20]) = 0; + (acc_fir[0] => z[21]) = 0; + (acc_fir[1] => z[21]) = 0; + (acc_fir[2] => z[21]) = 0; + (acc_fir[3] => z[21]) = 0; + (acc_fir[4] => z[21]) = 0; + (acc_fir[5] => z[21]) = 0; + (acc_fir[0] => z[22]) = 0; + (acc_fir[1] => z[22]) = 0; + (acc_fir[2] => z[22]) = 0; + (acc_fir[3] => z[22]) = 0; + (acc_fir[4] => z[22]) = 0; + (acc_fir[5] => z[22]) = 0; + (acc_fir[0] => z[23]) = 0; + (acc_fir[1] => z[23]) = 0; + (acc_fir[2] => z[23]) = 0; + (acc_fir[3] => z[23]) = 0; + (acc_fir[4] => z[23]) = 0; + (acc_fir[5] => z[23]) = 0; + (acc_fir[0] => z[24]) = 0; + (acc_fir[1] => z[24]) = 0; + (acc_fir[2] => z[24]) = 0; + (acc_fir[3] => z[24]) = 0; + (acc_fir[4] => z[24]) = 0; + (acc_fir[5] => z[24]) = 0; + (acc_fir[0] => z[25]) = 0; + (acc_fir[1] => z[25]) = 0; + (acc_fir[2] => z[25]) = 0; + (acc_fir[3] => z[25]) = 0; + (acc_fir[4] => z[25]) = 0; + (acc_fir[5] => z[25]) = 0; + (acc_fir[0] => z[26]) = 0; + (acc_fir[1] => z[26]) = 0; + (acc_fir[2] => z[26]) = 0; + (acc_fir[3] => z[26]) = 0; + (acc_fir[4] => z[26]) = 0; + (acc_fir[5] => z[26]) = 0; + (acc_fir[0] => z[27]) = 0; + (acc_fir[1] => z[27]) = 0; + (acc_fir[2] => z[27]) = 0; + (acc_fir[3] => z[27]) = 0; + (acc_fir[4] => z[27]) = 0; + (acc_fir[5] => z[27]) = 0; + (acc_fir[0] => z[28]) = 0; + (acc_fir[1] => z[28]) = 0; + (acc_fir[2] => z[28]) = 0; + (acc_fir[3] => z[28]) = 0; + (acc_fir[4] => z[28]) = 0; + (acc_fir[5] => z[28]) = 0; + (acc_fir[0] => z[29]) = 0; + (acc_fir[1] => z[29]) = 0; + (acc_fir[2] => z[29]) = 0; + (acc_fir[3] => z[29]) = 0; + (acc_fir[4] => z[29]) = 0; + (acc_fir[5] => z[29]) = 0; + (acc_fir[0] => z[30]) = 0; + (acc_fir[1] => z[30]) = 0; + (acc_fir[2] => z[30]) = 0; + (acc_fir[3] => z[30]) = 0; + (acc_fir[4] => z[30]) = 0; + (acc_fir[5] => z[30]) = 0; + (acc_fir[0] => z[31]) = 0; + (acc_fir[1] => z[31]) = 0; + (acc_fir[2] => z[31]) = 0; + (acc_fir[3] => z[31]) = 0; + (acc_fir[4] => z[31]) = 0; + (acc_fir[5] => z[31]) = 0; + (acc_fir[0] => z[32]) = 0; + (acc_fir[1] => z[32]) = 0; + (acc_fir[2] => z[32]) = 0; + (acc_fir[3] => z[32]) = 0; + (acc_fir[4] => z[32]) = 0; + (acc_fir[5] => z[32]) = 0; + (acc_fir[0] => z[33]) = 0; + (acc_fir[1] => z[33]) = 0; + (acc_fir[2] => z[33]) = 0; + (acc_fir[3] => z[33]) = 0; + (acc_fir[4] => z[33]) = 0; + (acc_fir[5] => z[33]) = 0; + (acc_fir[0] => z[34]) = 0; + (acc_fir[1] => z[34]) = 0; + (acc_fir[2] => z[34]) = 0; + (acc_fir[3] => z[34]) = 0; + (acc_fir[4] => z[34]) = 0; + (acc_fir[5] => z[34]) = 0; + (acc_fir[0] => z[35]) = 0; + (acc_fir[1] => z[35]) = 0; + (acc_fir[2] => z[35]) = 0; + (acc_fir[3] => z[35]) = 0; + (acc_fir[4] => z[35]) = 0; + (acc_fir[5] => z[35]) = 0; + (acc_fir[0] => z[36]) = 0; + (acc_fir[1] => z[36]) = 0; + (acc_fir[2] => z[36]) = 0; + (acc_fir[3] => z[36]) = 0; + (acc_fir[4] => z[36]) = 0; + (acc_fir[5] => z[36]) = 0; + (acc_fir[0] => z[37]) = 0; + (acc_fir[1] => z[37]) = 0; + (acc_fir[2] => z[37]) = 0; + (acc_fir[3] => z[37]) = 0; + (acc_fir[4] => z[37]) = 0; + (acc_fir[5] => z[37]) = 0; + endspecify +`endif + endmodule module QL_DSP2_MULTADD_REGIN ( @@ -468,6 +3700,7 @@ module QL_DSP2_MULTADD_REGIN ( ) dsp ( .a(a), .b(b), + .dly_b(), .z(z), .f_mode(f_mode), @@ -489,6 +3722,20 @@ module QL_DSP2_MULTADD_REGIN ( .subtract(subtract), .register_inputs(register_inputs) // registered inputs ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + endmodule module QL_DSP2_MULTADD_REGOUT ( @@ -527,6 +3774,7 @@ module QL_DSP2_MULTADD_REGOUT ( ) dsp ( .a(a), .b(b), + .dly_b(), .z(z), .f_mode(f_mode), @@ -548,6 +3796,20 @@ module QL_DSP2_MULTADD_REGOUT ( .subtract(subtract), .register_inputs(register_inputs) // unregistered inputs ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + endmodule module QL_DSP2_MULTADD_REGIN_REGOUT ( @@ -586,6 +3848,7 @@ module QL_DSP2_MULTADD_REGIN_REGOUT ( ) dsp ( .a(a), .b(b), + .dly_b(), .z(z), .f_mode(f_mode), @@ -607,6 +3870,20 @@ module QL_DSP2_MULTADD_REGIN_REGOUT ( .subtract(subtract), .register_inputs(register_inputs) // registered inputs ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + endmodule module QL_DSP2_MULTACC ( @@ -644,7 +3921,9 @@ module QL_DSP2_MULTACC ( ) dsp ( .a(a), .b(b), + .acc_fir(6'b0), .z(z), + .dly_b(), .f_mode(f_mode), @@ -664,6 +3943,19 @@ module QL_DSP2_MULTACC ( .subtract(subtract), .register_inputs(register_inputs) // unregistered inputs ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + endmodule module QL_DSP2_MULTACC_REGIN ( @@ -701,7 +3993,9 @@ module QL_DSP2_MULTACC_REGIN ( ) dsp ( .a(a), .b(b), + .acc_fir(6'b0), .z(z), + .dly_b(), .f_mode(f_mode), @@ -721,6 +4015,19 @@ module QL_DSP2_MULTACC_REGIN ( .subtract(subtract), .register_inputs(register_inputs) // registered inputs ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + endmodule module QL_DSP2_MULTACC_REGOUT ( @@ -758,7 +4065,9 @@ module QL_DSP2_MULTACC_REGOUT ( ) dsp ( .a(a), .b(b), + .acc_fir(6'b0), .z(z), + .dly_b(), .f_mode(f_mode), @@ -778,6 +4087,19 @@ module QL_DSP2_MULTACC_REGOUT ( .subtract(subtract), .register_inputs(register_inputs) // unregistered inputs ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + endmodule module QL_DSP2_MULTACC_REGIN_REGOUT ( @@ -815,7 +4137,9 @@ module QL_DSP2_MULTACC_REGIN_REGOUT ( ) dsp ( .a(a), .b(b), + .acc_fir(6'b0), .z(z), + .dly_b(), .f_mode(f_mode), @@ -835,6 +4159,19 @@ module QL_DSP2_MULTACC_REGIN_REGOUT ( .subtract(subtract), .register_inputs(register_inputs) // registered inputs ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + endmodule module dsp_t1_20x18x64_cfg_ports ( @@ -994,10 +4331,7 @@ module dsp_t1_sim_cfg_ports # ( // FIXME: The version of Icarus Verilog from Conda seems not to recognize the // $error macro. Disable this sanity check for now because of that. -`ifndef __ICARUS__ - if (NBITS_ACC < NBITS_A + NBITS_B) - $error("NBITS_ACC must be > NBITS_A + NBITS_B"); -`endif + // Input registers reg [NBITS_A-1:0] r_a; @@ -2224,10 +5558,6 @@ module dsp_t1_sim_cfg_params # ( // FIXME: The version of Icarus Verilog from Conda seems not to recognize the // $error macro. Disable this sanity check for now because of that. -`ifndef __ICARUS__ - if (NBITS_ACC < NBITS_A + NBITS_B) - $error("NBITS_ACC must be > NBITS_A + NBITS_B"); -`endif // Input registers reg [NBITS_A-1:0] r_a; diff --git a/ql-qlf-plugin/qlf_k6n10f/primitives_sim.v b/ql-qlf-plugin/qlf_k6n10f/primitives_sim.v new file mode 100644 index 0000000..e8cc011 --- /dev/null +++ b/ql-qlf-plugin/qlf_k6n10f/primitives_sim.v @@ -0,0 +1,79 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`timescale 1ps/1ps + +`default_nettype none + +module fpga_interconnect(datain, dataout); + input wire datain; + output wire dataout; + + assign dataout = datain; + + specify + (datain => dataout) = 0; + endspecify + +endmodule + +module LUT_K #( + //The Look-up Table size (number of inputs) + // supports 1<=K<=6 + parameter K = 5, + + //The lut mask. + //Left-most (MSB) bit corresponds to all inputs logic one. + //Defaults to always false. + parameter LUT_MASK={2**K{1'b0}} +) ( + //input wire [K-1:0] in, + input wire [5:0] in, + output wire out +); + + wire [63:0] LUT_MASK_full; + assign LUT_MASK_full = (K == 6) ? LUT_MASK[63:0] : + (K == 5) ? {32'b0, LUT_MASK[31:0]} : + (K == 4) ? {48'b0, LUT_MASK[15:0]} : + (K == 3) ? {56'b0, LUT_MASK[7:0]} : + (K == 2) ? {60'b0, LUT_MASK[3:0]} : + {62'b0, LUT_MASK[1:0]} ; + + reg [5:0] in_full; + always @(*) + case(K) + 6: in_full <= in[5:0]; + 5: in_full <= {1'b0, in[4:0]}; + 4: in_full <= {2'b0, in[3:0]}; + 3: in_full <= {3'b0, in[2:0]}; + 2: in_full <= {4'b0, in[1:0]}; + 1: in_full <= {5'b0, in[0]}; + default: in_full <= in[5:0]; + endcase + + assign out = LUT_MASK_full[in_full]; + + specify + (in[0] => out) = 0; + (in[1] => out) = 0; + (in[2] => out) = 0; + (in[3] => out) = 0; + (in[4] => out) = 0; + (in[5] => out) = 0; + endspecify + +endmodule \ No newline at end of file diff --git a/ql-qlf-plugin/synth_quicklogic.cc b/ql-qlf-plugin/synth_quicklogic.cc index 2816daa..f861704 100644 --- a/ql-qlf-plugin/synth_quicklogic.cc +++ b/ql-qlf-plugin/synth_quicklogic.cc @@ -85,6 +85,9 @@ struct SynthQuickLogicPass : public ScriptPass { log(" By default use Block RAM in output netlist.\n"); log(" Specifying this switch turns it off.\n"); log("\n"); + log(" -bram_types\n"); + log(" Emit specialized BRAM cells for particular address and data width configurations \n"); + log("\n"); log(" -no_ff_map\n"); log(" By default ff techmap is turned on. Specifying this switch turns it off.\n"); log("\n"); @@ -103,6 +106,7 @@ struct SynthQuickLogicPass : public ScriptPass { bool nodsp; bool inferAdder; bool inferBram; + bool bramTypes; bool abcOpt; bool abc9; bool noffmap; @@ -118,6 +122,7 @@ struct SynthQuickLogicPass : public ScriptPass { family = "qlf_k4n8"; inferAdder = true; inferBram = true; + bramTypes = false; abcOpt = true; abc9 = true; noffmap = false; @@ -181,6 +186,10 @@ struct SynthQuickLogicPass : public ScriptPass { inferBram = false; continue; } + if (args[argidx] == "-bram_types") { + bramTypes = true; + continue; + } if (args[argidx] == "-no_abc_opt") { abcOpt = false; continue; @@ -237,8 +246,10 @@ struct SynthQuickLogicPass : public ScriptPass { // Read simulation library readVelArgs = family_path + "/cells_sim.v"; - if (family == "qlf_k6n10f") + if (family == "qlf_k6n10f") { readVelArgs += family_path + "/dsp_sim.v"; + readVelArgs += family_path + "/brams_sim.v"; + } // Use -nomem2reg here to prevent Yosys from complaining about // some block ram cell models. After all the only part of the cells @@ -368,6 +379,32 @@ struct SynthQuickLogicPass : public ScriptPass { if (family == "qlf_k6n10f") { run("techmap -map +/quicklogic/" + family + "/brams_final_map.v"); } + + // Data width to specialized cell type width map + const std::unordered_map dataWidth36 = {{36, 36}, {32, 36}, {18, 18}, {16, 18}, {9, 9}, {8, 9}, {4, 4}, {2, 2}, {1, 1}}; + const std::unordered_map dataWidth18 = {{18, 18}, {16, 18}, {9, 9}, {8, 9}, {4, 4}, {2, 2}, {1, 1}}; + + // Perform a series of 'chtype' passess + if (bramTypes) { + for (const auto &ww : dataWidth18) { + for (const auto &rw : dataWidth18) { + auto cmd = + stringf("chtype -set TDP36K_BRAM_WR_X%d_RD_X%d_split t:TDP36K a:is_inferred=1 %%i a:is_split=1 %%i a:wr_data_width=%d " + "%%i a:rd_data_width=%d %%i", + ww.second, rw.second, ww.first, rw.first); + run(cmd); + } + } + + for (const auto &ww : dataWidth36) { + for (const auto &rw : dataWidth36) { + auto cmd = stringf( + "chtype -set TDP36K_BRAM_WR_X%d_RD_X%d_nonsplit t:TDP36K a:is_inferred=1 %%i a:wr_data_width=%d %%i a:rd_data_width=%d %%i", + ww.second, rw.second, ww.first, rw.first); + run(cmd); + } + } + } } if (check_label("map_ffram")) { diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl index b413b43..1ae531a 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl @@ -8,46 +8,46 @@ design -save bram_tdp select spram_16x2048_32x1024 select * -synth_quicklogic -family qlf_k6n10f -top spram_16x2048_32x1024 +synth_quicklogic -family qlf_k6n10f -top spram_16x2048_32x1024 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/spram_16x2048_32x1024_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X36_nonsplit select -assert-count 1 t:* select -clear design -load bram_tdp select spram_8x4096_16x2048 select * -synth_quicklogic -family qlf_k6n10f -top spram_8x4096_16x2048 +synth_quicklogic -family qlf_k6n10f -top spram_8x4096_16x2048 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/spram_8x4096_16x2048_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X18_nonsplit select -assert-count 1 t:* select -clear design -load bram_tdp select spram_8x2048_16x1024 select * -synth_quicklogic -family qlf_k6n10f -top spram_8x2048_16x1024 +synth_quicklogic -family qlf_k6n10f -top spram_8x2048_16x1024 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/spram_8x2048_16x1024_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X18_nonsplit select -assert-count 1 t:* select -clear design -load bram_tdp select spram_8x4096_32x1024 select * -synth_quicklogic -family qlf_k6n10f -top spram_8x4096_32x1024 +synth_quicklogic -family qlf_k6n10f -top spram_8x4096_32x1024 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/spram_8x4096_32x1024_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X36_nonsplit select -assert-count 1 t:* diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.tcl index 9d086bb..254c2ea 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.tcl @@ -8,46 +8,46 @@ design -save bram_tdp select spram_16x1024_8x2048 select * -synth_quicklogic -family qlf_k6n10f -top spram_16x1024_8x2048 +synth_quicklogic -family qlf_k6n10f -top spram_16x1024_8x2048 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/spram_16x1024_8x2048_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X9_nonsplit select -assert-count 1 t:* select -clear design -load bram_tdp select spram_16x2048_8x4096 select * -synth_quicklogic -family qlf_k6n10f -top spram_16x2048_8x4096 +synth_quicklogic -family qlf_k6n10f -top spram_16x2048_8x4096 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/spram_16x2048_8x4096_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X9_nonsplit select -assert-count 1 t:* select -clear design -load bram_tdp select spram_32x1024_16x2048 select * -synth_quicklogic -family qlf_k6n10f -top spram_32x1024_16x2048 +synth_quicklogic -family qlf_k6n10f -top spram_32x1024_16x2048 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/spram_32x1024_16x2048_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X18_nonsplit select -assert-count 1 t:* select -clear design -load bram_tdp select spram_32x1024_8x4096 select * -synth_quicklogic -family qlf_k6n10f -top spram_32x1024_8x4096 +synth_quicklogic -family qlf_k6n10f -top spram_32x1024_8x4096 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/spram_32x1024_8x4096_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X9_nonsplit select -assert-count 1 t:* diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl index f8567ce..4e98585 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl @@ -8,98 +8,98 @@ design -save bram_sdp select BRAM_SDP_36x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_36x1024 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_36x1024 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_36x1024_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X36_nonsplit select -clear design -load bram_sdp select BRAM_SDP_32x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_32x1024 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_32x1024 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_32x1024_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X36_nonsplit select -clear design -load bram_sdp select BRAM_SDP_18x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_18x2048 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_18x2048 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_18x2048_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_nonsplit select -clear design -load bram_sdp select BRAM_SDP_16x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_16x2048 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_16x2048 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_16x2048_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_nonsplit select -clear design -load bram_sdp select BRAM_SDP_9x4096 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_9x4096 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_9x4096 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_9x4096_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_nonsplit select -clear design -load bram_sdp select BRAM_SDP_8x4096 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_8x4096 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_8x4096 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_8x4096_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_nonsplit select -clear design -load bram_sdp select BRAM_SDP_4x8192 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_4x8192 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_4x8192 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_4x8192_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X4_RD_X4_nonsplit select -clear design -load bram_sdp select BRAM_SDP_2x16384 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_2x16384 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_2x16384 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_2x16384_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X2_RD_X2_nonsplit select -clear design -load bram_sdp select BRAM_SDP_1x32768 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_1x32768 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_1x32768 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_1x32768_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X1_RD_X1_nonsplit diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp_split/bram_sdp_split.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp_split/bram_sdp_split.tcl index a296d8c..fcf9acd 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp_split/bram_sdp_split.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp_split/bram_sdp_split.tcl @@ -8,76 +8,76 @@ design -save bram_sdp_split select BRAM_SDP_SPLIT_2x18x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x18x1024 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x18x1024 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_split_2x18x1024_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_split select -clear design -load bram_sdp_split select BRAM_SDP_SPLIT_2x16x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x16x1024 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x16x1024 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_split_2x16x1024_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_split select -clear design -load bram_sdp_split select BRAM_SDP_SPLIT_2x9x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x9x2048 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x9x2048 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_split_2x9x2048_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_split select -clear design -load bram_sdp_split select BRAM_SDP_SPLIT_2x8x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x8x2048 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x8x2048 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_split_2x8x2048_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_split select -clear design -load bram_sdp_split select BRAM_SDP_SPLIT_2x4x4096 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x4x4096 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x4x4096 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_split_2x4x4096_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X4_RD_X4_split select -clear design -load bram_sdp_split select BRAM_SDP_SPLIT_2x2x8192 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x2x8192 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x2x8192 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_split_2x2x8192_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X2_RD_X2_split select -clear design -load bram_sdp_split select BRAM_SDP_SPLIT_2x1x16384 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x1x16384 +synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x1x16384 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_sdp_split_2x1x16384_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X1_RD_X1_split diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl index 8ef0e9d..ea5ae8e 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl @@ -8,98 +8,98 @@ design -save bram_tdp select BRAM_TDP_36x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_36x1024 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_36x1024 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_36x1024_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X36_nonsplit select -clear design -load bram_tdp select BRAM_TDP_32x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_32x1024 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_32x1024 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_32x1024_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X36_RD_X36_nonsplit select -clear design -load bram_tdp select BRAM_TDP_18x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_18x2048 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_18x2048 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_18x2048_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_nonsplit select -clear design -load bram_tdp select BRAM_TDP_16x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_16x2048 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_16x2048 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_16x2048_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_nonsplit select -clear design -load bram_tdp select BRAM_TDP_9x4096 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_9x4096 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_9x4096 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_9x4096_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_nonsplit select -clear design -load bram_tdp select BRAM_TDP_8x4096 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_8x4096 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_8x4096 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_8x4096_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_nonsplit select -clear design -load bram_tdp select BRAM_TDP_4x8192 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_4x8192 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_4x8192 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_4x8192_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X4_RD_X4_nonsplit select -clear design -load bram_tdp select BRAM_TDP_2x16384 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_2x16384 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_2x16384 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_2x16384_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X2_RD_X2_nonsplit select -clear design -load bram_tdp select BRAM_TDP_1x32768 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_1x32768 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_1x32768 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_1x32768_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X1_RD_X1_nonsplit diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp_split/bram_tdp_split.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp_split/bram_tdp_split.tcl index 9a8921e..7b56e8d 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp_split/bram_tdp_split.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp_split/bram_tdp_split.tcl @@ -8,76 +8,76 @@ design -save bram_tdp_split select BRAM_TDP_SPLIT_2x18x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x18x1024 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x18x1024 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_split_2x18x1024_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_split select -clear design -load bram_tdp_split select BRAM_TDP_SPLIT_2x16x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x16x1024 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x16x1024 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_split_2x16x1024_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X18_RD_X18_split select -clear design -load bram_tdp_split select BRAM_TDP_SPLIT_2x9x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x9x2048 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x9x2048 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_split_2x9x2048_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_split select -clear design -load bram_tdp_split select BRAM_TDP_SPLIT_2x8x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x8x2048 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x8x2048 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_split_2x8x2048_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X9_RD_X9_split select -clear design -load bram_tdp_split select BRAM_TDP_SPLIT_2x4x4096 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x4x4096 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x4x4096 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_split_2x4x4096_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X4_RD_X4_split select -clear design -load bram_tdp_split select BRAM_TDP_SPLIT_2x2x8192 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x2x8192 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x2x8192 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_split_2x2x8192_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X2_RD_X2_split select -clear design -load bram_tdp_split select BRAM_TDP_SPLIT_2x1x16384 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x1x16384 +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x1x16384 -bram_types opt_expr -undriven opt_clean stat write_verilog sim/bram_tdp_split_2x1x16384_post_synth.v -select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K_BRAM_WR_X1_RD_X1_split diff --git a/sdc-plugin/Makefile b/sdc-plugin/Makefile index 3ae63e0..871c9bc 100644 --- a/sdc-plugin/Makefile +++ b/sdc-plugin/Makefile @@ -14,6 +14,8 @@ # # SPDX-License-Identifier: Apache-2.0 +PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + NAME = sdc SOURCES = buffers.cc \ clocks.cc \ diff --git a/systemverilog-plugin/Makefile b/systemverilog-plugin/Makefile index 1b162be..a1d69e1 100644 --- a/systemverilog-plugin/Makefile +++ b/systemverilog-plugin/Makefile @@ -14,24 +14,44 @@ # # SPDX-License-Identifier: Apache-2.0 +PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + NAME = systemverilog SOURCES = UhdmAst.cc \ - uhdmastfrontend.cc \ - uhdmcommonfrontend.cc \ - uhdmsurelogastfrontend.cc \ - uhdmastreport.cc + UhdmAstUpstream.cc \ + uhdmastfrontend.cc \ + uhdmcommonfrontend.cc \ + uhdmsurelogastfrontend.cc \ + uhdmastreport.cc # Directory to search for Surelog and UHDM libraries UHDM_INSTALL_DIR ?= /usr/local include ../Makefile_plugin.common -CPPFLAGS += -std=c++17 -Wall -W -Wextra \ - -Wno-deprecated-declarations \ - -Wno-unused-parameter \ - -I${UHDM_INSTALL_DIR}/include \ - -I${UHDM_INSTALL_DIR}/include/Surelog +CXXFLAGS += -std=c++17 -Wall -W -Wextra \ + -Wno-deprecated-declarations \ + -Wno-unused-parameter \ + -I${UHDM_INSTALL_DIR}/include \ + -I${UHDM_INSTALL_DIR}/include/Surelog + +LDFLAGS += -L${UHDM_INSTALL_DIR}/lib/uhdm \ + -L${UHDM_INSTALL_DIR}/lib/surelog \ + -L${UHDM_INSTALL_DIR}/lib \ + -L${UHDM_INSTALL_DIR}/lib64/uhdm \ + -L${UHDM_INSTALL_DIR}/lib64/surelog \ + -L${UHDM_INSTALL_DIR}/lib64 -CXXFLAGS += -Wno-unused-parameter -LDFLAGS += -L${UHDM_INSTALL_DIR}/lib/uhdm -L${UHDM_INSTALL_DIR}/lib/surelog -L${UHDM_INSTALL_DIR}/lib -L${UHDM_INSTALL_DIR}/lib64/uhdm -L${UHDM_INSTALL_DIR}/lib64/surelog -L${UHDM_INSTALL_DIR}/lib64 -LDLIBS += -Wl,--whole-archive -luhdm -Wl,--no-whole-archive -lsurelog -lantlr4-runtime -lflatbuffers -lcapnp -lkj -ldl -lutil -lm -lrt -lpthread +LDLIBS += -Wl,--whole-archive \ + -luhdm \ + -Wl,--no-whole-archive \ + -lsurelog \ + -lantlr4-runtime \ + -lflatbuffers \ + -lcapnp \ + -lkj \ + -ldl \ + -lutil \ + -lm \ + -lrt \ + -lpthread diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc index 73902f1..6b3624a 100644 --- a/systemverilog-plugin/UhdmAst.cc +++ b/systemverilog-plugin/UhdmAst.cc @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include @@ -13,6 +14,8 @@ #include #include +#include "UhdmAstUpstream.h" + YOSYS_NAMESPACE_BEGIN /*static*/ const IdString &UhdmAst::partial() @@ -124,8 +127,6 @@ static void copy_packed_unpacked_attribute(AST::AstNode *from, AST::AstNode *to) } } -#include "UhdmAstUpstream.cc" - static int get_max_offset_struct(AST::AstNode *node) { // get the width from the MS member in the struct @@ -1070,33 +1071,54 @@ AST::AstNode *UhdmAst::process_value(vpiHandle obj_h) { s_vpi_value val; vpi_get_value(obj_h, &val); - std::string strValType; + std::string strValType = "'"; + bool is_signed = false; + if (vpiHandle typespec_h = vpi_handle(vpiTypespec, obj_h)) { + is_signed = vpi_get(vpiSigned, typespec_h); + if (is_signed) { + strValType += "s"; + } + } if (val.format) { // Needed to handle parameter nodes without typespecs and constants switch (val.format) { case vpiScalarVal: return AST::AstNode::mkconst_int(val.value.scalar, false, 1); case vpiBinStrVal: { - strValType = "'b"; + strValType += "b"; break; } case vpiDecStrVal: { - strValType = "'d"; + strValType += "d"; break; } case vpiHexStrVal: { - strValType = "'h"; + strValType += "h"; break; } case vpiOctStrVal: { - strValType = "'o"; + strValType += "o"; break; } // Surelog reports constant integers as a unsigned, but by default int is signed // so we are treating here UInt in the same way as if they would be Int case vpiUIntVal: + if (val.value.uint > std::numeric_limits::max()) { + // an integer is by default signed, so use 'sd despite the variant vpiUIntVal + strValType = "'sd"; + string str_value = std::to_string(val.value.uint); + val.value.str = strdup(str_value.c_str()); + break; + } + [[fallthrough]]; case vpiIntVal: { + if (val.value.integer > std::numeric_limits::max()) { + strValType = "'sd"; + string str_value = std::to_string(val.value.integer); + val.value.str = strdup(str_value.c_str()); + break; + } + int size = -1; - bool is_signed = false; // Surelog sometimes report size as part of vpiTypespec (e.g. int_typespec) // if it is the case, we need to set size to the left_range of first packed range visit_one_to_one({vpiTypespec}, obj_h, [&](AST::AstNode *node) { @@ -1116,7 +1138,7 @@ AST::AstNode *UhdmAst::process_value(vpiHandle obj_h) size = 32; is_signed = true; } - auto c = AST::AstNode::mkconst_int(val.value.integer, is_signed, size > 0 ? size : 32); + auto c = AST::AstNode::mkconst_int(val.format == vpiUIntVal ? val.value.uint : val.value.integer, is_signed, size > 0 ? size : 32); if (size == 0 || size == -1) c->is_unsized = true; return c; @@ -1277,8 +1299,21 @@ AST::AstNode *UhdmAst::make_ast_node(AST::AstNodeType type, std::vectorfilename = filename; } - if (unsigned int line = vpi_get(vpiLineNo, obj_h)) { - node->location.first_line = node->location.last_line = line; + if (unsigned int first_line = vpi_get(vpiLineNo, obj_h)) { + node->location.first_line = first_line; + } + if (unsigned int last_line = vpi_get(vpiEndLineNo, obj_h)) { + node->location.last_line = last_line; + } else { + node->location.last_line = node->location.first_line; + } + if (unsigned int first_col = vpi_get(vpiColumnNo, obj_h)) { + node->location.first_column = first_col; + } + if (unsigned int last_col = vpi_get(vpiEndColumnNo, obj_h)) { + node->location.last_column = last_col; + } else { + node->location.last_column = node->location.first_column; } node->children = children; return node; @@ -1515,12 +1550,13 @@ AST::AstNode *UhdmAst::find_ancestor(const std::unordered_set void UhdmAst::process_design() { current_node = make_ast_node(AST::AST_DESIGN); - visit_one_to_many({UHDM::uhdmallInterfaces, UHDM::uhdmallPackages, UHDM::uhdmtopPackages, UHDM::uhdmallModules, UHDM::uhdmtopModules}, obj_h, - [&](AST::AstNode *node) { - if (node) { - shared.top_nodes[node->str] = node; - } - }); + visit_one_to_many( + {UHDM::uhdmallInterfaces, UHDM::uhdmallPackages, UHDM::uhdmtopPackages, UHDM::uhdmallModules, UHDM::uhdmtopModules, vpiTaskFunc}, obj_h, + [&](AST::AstNode *node) { + if (node) { + shared.top_nodes[node->str] = node; + } + }); visit_one_to_many({vpiParameter, vpiParamAssign}, obj_h, [&](AST::AstNode *node) {}); visit_one_to_many({vpiTypedef}, obj_h, [&](AST::AstNode *node) { if (node) @@ -1558,6 +1594,13 @@ void UhdmAst::process_design() pair.second = nullptr; } } + if (!shared.debug_flag) { + // Ranges were already converted, erase obsolete attributes + visitEachDescendant(current_node, [&](AST::AstNode *node) { + node->attributes.erase(UhdmAst::packed_ranges()); + node->attributes.erase(UhdmAst::unpacked_ranges()); + }); + } } void UhdmAst::simplify_parameter(AST::AstNode *parameter, AST::AstNode *module_node) @@ -1566,8 +1609,6 @@ void UhdmAst::simplify_parameter(AST::AstNode *parameter, AST::AstNode *module_n visitEachDescendant(shared.current_top_node, [&](AST::AstNode *current_scope_node) { if (current_scope_node->type == AST::AST_TYPEDEF || current_scope_node->type == AST::AST_PARAMETER || current_scope_node->type == AST::AST_LOCALPARAM) { - if (current_scope_node->type == AST::AST_TYPEDEF) - simplify(current_scope_node, nullptr); AST_INTERNAL::current_scope[current_scope_node->str] = current_scope_node; } }); @@ -1851,27 +1892,27 @@ void UhdmAst::process_typespec_member() break; } case vpiByteTypespec: { - current_node->is_signed = true; + current_node->is_signed = vpi_get(vpiSigned, typespec_h); packed_ranges.push_back(make_range(7, 0)); shared.report.mark_handled(typespec_h); break; } case vpiShortIntTypespec: { - current_node->is_signed = true; + current_node->is_signed = vpi_get(vpiSigned, typespec_h); packed_ranges.push_back(make_range(15, 0)); shared.report.mark_handled(typespec_h); break; } case vpiIntTypespec: case vpiIntegerTypespec: { - current_node->is_signed = true; + current_node->is_signed = vpi_get(vpiSigned, typespec_h); packed_ranges.push_back(make_range(31, 0)); shared.report.mark_handled(typespec_h); break; } case vpiTimeTypespec: case vpiLongIntTypespec: { - current_node->is_signed = true; + current_node->is_signed = vpi_get(vpiSigned, typespec_h); packed_ranges.push_back(make_range(63, 0)); shared.report.mark_handled(typespec_h); break; @@ -1957,42 +1998,67 @@ void UhdmAst::process_typespec_member() void UhdmAst::process_enum_typespec() { + // BaseTypespec specifies underlying type of the enum. + // The BaseTypespec has at most one explicit packed dimension (range). + // When base type is not specified in SystemVerilog code, it is assumed to be an int. + // Type of enum items (constants) is the same as the enum type. current_node = make_ast_node(AST::AST_ENUM); + bool has_base_type = false; + visit_one_to_one({vpiBaseTypespec}, obj_h, [&](AST::AstNode *node) { + has_base_type = true; + current_node->children = std::move(node->children); + current_node->attributes = std::move(node->attributes); + current_node->is_signed = node->is_signed; + current_node->is_logic = node->is_logic; + delete node; + }); + if (!has_base_type) { + // Base typespec is `int` by default + // TODO (mglb): This is almost the same code as in `process_int_typespec()`. Put common code in dedicated function. + std::vector packed_ranges; + packed_ranges.push_back(make_range(31, 0)); + add_multirange_wire(current_node, std::move(packed_ranges), {}); + current_node->is_signed = true; + } + // We have to restore node's range_* properties if there's no range. + const auto range_left = current_node->range_left; + const auto range_right = current_node->range_right; + const auto range_valid = current_node->range_valid; + // Create a range from the typespec just for the purpose of copying it to consts. + convert_packed_unpacked_range(current_node); + const auto range_it = std::find_if(current_node->children.cbegin(), current_node->children.cend(), + [](const AST::AstNode *n) { return n->type == AST::AST_RANGE || n->type == AST::AST_MULTIRANGE; }); + const auto *const range = range_it != current_node->children.cend() ? *range_it : nullptr; + if (range) { + current_node->children.erase(range_it); + } else { + current_node->range_left = range_left; + current_node->range_right = range_right; + current_node->range_valid = range_valid; + } + visit_one_to_one({vpiTypedefAlias}, obj_h, [&](AST::AstNode *node) { if (node) { - current_node->attributes["\\enum_base_type"] = node->clone(); + current_node->attributes["\\enum_base_type"] = node; } }); - visit_one_to_many({vpiEnumConst}, obj_h, [&](AST::AstNode *node) { current_node->children.push_back(node); }); - vpiHandle typespec_h = vpi_handle(vpiBaseTypespec, obj_h); - if (typespec_h) { - int typespec_type = vpi_get(vpiType, typespec_h); - switch (typespec_type) { - case vpiLogicTypespec: { - current_node->is_logic = true; - shared.report.mark_handled(typespec_h); - break; - } - case vpiByteTypespec: - case vpiIntTypespec: - case vpiIntegerTypespec: { - current_node->is_signed = true; - shared.report.mark_handled(typespec_h); - break; - } - case vpiBitTypespec: { - shared.report.mark_handled(typespec_h); - break; - } - default: { - const uhdm_handle *const handle = (const uhdm_handle *)typespec_h; - const UHDM::BaseClass *const object = (const UHDM::BaseClass *)handle->object; - report_error("%s:%d: Encountered unhandled typespec in process_enum_typespec: '%s' of type '%s'\n", object->VpiFile().c_str(), - object->VpiLineNo(), object->VpiName().c_str(), UHDM::VpiTypeName(typespec_h).c_str()); - break; - } + visit_one_to_many({vpiEnumConst}, obj_h, [&](AST::AstNode *node) { + // Enum const must have the same type and ranges as the enum. + node->is_logic = current_node->is_logic; + node->is_signed = current_node->is_signed; + if (range) { + node->children.push_back(range->clone()); + node->range_valid = true; + } else { + node->range_left = range_left; + node->range_right = range_right; + node->range_valid = range_valid; } - vpi_release_handle(typespec_h); + // IMPORTANT: invalidates `range_it`! + current_node->children.push_back(node); + }); + if (range) { + delete range; } } @@ -2004,7 +2070,6 @@ void UhdmAst::process_enum_const() constant_node->filename = current_node->filename; constant_node->location = current_node->location; current_node->children.push_back(constant_node); - current_node->children.push_back(make_range(constant_node->range_left, constant_node->range_right, true)); } } @@ -2038,7 +2103,7 @@ void UhdmAst::process_int_var() auto right_const = AST::AstNode::mkconst_int(0, true); auto range = new AST::AstNode(AST::AST_RANGE, left_const, right_const); current_node->children.push_back(range); - current_node->is_signed = true; + current_node->is_signed = vpi_get(vpiSigned, obj_h); visit_default_expr(obj_h); } @@ -2519,6 +2584,7 @@ void UhdmAst::process_io_decl() current_node->is_logic = node->is_logic; current_node->is_reg = node->is_reg; } + current_node->is_signed = node->is_signed; delete node; } }); @@ -3226,14 +3292,13 @@ void UhdmAst::process_for() current_node->str = "$fordecl_block" + std::to_string(loop_id); auto loop = make_ast_node(AST::AST_FOR); loop->str = "$loop" + std::to_string(loop_id); - current_node->children.push_back(loop); visit_one_to_many({vpiForInitStmt}, obj_h, [&](AST::AstNode *node) { if (node->type == AST::AST_ASSIGN_LE) node->type = AST::AST_ASSIGN_EQ; auto lhs = node->children[0]; if (lhs->type == AST::AST_WIRE) { auto *wire = lhs->clone(); - wire->is_reg = true; + wire->is_logic = true; current_node->children.push_back(wire); lhs->type = AST::AST_IDENTIFIER; lhs->is_signed = false; @@ -3260,6 +3325,7 @@ void UhdmAst::process_for() loop->children.push_back(node); } }); + current_node->children.push_back(loop); transform_breaks_continues(loop, current_node); } @@ -3519,6 +3585,7 @@ void UhdmAst::process_logic_var() current_node->children.push_back(wiretype_node); current_node->is_custom_type = true; } + current_node->is_signed = node->is_signed; delete node; }); // TODO: Handling below seems similar to other typespec accesses for range. Candidate for extraction to a function. @@ -3566,9 +3633,9 @@ void UhdmAst::process_sys_func_call() current_node->str = current_node->str.substr(1); } -void UhdmAst::process_func_call() +void UhdmAst::process_tf_call(AST::AstNodeType type) { - current_node = make_ast_node(AST::AST_FCALL); + current_node = make_ast_node(type); visit_one_to_many({vpiArgument}, obj_h, [&](AST::AstNode *node) { if (node) { if (node->type == AST::AST_PARAMETER || node->type == AST::AST_LOCALPARAM) { @@ -3834,6 +3901,8 @@ void UhdmAst::process_port() case vpiStructVar: case vpiUnionVar: case vpiEnumVar: + case vpiBitVar: + case vpiByteVar: case vpiShortIntVar: case vpiLongIntVar: case vpiIntVar: @@ -3943,7 +4012,10 @@ void UhdmAst::process_parameter() } case vpiIntTypespec: case vpiIntegerTypespec: { - packed_ranges.push_back(make_range(31, 0)); + visit_one_to_many({vpiRange}, typespec_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); }); + if (packed_ranges.empty()) { + packed_ranges.push_back(make_range(31, 0)); + } shared.report.mark_handled(typespec_h); break; } @@ -4306,10 +4378,10 @@ AST::AstNode *UhdmAst::process_object(vpiHandle obj_handle) process_sys_func_call(); break; case vpiFuncCall: - process_func_call(); + process_tf_call(AST::AST_FCALL); break; case vpiTaskCall: - current_node = make_ast_node(AST::AST_TCALL); + process_tf_call(AST::AST_TCALL); break; case vpiImmediateAssert: if (!shared.no_assert) diff --git a/systemverilog-plugin/UhdmAst.h b/systemverilog-plugin/UhdmAst.h index 0d41f14..1e77c17 100644 --- a/systemverilog-plugin/UhdmAst.h +++ b/systemverilog-plugin/UhdmAst.h @@ -127,7 +127,8 @@ class UhdmAst void process_function(); void process_logic_var(); void process_sys_func_call(); - void process_func_call(); + // use for task calls and function calls + void process_tf_call(AST::AstNodeType type); void process_immediate_assert(); void process_hier_path(); void process_logic_typespec(); diff --git a/systemverilog-plugin/UhdmAstUpstream.cc b/systemverilog-plugin/UhdmAstUpstream.cc index 921acf1..79da255 100644 --- a/systemverilog-plugin/UhdmAstUpstream.cc +++ b/systemverilog-plugin/UhdmAstUpstream.cc @@ -1,21 +1,24 @@ -namespace AST -{ -enum AstNodeTypeExtended { - AST_DOT = AST::AST_BIND + 1, // here we always want to point to the last element of yosys' AstNodeType - AST_BREAK, - AST_CONTINUE -}; -} +#include +#include +#include + +#include "UhdmAstUpstream.h" +#include "frontends/ast/ast.h" + +YOSYS_NAMESPACE_BEGIN -static AST::AstNode *mkconst_real(double d) +AST::AstNode *mkconst_real(double d) { AST::AstNode *node = new AST::AstNode(AST::AST_REALVALUE); node->realvalue = d; return node; } + namespace VERILOG_FRONTEND { + using namespace AST; + // divide an arbitrary length decimal number by two and return the rest static int my_decimal_div_by_two(std::vector &digits) { @@ -120,7 +123,7 @@ static void my_strtobin(std::vector &data, const char *str, int le } // convert the Verilog code for a constant to an AST node -static AST::AstNode *const2ast(std::string code, char case_type, bool warn_z) +AST::AstNode *const2ast(std::string code, char case_type, bool warn_z) { if (warn_z) { AST::AstNode *ret = const2ast(code, case_type, false); @@ -214,3 +217,5 @@ static AST::AstNode *const2ast(std::string code, char case_type, bool warn_z) return NULL; } } // namespace VERILOG_FRONTEND + +YOSYS_NAMESPACE_END diff --git a/systemverilog-plugin/UhdmAstUpstream.h b/systemverilog-plugin/UhdmAstUpstream.h new file mode 100644 index 0000000..5fe8f14 --- /dev/null +++ b/systemverilog-plugin/UhdmAstUpstream.h @@ -0,0 +1,33 @@ +#ifndef YOSYS_SYSTEMVERILOG_PLUGIN_UHDM_AST_UPSTREAM_H_ +#define YOSYS_SYSTEMVERILOG_PLUGIN_UHDM_AST_UPSTREAM_H_ + +#include +#include +#include + +#include "frontends/ast/ast.h" + +YOSYS_NAMESPACE_BEGIN + +namespace AST +{ +enum AstNodeTypeExtended { + AST_DOT = AST::AST_BIND + 1, // here we always want to point to the last element of yosys' AstNodeType + AST_BREAK, + AST_CONTINUE +}; +} + +AST::AstNode *mkconst_real(double d); + +namespace VERILOG_FRONTEND +{ + +// convert the Verilog code for a constant to an AST node +AST::AstNode *const2ast(std::string code, char case_type, bool warn_z); + +} // namespace VERILOG_FRONTEND + +YOSYS_NAMESPACE_END + +#endif // YOSYS_SYSTEMVERILOG_PLUGIN_UHDM_AST_UPSTREAM_H_ diff --git a/systemverilog-plugin/tests/Makefile b/systemverilog-plugin/tests/Makefile index e078fa7..1843a05 100644 --- a/systemverilog-plugin/tests/Makefile +++ b/systemverilog-plugin/tests/Makefile @@ -16,10 +16,14 @@ TESTS = counter \ break_continue \ - separate-compilation + separate-compilation \ + debug-flag \ + report-flag include $(shell pwd)/../../Makefile_test.common counter_verify = true break_continue_verify = $(call diff_test,break_continue,out) separate-compilation_verify = true +debug-flag_verify = true +report-flag_verify = true diff --git a/systemverilog-plugin/tests/debug-flag/debug-flag-buf.sv b/systemverilog-plugin/tests/debug-flag/debug-flag-buf.sv new file mode 100644 index 0000000..565946b --- /dev/null +++ b/systemverilog-plugin/tests/debug-flag/debug-flag-buf.sv @@ -0,0 +1,21 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +module BUF ( + input I, + output O +); + assign O = I; +endmodule; diff --git a/systemverilog-plugin/tests/debug-flag/debug-flag-pkg.sv b/systemverilog-plugin/tests/debug-flag/debug-flag-pkg.sv new file mode 100644 index 0000000..b0362fc --- /dev/null +++ b/systemverilog-plugin/tests/debug-flag/debug-flag-pkg.sv @@ -0,0 +1,19 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +package pkg; + parameter BITS = 4; + parameter LOG2DELAY = 22; +endpackage diff --git a/systemverilog-plugin/tests/debug-flag/debug-flag.tcl b/systemverilog-plugin/tests/debug-flag/debug-flag.tcl new file mode 100644 index 0000000..86cfee5 --- /dev/null +++ b/systemverilog-plugin/tests/debug-flag/debug-flag.tcl @@ -0,0 +1,16 @@ +yosys -import +if { [info procs read_uhdm] == {} } { plugin -i systemverilog } +yosys -import ;# ingest plugin commands + +set TMP_DIR /tmp +if { [info exists ::env(TMPDIR) ] } { + set TMP_DIR $::env(TMPDIR) +} + +# Testing simple round-trip +read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP)-pkg.sv +read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP)-buf.sv +read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP).v +read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -link +hierarchy +write_verilog diff --git a/systemverilog-plugin/tests/debug-flag/debug-flag.v b/systemverilog-plugin/tests/debug-flag/debug-flag.v new file mode 100644 index 0000000..5bd294a --- /dev/null +++ b/systemverilog-plugin/tests/debug-flag/debug-flag.v @@ -0,0 +1,31 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +module top ( + input clk, + output [3:0] led +); + + wire bufg; + BUF bufgctrl ( + .I(clk), + .O(bufg) + ); + reg [pkg::BITS + pkg::LOG2DELAY-1 : 0] counter = 0; + always @(posedge bufg) begin + counter <= counter + 1; + end + assign led[3:0] = counter >> pkg::LOG2DELAY; +endmodule diff --git a/systemverilog-plugin/tests/report-flag/report-flag-buf.sv b/systemverilog-plugin/tests/report-flag/report-flag-buf.sv new file mode 100644 index 0000000..565946b --- /dev/null +++ b/systemverilog-plugin/tests/report-flag/report-flag-buf.sv @@ -0,0 +1,21 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +module BUF ( + input I, + output O +); + assign O = I; +endmodule; diff --git a/systemverilog-plugin/tests/report-flag/report-flag-pkg.sv b/systemverilog-plugin/tests/report-flag/report-flag-pkg.sv new file mode 100644 index 0000000..b0362fc --- /dev/null +++ b/systemverilog-plugin/tests/report-flag/report-flag-pkg.sv @@ -0,0 +1,19 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +package pkg; + parameter BITS = 4; + parameter LOG2DELAY = 22; +endpackage diff --git a/systemverilog-plugin/tests/report-flag/report-flag.tcl b/systemverilog-plugin/tests/report-flag/report-flag.tcl new file mode 100644 index 0000000..3a3cc6d --- /dev/null +++ b/systemverilog-plugin/tests/report-flag/report-flag.tcl @@ -0,0 +1,16 @@ +yosys -import +if { [info procs read_uhdm] == {} } { plugin -i systemverilog } +yosys -import ;# ingest plugin commands + +set TMP_DIR /tmp +if { [info exists ::env(TMPDIR) ] } { + set TMP_DIR $::env(TMPDIR) +} + +# Testing simple round-trip +read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP)-pkg.sv +read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP)-buf.sv +read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP).v +read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -link +hierarchy +write_verilog diff --git a/systemverilog-plugin/tests/report-flag/report-flag.v b/systemverilog-plugin/tests/report-flag/report-flag.v new file mode 100644 index 0000000..5bd294a --- /dev/null +++ b/systemverilog-plugin/tests/report-flag/report-flag.v @@ -0,0 +1,31 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +module top ( + input clk, + output [3:0] led +); + + wire bufg; + BUF bufgctrl ( + .I(clk), + .O(bufg) + ); + reg [pkg::BITS + pkg::LOG2DELAY-1 : 0] counter = 0; + always @(posedge bufg) begin + counter <= counter + 1; + end + assign led[3:0] = counter >> pkg::LOG2DELAY; +endmodule diff --git a/systemverilog-plugin/uhdmastfrontend.cc b/systemverilog-plugin/uhdmastfrontend.cc index c09688c..5925d06 100644 --- a/systemverilog-plugin/uhdmastfrontend.cc +++ b/systemverilog-plugin/uhdmastfrontend.cc @@ -44,13 +44,14 @@ struct UhdmAstFrontend : public UhdmCommonFrontend { UHDM::Serializer serializer; std::vector restoredDesigns = serializer.Restore(filename); - UHDM::SynthSubset *synthSubset = new UHDM::SynthSubset(&serializer, this->shared.nonSynthesizableObjects, false); + UHDM::SynthSubset *synthSubset = + make_new_object_with_optional_extra_true_arg(&serializer, this->shared.nonSynthesizableObjects, false); synthSubset->listenDesigns(restoredDesigns); delete synthSubset; if (this->shared.debug_flag || !this->report_directory.empty()) { for (auto design : restoredDesigns) { - std::stringstream strstr; - UHDM::visit_object(design, 1, "", &this->shared.report.unhandled, this->shared.debug_flag ? std::cout : strstr); + std::ofstream null_stream; + UHDM::visit_object(design, 1, "", &this->shared.report.unhandled, this->shared.debug_flag ? std::cout : null_stream); } } UhdmAst uhdm_ast(this->shared); diff --git a/systemverilog-plugin/uhdmcommonfrontend.h b/systemverilog-plugin/uhdmcommonfrontend.h index 3d5ff16..e8b59f9 100644 --- a/systemverilog-plugin/uhdmcommonfrontend.h +++ b/systemverilog-plugin/uhdmcommonfrontend.h @@ -23,10 +23,28 @@ #include "uhdm/SynthSubset.h" #include "uhdm/VpiListener.h" #include +#include #include YOSYS_NAMESPACE_BEGIN +// FIXME (mglb): temporary fix to support UHDM both before and after the following change: +// https://github.com/chipsalliance/UHDM/commit/d78d094448bd94926644e48adea4df293b82f101 +// The commit introducing this code should to be reverted after Surelog is bumped to recent versions in all our repositories. +template , bool> = true> +static inline ObjT *make_new_object_with_optional_extra_true_arg(ArgN &&... arg_n) +{ + // Older UHDM version + return new ObjT(std::forward(arg_n)...); +} + +template , bool> = true> +static inline ObjT *make_new_object_with_optional_extra_true_arg(ArgN &&... arg_n) +{ + // Newer UHDM version + return new ObjT(std::forward(arg_n)..., true); +} + struct UhdmCommonFrontend : public Frontend { UhdmAstShared shared; std::string report_directory; diff --git a/systemverilog-plugin/uhdmsurelogastfrontend.cc b/systemverilog-plugin/uhdmsurelogastfrontend.cc index 0a72d26..d208cfb 100644 --- a/systemverilog-plugin/uhdmsurelogastfrontend.cc +++ b/systemverilog-plugin/uhdmsurelogastfrontend.cc @@ -29,6 +29,9 @@ #include #include #endif +#include + +#include #include "Surelog/ErrorReporting/Report.h" #include "Surelog/surelog.h" @@ -41,42 +44,73 @@ extern void visit_object(vpiHandle obj_h, int indent, const char *relation, std: YOSYS_NAMESPACE_BEGIN -std::vector executeCompilation(SURELOG::SymbolTable *symbolTable, SURELOG::ErrorContainer *errors, SURELOG::CommandLineParser *clp, - SURELOG::scompiler *compiler) +// Store systemverilog defaults to be passed for every invocation of read_systemverilog +static std::vector systemverilog_defaults; +static std::list> systemverilog_defaults_stack; + +// Store global definitions for top-level defines +static std::vector systemverilog_defines; + +// SURELOG::scompiler wrapper. +// Owns UHDM/VPI resources used by designs returned from `execute` +class Compiler { - bool success = true; - bool noFatalErrors = true; - unsigned int codedReturn = 0; - clp->setWriteUhdm(false); - errors->printMessages(clp->muteStdout()); - std::vector the_design; - if (success && (!clp->help())) { - compiler = SURELOG::start_compiler(clp); - if (!compiler) - codedReturn |= 1; - the_design.push_back(SURELOG::get_uhdm_design(compiler)); + public: + Compiler() = default; + ~Compiler() + { + if (this->scompiler) { + SURELOG::shutdown_compiler(this->scompiler); + } } - SURELOG::ErrorContainer::Stats stats; - if (!clp->help()) { - stats = errors->getErrorStats(); - if (stats.nbFatal) + + const std::vector &execute(std::unique_ptr errors, std::unique_ptr clp) + { + log_assert(!this->errors && !this->clp && !this->scompiler); + + bool success = true; + bool noFatalErrors = true; + unsigned int codedReturn = 0; + clp->setWriteUhdm(false); + errors->printMessages(clp->muteStdout()); + if (success && (!clp->help())) { + this->scompiler = SURELOG::start_compiler(clp.get()); + if (!this->scompiler) + codedReturn |= 1; + this->designs.push_back(SURELOG::get_uhdm_design(this->scompiler)); + } + SURELOG::ErrorContainer::Stats stats; + if (!clp->help()) { + stats = errors->getErrorStats(); + if (stats.nbFatal) + codedReturn |= 1; + if (stats.nbSyntax) + codedReturn |= 2; + } + bool noFErrors = true; + if (!clp->help()) + noFErrors = errors->printStats(stats, clp->muteStdout()); + if (noFErrors == false) { + noFatalErrors = false; + } + if ((!noFatalErrors) || (!success) || (errors->getErrorStats().nbError)) codedReturn |= 1; - if (stats.nbSyntax) - codedReturn |= 2; - } - bool noFErrors = true; - if (!clp->help()) - noFErrors = errors->printStats(stats, clp->muteStdout()); - if (noFErrors == false) { - noFatalErrors = false; - } - if ((!noFatalErrors) || (!success) || (errors->getErrorStats().nbError)) - codedReturn |= 1; - if (codedReturn) { - log_error("Error when parsing design. Aborting!\n"); + if (codedReturn) { + log_error("Error when parsing design. Aborting!\n"); + } + + this->clp = std::move(clp); + this->errors = std::move(errors); + + return this->designs; } - return the_design; -} + + private: + std::unique_ptr errors = nullptr; + std::unique_ptr clp = nullptr; + SURELOG::scompiler *scompiler = nullptr; + std::vector designs = {}; +}; struct UhdmSurelogAstFrontend : public UhdmCommonFrontend { UhdmSurelogAstFrontend(std::string name, std::string short_help) : UhdmCommonFrontend(name, short_help) {} @@ -94,13 +128,35 @@ struct UhdmSurelogAstFrontend : public UhdmCommonFrontend { AST::AstNode *parse(std::string filename) override { std::vector cstrings; - cstrings.reserve(this->args.size()); - for (size_t i = 0; i < this->args.size(); ++i) + bool link = false; + cstrings.reserve(this->args.size() + + systemverilog_defaults.size() + + systemverilog_defines.size()); + for (size_t i = 0; i < this->args.size(); ++i) { cstrings.push_back(const_cast(this->args[i].c_str())); + if (this->args[i] == "-link") + link = true; + } + + if (!link) { + // Add systemverilog defaults args + for (size_t i = 0; i < systemverilog_defaults.size(); ++i) { + // Convert args to surelog compatible + if (systemverilog_defaults[i] == "-defer") + this->shared.defer = true; + // Pass any remainings args directly to surelog + else + cstrings.push_back(const_cast(systemverilog_defaults[i].c_str())); + } + + // Add systemverilog defines args + for (size_t i = 0; i < systemverilog_defines.size(); ++i) + cstrings.push_back(const_cast(systemverilog_defines[i].c_str())); + } - SURELOG::SymbolTable *symbolTable = new SURELOG::SymbolTable(); - SURELOG::ErrorContainer *errors = new SURELOG::ErrorContainer(symbolTable); - SURELOG::CommandLineParser *clp = new SURELOG::CommandLineParser(errors, symbolTable, false, false); + auto symbolTable = std::make_unique(); + auto errors = std::make_unique(symbolTable.get()); + auto clp = std::make_unique(errors.get(), symbolTable.get(), false, false); bool success = clp->parseCommandLine(cstrings.size(), &cstrings[0]); if (!success) { log_error("Error parsing Surelog arguments!\n"); @@ -122,25 +178,21 @@ struct UhdmSurelogAstFrontend : public UhdmCommonFrontend { clp->setLink(true); } - SURELOG::scompiler *compiler = nullptr; - const std::vector uhdm_design = executeCompilation(symbolTable, errors, clp, compiler); + Compiler compiler; + const auto &uhdm_designs = compiler.execute(std::move(errors), std::move(clp)); + if (this->shared.debug_flag || !this->report_directory.empty()) { - for (auto design : uhdm_design) { - std::stringstream strstr; - UHDM::visit_object(design, 1, "", &this->shared.report.unhandled, this->shared.debug_flag ? std::cout : strstr); + for (auto design : uhdm_designs) { + std::ofstream null_stream; + UHDM::visit_object(design, 1, "", &this->shared.report.unhandled, this->shared.debug_flag ? std::cout : null_stream); } } - SURELOG::shutdown_compiler(compiler); - delete clp; - delete symbolTable; - delete errors; // on parse_only mode, don't try to load design // into yosys if (this->shared.parse_only) return nullptr; - UhdmAst uhdm_ast(this->shared); if (this->shared.defer && !this->shared.link) return nullptr; @@ -149,12 +201,14 @@ struct UhdmSurelogAstFrontend : public UhdmCommonFrontend { // Should be called 1. for normal flow 2. after finishing with `-link` if (!this->shared.defer) { UHDM::Serializer serializer; - UHDM::SynthSubset *synthSubset = new UHDM::SynthSubset(&serializer, this->shared.nonSynthesizableObjects, false); - synthSubset->listenDesigns(uhdm_design); + UHDM::SynthSubset *synthSubset = + make_new_object_with_optional_extra_true_arg(&serializer, this->shared.nonSynthesizableObjects, false); + synthSubset->listenDesigns(uhdm_designs); delete synthSubset; } - AST::AstNode *current_ast = uhdm_ast.visit_designs(uhdm_design); + UhdmAst uhdm_ast(this->shared); + AST::AstNode *current_ast = uhdm_ast.visit_designs(uhdm_designs); if (!this->report_directory.empty()) { this->shared.report.write(this->report_directory); } @@ -175,7 +229,179 @@ struct UhdmSystemVerilogFrontend : public UhdmSurelogAstFrontend { log("Read SystemVerilog files using Surelog into the current design\n"); log("\n"); this->print_read_options(); + log(" -Ipath\n"); + log(" add include path.\n"); + log("\n"); + log(" -Pparameter=value\n"); + log(" define parameter as value.\n"); + log("\n"); } } UhdmSystemVerilogFrontend; +struct SystemVerilogDefaults : public Pass { + SystemVerilogDefaults() : Pass("systemverilog_defaults", "set default options for read_systemverilog") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" systemverilog_defaults -add [options]\n"); + log("\n"); + log("Add the specified options to the list of default options to read_systemverilog.\n"); + log("\n"); + log("\n"); + log(" systemverilog_defaults -clear\n"); + log("\n"); + log("Clear the list of Systemverilog default options.\n"); + log("\n"); + log("\n"); + log(" systemverilog_defaults -push\n"); + log(" systemverilog_defaults -pop\n"); + log("\n"); + log("Push or pop the list of default options to a stack. Note that -push does\n"); + log("not imply -clear.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design*) override + { + if (args.size() < 2) + cmd_error(args, 1, "Missing argument."); + + if (args[1] == "-add") { + systemverilog_defaults.insert(systemverilog_defaults.end(), args.begin()+2, args.end()); + return; + } + + if (args.size() != 2) + cmd_error(args, 2, "Extra argument."); + + if (args[1] == "-clear") { + systemverilog_defaults.clear(); + return; + } + + if (args[1] == "-push") { + systemverilog_defaults_stack.push_back(systemverilog_defaults); + return; + } + + if (args[1] == "-pop") { + if (systemverilog_defaults_stack.empty()) { + systemverilog_defaults.clear(); + } else { + systemverilog_defaults.swap(systemverilog_defaults_stack.back()); + systemverilog_defaults_stack.pop_back(); + } + return; + } + } +} SystemVerilogDefaults; + +struct SystemVerilogDefines : public Pass { + SystemVerilogDefines() : Pass("systemverilog_defines", "define and undefine systemverilog defines") { + systemverilog_defines.push_back ("-PYOSYS=1"); + } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" systemverilog_defines [options]\n"); + log("\n"); + log("Define and undefine systemverilog preprocessor macros.\n"); + log("\n"); + log(" -Dname[=definition]\n"); + log(" define the preprocessor symbol 'name' and set its optional value\n"); + log(" 'definition'\n"); + log("\n"); + log(" -Uname[=definition]\n"); + log(" undefine the preprocessor symbol 'name'\n"); + log("\n"); + log(" -reset\n"); + log(" clear list of defined preprocessor symbols\n"); + log("\n"); + log(" -list\n"); + log(" list currently defined preprocessor symbols\n"); + log("\n"); + } + void remove(const std::string name) + { + auto it = systemverilog_defines.begin(); + while (it != systemverilog_defines.end()) { + std::string nm; + size_t equal = (*it).find('=', 2); + if (equal == std::string::npos) + nm = (*it).substr (2, std::string::npos); + else + nm = (*it).substr (2, equal-2); + if (name == nm) + systemverilog_defines.erase (it); + else + it++; + } + } + void dump(void) + { + for (size_t i = 0; i < systemverilog_defines.size(); ++i) { + std::string name, value = ""; + size_t equal = systemverilog_defines[i].find('=', 2); + name = systemverilog_defines[i].substr (2, equal-2); + if (equal != std::string::npos) + value = systemverilog_defines[i].substr(equal+1, std::string::npos); + Yosys::log("`define %s %s\n", + name.c_str(), value.c_str()); + } + } + void execute(std::vector args, RTLIL::Design *design) override + { + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + std::string arg = args[argidx]; + if (arg == "-D" && argidx+1 < args.size()) { + std::string name = args[++argidx], value; + size_t equal = name.find('='); + if (equal != std::string::npos) { + value = name.substr(equal+1); + name = name.substr(0, equal); + systemverilog_defines.push_back ("-P"+name+"="+value); + } else + systemverilog_defines.push_back ("-P"+name); + continue; + } + if (arg.compare(0, 2, "-D") == 0) { + size_t equal = arg.find('=', 2); + std::string name = arg.substr(2, equal-2); + std::string value; + if (equal != std::string::npos) { + value = arg.substr(equal+1); + systemverilog_defines.push_back ("-P"+name+"="+value); + } else + systemverilog_defines.push_back ("-P"+name); + continue; + } + if (arg == "-U" && argidx+1 < args.size()) { + std::string name = args[++argidx]; + this->remove (name); + continue; + } + if (arg.compare(0, 2, "-U") == 0) { + std::string name = arg.substr(2); + this->remove (name); + continue; + } + if (arg == "-reset") { + systemverilog_defines.erase (systemverilog_defines.begin()+1, + systemverilog_defines.end()); + continue; + } + if (arg == "-list") { + this->dump (); + continue; + } + break; + } + + if (args.size() != argidx) + cmd_error(args, argidx, "Extra argument."); + } +} SystemVerilogDefines; + YOSYS_NAMESPACE_END diff --git a/uhdm-plugin/Makefile b/uhdm-plugin/Makefile index 3eea3d4..4f67830 100644 --- a/uhdm-plugin/Makefile +++ b/uhdm-plugin/Makefile @@ -14,6 +14,8 @@ # # SPDX-License-Identifier: Apache-2.0 +PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + NAME = uhdm SOURCES = uhdm.cc include ../Makefile_plugin.common diff --git a/xdc-plugin/Makefile b/xdc-plugin/Makefile index 06d61d7..b2ebd88 100644 --- a/xdc-plugin/Makefile +++ b/xdc-plugin/Makefile @@ -14,12 +14,14 @@ # # SPDX-License-Identifier: Apache-2.0 +PLUGIN_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) + NAME = xdc SOURCES = xdc.cc include ../Makefile_plugin.common VERILOG_MODULES = BANK.v install_modules: $(VERILOG_MODULES) - install -D $< $(PLUGINS_DIR)/fasm_extra_modules/$< + install -D $< $(YOSYS_PLUGINS_DIR)/fasm_extra_modules/$< install: install_modules