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mc hck board blink only files

Signed-off-by: Anton Eltchaninov <anton.eltchaninov@gmail.com>
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commit d26c3b31785be9b7e006874ca24fb21ca3beb5b2 1 parent 25dd5cc
@anton19286 authored
Showing with 735 additions and 778 deletions.
  1. +1 −1  Makefile
  2. +0 −13 libmaple/include/libmaple/rcc.h
  3. +2 −2 libmaple/rules.mk
  4. +10 −0 libmaple/stm32f1/include/series/rcc.h
  5. +10 −0 libmaple/stm32f2/include/series/rcc.h
  6. +0 −4 libmaple/stm32l1/adc.c
  7. +10 −6 libmaple/stm32l1/gpio.c
  8. +5 −6 libmaple/stm32l1/include/series/adc.h
  9. +82 −62 libmaple/stm32l1/include/series/flash.h
  10. +72 −353 libmaple/stm32l1/include/series/gpio.h
  11. +51 −14 libmaple/stm32l1/include/series/pwr.h
  12. +118 −72 libmaple/stm32l1/include/series/rcc.h
  13. +2 −2 libmaple/stm32l1/include/series/stm32.h
  14. +7 −27 libmaple/stm32l1/include/series/timer.h
  15. +24 −71 libmaple/stm32l1/isrs_performance.S
  16. +4 −3 libmaple/stm32l1/rcc.c
  17. +10 −104 libmaple/stm32l1/timer.c
  18. +9 −26 libmaple/stm32l1/vector_table_performance.S
  19. +24 −0 support/ld/mchck/flash.ld
  20. +24 −0 support/ld/mchck/jtag.ld
  21. +22 −0 support/ld/mchck/ram.ld
  22. +5 −0 support/make/board-includes/mchck.mk
  23. +1 −1  wirish/boards.cpp
  24. +90 −0 wirish/boards/mchck/board.cpp
  25. +87 −0 wirish/boards/mchck/include/board/board.h
  26. +3 −0  wirish/boards_private.h
  27. +2 −2 wirish/include/wirish/wirish_debug.h
  28. +1 −1  wirish/rules.mk
  29. +59 −8 wirish/stm32l1/boards_setup.cpp
View
2  Makefile
@@ -31,7 +31,7 @@ PRODUCT_ID := 0003
# Try "make help" for more information on BOARD and MEMORY_TARGET;
# these default to a Maple Flash build.
-BOARD ?= STM32LDiscovery
+BOARD ?= mchck
MEMORY_TARGET ?= flash
# $(BOARD)- and $(MEMORY_TARGET)-specific configuration
View
13 libmaple/include/libmaple/rcc.h
@@ -37,19 +37,6 @@ extern "C"{
#endif
#include <libmaple/libmaple_types.h>
-
-/* Put the SYSCLK sources before the series header is included, as it
- * might need them. */
-/**
- * @brief SYSCLK sources
- * @see rcc_switch_sysclk()
- */
-typedef enum rcc_sysclk_src {
- RCC_CLKSRC_HSI = 0x0,
- RCC_CLKSRC_HSE = 0x1,
- RCC_CLKSRC_PLL = 0x2,
-} rcc_sysclk_src;
-
#include <series/rcc.h>
/* Note: Beyond the usual (registers, etc.), it's up to the series
View
4 libmaple/rules.mk
@@ -28,8 +28,8 @@ cSRCS_$(d) += util.c
# These still need to be ported to F2:
cSRCS_$(d) += dac.c
cSRCS_$(d) += dma.c
-cSRCS_$(d) += exti.c
-cSRCS_$(d) += i2c.c
+# cSRCS_$(d) += exti.c
+# cSRCS_$(d) += i2c.c
sSRCS_$(d) := exc.S
View
10 libmaple/stm32f1/include/series/rcc.h
@@ -39,6 +39,16 @@ extern "C"{
#include <libmaple/libmaple.h>
+/**
+ * @brief SYSCLK sources
+ * @see rcc_switch_sysclk()
+ */
+typedef enum rcc_sysclk_src {
+ RCC_CLKSRC_HSI = 0x0,
+ RCC_CLKSRC_HSE = 0x1,
+ RCC_CLKSRC_PLL = 0x2,
+} rcc_sysclk_src;
+
/*
* Register map
*/
View
10 libmaple/stm32f2/include/series/rcc.h
@@ -45,6 +45,16 @@ extern "C"{
#include <libmaple/libmaple.h>
+/**
+ * @brief SYSCLK sources
+ * @see rcc_switch_sysclk()
+ */
+typedef enum rcc_sysclk_src {
+ RCC_CLKSRC_HSI = 0x0,
+ RCC_CLKSRC_HSE = 0x1,
+ RCC_CLKSRC_PLL = 0x2,
+} rcc_sysclk_src;
+
/*
* Register map
*/
View
4 libmaple/stm32l1/adc.c
@@ -69,10 +69,6 @@ void adc_calibrate(const adc_dev *dev) {
* Common routines
*/
-void adc_set_prescaler(adc_prescaler pre) {
- rcc_set_prescaler(RCC_PRESCALER_ADC, (uint32)pre);
-}
-
void adc_foreach(void (*fn)(const adc_dev*)) {
fn(ADC1);
}
View
16 libmaple/stm32l1/gpio.c
@@ -39,7 +39,7 @@
gpio_dev gpioa = {
.regs = GPIOA_BASE,
.clk_id = RCC_GPIOA,
- .exti_port = AFIO_EXTI_PA,
+// .exti_port = AFIO_EXTI_PA,
};
/** GPIO port A device. */
gpio_dev* const GPIOA = &gpioa;
@@ -47,7 +47,7 @@ gpio_dev* const GPIOA = &gpioa;
gpio_dev gpiob = {
.regs = GPIOB_BASE,
.clk_id = RCC_GPIOB,
- .exti_port = AFIO_EXTI_PB,
+// .exti_port = AFIO_EXTI_PB,
};
/** GPIO port B device. */
gpio_dev* const GPIOB = &gpiob;
@@ -55,7 +55,7 @@ gpio_dev* const GPIOB = &gpiob;
gpio_dev gpioc = {
.regs = GPIOC_BASE,
.clk_id = RCC_GPIOC,
- .exti_port = AFIO_EXTI_PC,
+// .exti_port = AFIO_EXTI_PC,
};
/** GPIO port C device. */
gpio_dev* const GPIOC = &gpioc;
@@ -63,7 +63,7 @@ gpio_dev* const GPIOC = &gpioc;
gpio_dev gpiod = {
.regs = GPIOD_BASE,
.clk_id = RCC_GPIOD,
- .exti_port = AFIO_EXTI_PD,
+// .exti_port = AFIO_EXTI_PD,
};
/** GPIO port D device. */
gpio_dev* const GPIOD = &gpiod;
@@ -71,7 +71,7 @@ gpio_dev* const GPIOD = &gpiod;
gpio_dev gpioe = {
.regs = GPIOE_BASE,
.clk_id = RCC_GPIOE,
- .exti_port = AFIO_EXTI_PE,
+// .exti_port = AFIO_EXTI_PE,
};
/** GPIO port E device. */
gpio_dev* const GPIOE = &gpioe;
@@ -80,7 +80,7 @@ gpio_dev* const GPIOE = &gpioe;
gpio_dev gpioh = {
.regs = GPIOH_BASE,
.clk_id = RCC_GPIOH,
- .exti_port = AFIO_EXTI_PH,
+// .exti_port = AFIO_EXTI_PH,
};*/
/** GPIO port H device. */
// gpio_dev* const GPIOH = &gpioh;
@@ -200,6 +200,7 @@ void afio_init(void) {
* @see afio_exti_num
* @see afio_exti_port
*/
+/*
void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port) {
__io uint32 *exti_cr = &AFIO_BASE->EXTICR1 + exti / 4;
uint32 shift = 4 * (exti % 4);
@@ -209,11 +210,13 @@ void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port) {
cr |= gpio_port << shift;
*exti_cr = cr;
}
+*/
/**
* @brief Perform an alternate function remap.
* @param remapping Remapping to perform.
*/
+/*
void afio_remap(afio_remap_peripheral remapping) {
if (remapping & AFIO_REMAP_USE_MAPR2) {
remapping &= ~AFIO_REMAP_USE_MAPR2;
@@ -222,3 +225,4 @@ void afio_remap(afio_remap_peripheral remapping) {
AFIO_BASE->MAPR |= remapping;
}
}
+*/
View
11 libmaple/stm32l1/include/series/adc.h
@@ -221,20 +221,19 @@ typedef enum {
} adc_smp_rate;
/**
- * @brief STM32F1 ADC prescalers, as divisors of PCLK2.
+ * @brief STM32L1 ADC prescalers, as divisors of PCLK2.
*/
typedef enum adc_prescaler {
- ADC_PRE_PCLK2_DIV_2 = RCC_ADCPRE_PCLK_DIV_2, /** PCLK2 divided by 2 */
- ADC_PRE_PCLK2_DIV_4 = RCC_ADCPRE_PCLK_DIV_4, /** PCLK2 divided by 4 */
- ADC_PRE_PCLK2_DIV_6 = RCC_ADCPRE_PCLK_DIV_6, /** PCLK2 divided by 6 */
- ADC_PRE_PCLK2_DIV_8 = RCC_ADCPRE_PCLK_DIV_8, /** PCLK2 divided by 8 */
+ ADC_PRE_DIV_1, /** 16 MHz */
+ ADC_PRE_DIV_2, /** 8 MHz */
+ ADC_PRE_DIV_4, /** 4 MHz */
} adc_prescaler;
-
void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate);
void adc_calibrate(const adc_dev *dev);
uint16 adc_read(const adc_dev *dev, uint8 channel);
+
/**
* @brief Set external trigger conversion mode event for regular channels
* @param dev ADC device
View
144 libmaple/stm32l1/include/series/flash.h
@@ -25,16 +25,16 @@
*****************************************************************************/
/**
- * @file libmaple/stm32f1/flash.h
- * @brief STM32F1 Flash header.
+ * @file libmaple/stm32l1/flash.h
+ * @brief STM32L1 Flash header.
*
* Provides register map, base pointer, and register bit definitions
* for the Flash controller on the STM32F1 line, along with
* series-specific configuration values.
*/
-#ifndef _LIBMAPLE_STM32F1_FLASH_H_
-#define _LIBMAPLE_STM32F1_FLASH_H_
+#ifndef _LIBMAPLE_STM32L1_FLASH_H_
+#define _LIBMAPLE_STM32L1_FLASH_H_
#ifdef __cplusplus
extern "C"{
@@ -48,18 +48,22 @@ extern "C"{
/** Flash register map type */
typedef struct flash_reg_map {
- __io uint32 ACR; /**< Access control register */
- __io uint32 KEYR; /**< Key register */
- __io uint32 OPTKEYR; /**< OPTKEY register */
- __io uint32 SR; /**< Status register */
- __io uint32 CR; /**< Control register */
- __io uint32 AR; /**< Address register */
- __io uint32 OBR; /**< Option byte register */
- __io uint32 WRPR; /**< Write protection register */
+ __io uint32 ACR; /**< Access control register */
+ __io uint32 PECR; /**< Program/erase control register */
+ __io uint32 PDKEYR; /**< Power down key register */
+ __io uint32 PEKEYR; /**< SProgram/erase key register */
+ __io uint32 PRGKEYR; /**< Program memory key register */
+ __io uint32 OPTKEYR; /**< Option byte key register */
+ __io uint32 SR; /**< Status register */
+ __io uint32 OBR; /**< Option byte register */
+ __io uint32 WRPR1; /**< Write protection register 1 */
+ const uint32 RESERVED[0x5C];
+ __io uint32 WRPR2; /**< Write protection register 2 */
+ __io uint32 WRPR3; /**< Write protection register 3 */
} flash_reg_map;
/** Flash register map base pointer */
-#define FLASH_BASE ((struct flash_reg_map*)0x40022000)
+#define FLASH_BASE ((struct flash_reg_map*)0x40023C00)
/*
* Register bit definitions
@@ -67,80 +71,96 @@ typedef struct flash_reg_map {
/* Access control register */
-#define FLASH_ACR_PRFTBS_BIT 5
-#define FLASH_ACR_PRFTBE_BIT 4
-#define FLASH_ACR_HLFCYA_BIT 3
+#define FLASH_ACR_RUN_PD_BIT 4
+#define FLASH_ACR_SLEEP_PD_BIT 3
+#define FLASH_ACR_ACC64_BIT 2
+#define FLASH_ACR_PRFTEN_BIT 1
+#define FLASH_ACR_LATENCY_BIT 0
-#define FLASH_ACR_PRFTBS BIT(FLASH_ACR_PRFTBS_BIT)
-#define FLASH_ACR_PRFTBE BIT(FLASH_ACR_PRFTBE_BIT)
-#define FLASH_ACR_HLFCYA BIT(FLASH_ACR_HLFCYA_BIT)
-#define FLASH_ACR_LATENCY 0x7
+#define FLASH_ACR_RUN_PD BIT(FLASH_ACR_RUN_PD_BIT)
+#define FLASH_ACR_SLEEP_PD BIT(FLASH_ACR_SLEEP_PD_BIT)
+#define FLASH_ACR_ACC64 BIT(FLASH_ACR_ACC64_BIT)
+#define FLASH_ACR_PRFTEN BIT(FLASH_ACR_PRFTEN_BIT)
+#define FLASH_ACR_LATENCY BIT(FLASH_ACR_LATENCY_BIT)
/* Status register */
-#define FLASH_SR_EOP_BIT 5
-#define FLASH_SR_WRPRTERR_BIT 4
-#define FLASH_SR_PGERR_BIT 2
+#define FLASH_SR_OPTVERRUSR_BIT 12
+#define FLASH_SR_OPTVERR_BIT 11
+#define FLASH_SR_SIZEERR_BIT 10
+#define FLASH_SR_PGAERR_BIT 9
+#define FLASH_SR_WRPERR_BIT 8
+#define FLASH_SR_READY_BIT 3
+#define FLASH_SR_ENDHV_BIT 2
+#define FLASH_SR_EOP_BIT 1
#define FLASH_SR_BSY_BIT 0
+#define FLASH_SR_OPTVERRUSR BIT(FLASH_SR_OPTVERRUSR_BIT)
+#define FLASH_SR_OPTVERR BIT(FLASH_SR_OPTVERR_BIT)
+#define FLASH_SR_SIZEERR BIT(FLASH_SR_SIZEERR_BIT)
+#define FLASH_SR_PGAERR BIT(FLASH_SR_PGARR_BIT)
+#define FLASH_SR_WRPERR BIT(FLASH_SR_WRPERR_BIT)
+#define FLASH_SR_READY BIT(FLASH_SR_READY_BIT)
+#define FLASH_SR_ENDHV BIT(FLASH_SR_ENDHV_BIT)
#define FLASH_SR_EOP BIT(FLASH_SR_EOP_BIT)
-#define FLASH_SR_WRPRTERR BIT(FLASH_SR_WRPRTERR_BIT)
-#define FLASH_SR_PGERR BIT(FLASH_SR_PGERR_BIT)
#define FLASH_SR_BSY BIT(FLASH_SR_BSY_BIT)
/* Control register */
-#define FLASH_CR_EOPIE_BIT 12
-#define FLASH_CR_ERRIE_BIT 10
-#define FLASH_CR_OPTWRE_BIT 9
-#define FLASH_CR_LOCK_BIT 7
-#define FLASH_CR_STRT_BIT 6
-#define FLASH_CR_OPTER_BIT 5
-#define FLASH_CR_OPTPG_BIT 4
-#define FLASH_CR_MER_BIT 2
-#define FLASH_CR_PER_BIT 1
-#define FLASH_CR_PG_BIT 0
-
-#define FLASH_CR_EOPIE BIT(FLASH_CR_EOPIE_BIT)
-#define FLASH_CR_ERRIE BIT(FLASH_CR_ERRIE_BIT)
-#define FLASH_CR_OPTWRE BIT(FLASH_CR_OPTWRE_BIT)
-#define FLASH_CR_LOCK BIT(FLASH_CR_LOCK_BIT)
-#define FLASH_CR_STRT BIT(FLASH_CR_STRT_BIT)
-#define FLASH_CR_OPTER BIT(FLASH_CR_OPTER_BIT)
-#define FLASH_CR_OPTPG BIT(FLASH_CR_OPTPG_BIT)
-#define FLASH_CR_MER BIT(FLASH_CR_MER_BIT)
-#define FLASH_CR_PER BIT(FLASH_CR_PER_BIT)
-#define FLASH_CR_PG BIT(FLASH_CR_PG_BIT)
+#define FLASH_PECR_OBL_LAUNCH_BIT 18
+#define FLASH_PECR_ERRIE_BIT 17
+#define FLASH_PECR_EOPIE_BIT 16
+#define FLASH_PECR_PARALLELBANK_BIT 15
+#define FLASH_PECR_FPRG_BIT 10
+#define FLASH_PECR_ERASE_BIT 9
+#define FLASH_PECR_FTDW_BIT 8
+#define FLASH_PECR_DATA_BIT 4
+#define FLASH_PECR_PROG_BIT 3
+#define FLASH_PECR_OPTLOCK_BIT 2
+#define FLASH_PECR_PRGLOCK_BIT 1
+#define FLASH_PECR_PELOCK_BIT 0
+
+#define FLASH_PECR_OBL_LAUNCH BIT(FLASH_PECR_OBL_LAUNCH_BIT)
+#define FLASH_PECR_ERRIE BIT(FLASH_PECR_ERRIE_BIT)
+#define FLASH_PECR_EOPIE BIT(FLASH_PECR_EOPIE_BIT)
+#define FLASH_PECR_PARALLELBANK BIT(FLASH_PECR_PARALLELBANK_BIT)
+#define FLASH_PECR_FPRG BIT(FLASH_PECR_FPRG_BIT)
+#define FLASH_PECR_ERASE BIT(FLASH_PECR_ERASE_BIT)
+#define FLASH_PECR_FTDW BIT(FLASH_PECR_FTDW_BIT)
+#define FLASH_PECR_DATA BIT(FLASH_PECR_DATA_BIT)
+#define FLASH_PECR_PROG BIT(FLASH_PECR_PROG_BIT)
+
+#define FLASH_PECR_OPTLOCK BIT(FLASH_PECR_OPTLOCK_BIT)
+#define FLASH_PECR_PRGLOCK BIT(FLASH_PECR_PRGLOCK_BIT)
+#define FLASH_PECR_PELOCK BIT(FLASH_PECR_PELOCK_BIT)
/* Option byte register */
-#define FLASH_OBR_nRST_STDBY_BIT 4
-#define FLASH_OBR_nRST_STOP_BIT 3
-#define FLASH_OBR_WDG_SW_BIT 2
-#define FLASH_OBR_RDPRT_BIT 1
-#define FLASH_OBR_OPTERR_BIT 0
+#define FLASH_OBR_BFB2_BIT 23
+#define FLASH_OBR_nRST_STDBY_BIT 22
+#define FLASH_OBR_nRST_STOP_BIT 21
+#define FLASH_OBR_IWDG_SW_BIT 20
-#define FLASH_OBR_DATA1 (0xFF << 18)
-#define FLASH_OBR_DATA0 (0xFF << 10)
-#define FLASH_OBR_USER 0x3FF
+#define FLASH_OBR_BOR_LEV (0xF << 16)
+#define FLASH_OBR_RDPRT 0xFF
+#define FLASH_OBR_BFB2 BIT(FLASH_OBR_BFB2_BIT)
#define FLASH_OBR_nRST_STDBY BIT(FLASH_OBR_nRST_STDBY_BIT)
#define FLASH_OBR_nRST_STOP BIT(FLASH_OBR_nRST_STOP_BIT)
-#define FLASH_OBR_WDG_SW BIT(FLASH_OBR_WDG_SW_BIT)
-#define FLASH_OBR_RDPRT BIT(FLASH_OBR_RDPRT_BIT)
-#define FLASH_OBR_OPTERR BIT(FLASH_OBR_OPTERR_BIT)
+#define FLASH_OBR_IWDG_SW BIT(FLASH_OBR_WDG_SW_BIT)
/*
* Series-specific configuration values.
*/
-#define FLASH_SAFE_WAIT_STATES FLASH_WAIT_STATE_2
+#define FLASH_SAFE_WAIT_STATES FLASH_WAIT_STATE_1
/* Flash memory features available via ACR */
enum {
- FLASH_PREFETCH = 0x10,
- FLASH_HALF_CYCLE = 0x8,
- FLASH_ICACHE = 0x0, /* Not available on STM32F1 */
- FLASH_DCACHE = 0x0, /* Not available on STM32F1 */
+ FLASH_PREFETCH = FLASH_ACR_PRFTEN,
+ FLASH_ACC64 = FLASH_ACR_ACC64,
+ FLASH_HALF_CYCLE = 0x0, /* Not available on STM32L1 */
+ FLASH_ICACHE = 0x0, /* Not available on STM32L1 */
+ FLASH_DCACHE = 0x0, /* Not available on STM32L1 */
};
#ifdef __cplusplus
View
425 libmaple/stm32l1/include/series/gpio.h
@@ -46,42 +46,36 @@ extern "C"{
*/
/** GPIO register map type */
-
typedef struct gpio_reg_map {
- __io uint32 MODER; /**< Port mode register */
- __io uint32 OTYPER; /**< Port output type register */
- __io uint32 OSPEEDR; /**< Port output speed register */
- __io uint32 PUPDR; /**< Port pull-up/pull-down register */
- __io uint32 IDR; /**< Port input data register */
- __io uint32 ODR; /**< Port output data register */
- __io uint32 BSRR; /**< Port bit set/reset register */
- __io uint32 LCKR; /**< Port configuration lock register */
- __io uint32 AFRL; /**< Port alternate function low register */
- __io uint32 AFRH; /**< Port alternate function high register */
-
+ __io uint32 MODER; /**< Mode register */
+ __io uint32 OTYPER; /**< Output type register */
+ __io uint32 OSPEEDR; /**< Output speed register */
+ __io uint32 PUPDR; /**< Pull-up/pull-down register */
+ __io uint32 IDR; /**< Input data register */
+ __io uint32 ODR; /**< Output data register */
+ __io uint32 BSRR; /**< Bit set/reset register */
+ __io uint32 LCKR; /**< Configuration lock register */
+ __io uint32 AFRL; /**< Alternate function low register */
+ __io uint32 AFRH; /**< Alternate function high register */
} gpio_reg_map;
-
-/**
- * @brief External interrupt line port selector.
- *
- * Used to determine which GPIO port to map an external interrupt line
- * onto. */
-/* (See AFIO sections, below) */
-typedef enum afio_exti_port {
- AFIO_EXTI_PA, /**< Use port A (PAx) pin. */
- AFIO_EXTI_PB, /**< Use port B (PBx) pin. */
- AFIO_EXTI_PC, /**< Use port C (PCx) pin. */
- AFIO_EXTI_PD, /**< Use port D (PDx) pin. */
- AFIO_EXTI_PE, /**< Use port E (PEx) pin. */
- AFIO_EXTI_PH, /**< Use port H (PHx) pin. */
-} afio_exti_port;
+/** GPIO port A register map base pointer */
+#define GPIOA_BASE ((struct gpio_reg_map*)0x40020000)
+/** GPIO port B register map base pointer */
+#define GPIOB_BASE ((struct gpio_reg_map*)0x40020400)
+/** GPIO port C register map base pointer */
+#define GPIOC_BASE ((struct gpio_reg_map*)0x40020800)
+/** GPIO port D register map base pointer */
+#define GPIOD_BASE ((struct gpio_reg_map*)0x40020C00)
+/** GPIO port E register map base pointer */
+#define GPIOE_BASE ((struct gpio_reg_map*)0x40021000)
+/** GPIO port H register map base pointer */
+#define GPIOH_BASE ((struct gpio_reg_map*)0x40021400)
/** GPIO device type */
typedef struct gpio_dev {
gpio_reg_map *regs; /**< Register map */
rcc_clk_id clk_id; /**< RCC clock information */
- afio_exti_port exti_port; /**< AFIO external interrupt port value */
} gpio_dev;
extern gpio_dev gpioa;
@@ -94,51 +88,60 @@ extern gpio_dev gpiod;
extern gpio_dev* const GPIOD;
extern gpio_dev gpioe;
extern gpio_dev* const GPIOE;
-extern gpio_dev gpiof;
+extern gpio_dev gpioh;
extern gpio_dev* const GPIOH;
-/** GPIO port A register map base pointer */
-#define GPIOA_BASE ((struct gpio_reg_map*)0x40020000)
-/** GPIO port B register map base pointer */
-#define GPIOB_BASE ((struct gpio_reg_map*)0x40020400)
-/** GPIO port C register map base pointer */
-#define GPIOC_BASE ((struct gpio_reg_map*)0x40020800)
-/** GPIO port D register map base pointer */
-#define GPIOD_BASE ((struct gpio_reg_map*)0x40020C00)
-/** GPIO port E register map base pointer */
-#define GPIOE_BASE ((struct gpio_reg_map*)0x40021000)
-/** GPIO port H register map base pointer */
-#define GPIOH_BASE ((struct gpio_reg_map*)0x40021400)
-/** GPIO port F register map base pointer */
-#define GPIOF_BASE ((struct gpio_reg_map*)0x40021800)
-/** GPIO port G register map base pointer */
-#define GPIOG_BASE ((struct gpio_reg_map*)0x40021C00)
-
-
/*
* GPIO register bit definitions
*/
/* Control registers */
+/* Mode register */
#define GPIO_MODE_INPUT 0x0
#define GPIO_MODE_OUTPUT 0x1
#define GPIO_MODE_AF 0x2
#define GPIO_MODE_ANALOG 0x3
+/* Output type register */
+
#define GPIO_OTYPE_PP 0x0
#define GPIO_OTYPE_OD 0x1
+/* Output speed register */
+
#define GPIO_OSPEED_400KHZ 0x0
#define GPIO_OSPEED_2MHZ 0x1
#define GPIO_OSPEED_10MHZ 0x2
#define GPIO_OSPEED_40MHZ 0x3
+/* Pull-up/pull-down register */
+
#define GPIO_PUPD_NO_PUPD 0x0
#define GPIO_PUPD_PU 0x1
#define GPIO_PUPD_PD 0x2
-
+/* Alternate function register low */
+
+#define GPIO_AFRL_AF0 (0xFU << 0)
+#define GPIO_AFRL_AF1 (0xFU << 4)
+#define GPIO_AFRL_AF2 (0xFU << 8)
+#define GPIO_AFRL_AF3 (0xFU << 12)
+#define GPIO_AFRL_AF4 (0xFU << 16)
+#define GPIO_AFRL_AF5 (0xFU << 20)
+#define GPIO_AFRL_AF6 (0xFU << 24)
+#define GPIO_AFRL_AF7 (0xFU << 28)
+
+/* Alternate function register high */
+
+#define GPIO_AFRH_AF8 (0xFU << 0)
+#define GPIO_AFRH_AF9 (0xFU << 4)
+#define GPIO_AFRH_AF10 (0xFU << 8)
+#define GPIO_AFRH_AF11 (0xFU << 12)
+#define GPIO_AFRH_AF12 (0xFU << 16)
+#define GPIO_AFRH_AF13 (0xFU << 20)
+#define GPIO_AFRH_AF14 (0xFU << 24)
+#define GPIO_AFRH_AF15 (0xFU << 28)
/**
* @brief GPIO Pin modes.
*
@@ -156,315 +159,31 @@ typedef enum gpio_pin_mode {
GPIO_INPUT_PU /**< Input pull-up. */
} gpio_pin_mode;
-/**
- * @brief Get a GPIO port's corresponding afio_exti_port.
- * @param dev GPIO device whose afio_exti_port to return.
- */
-static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
- return dev->exti_port;
-}
-
-/*
- * AFIO register map
- */
-
-/** AFIO register map */
-typedef struct afio_reg_map {
- __io uint32 EVCR; /**< Event control register. */
- __io uint32 MAPR; /**< AF remap and debug I/O configuration
- register. */
- __io uint32 EXTICR1; /**< External interrupt configuration
- register 1. */
- __io uint32 EXTICR2; /**< External interrupt configuration
- register 2. */
- __io uint32 EXTICR3; /**< External interrupt configuration
- register 3. */
- __io uint32 EXTICR4; /**< External interrupt configuration
- register 4. */
- __io uint32 MAPR2; /**< AF remap and debug I/O configuration
- register 2. */
-} afio_reg_map;
-
-/** AFIO register map base pointer. */
-#define AFIO_BASE ((struct afio_reg_map *)0x40010000)
-
-/*
- * AFIO register bit definitions
- */
-
-/* Event control register */
-
-#define AFIO_EVCR_EVOE (0x1 << 7)
-#define AFIO_EVCR_PORT_PA (0x0 << 4)
-#define AFIO_EVCR_PORT_PB (0x1 << 4)
-#define AFIO_EVCR_PORT_PC (0x2 << 4)
-#define AFIO_EVCR_PORT_PD (0x3 << 4)
-#define AFIO_EVCR_PORT_PE (0x4 << 4)
-#define AFIO_EVCR_PIN_0 0x0
-#define AFIO_EVCR_PIN_1 0x1
-#define AFIO_EVCR_PIN_2 0x2
-#define AFIO_EVCR_PIN_3 0x3
-#define AFIO_EVCR_PIN_4 0x4
-#define AFIO_EVCR_PIN_5 0x5
-#define AFIO_EVCR_PIN_6 0x6
-#define AFIO_EVCR_PIN_7 0x7
-#define AFIO_EVCR_PIN_8 0x8
-#define AFIO_EVCR_PIN_9 0x9
-#define AFIO_EVCR_PIN_10 0xA
-#define AFIO_EVCR_PIN_11 0xB
-#define AFIO_EVCR_PIN_12 0xC
-#define AFIO_EVCR_PIN_13 0xD
-#define AFIO_EVCR_PIN_14 0xE
-#define AFIO_EVCR_PIN_15 0xF
-
-/* AF remap and debug I/O configuration register */
-
-#define AFIO_MAPR_SWJ_CFG (0x7 << 24)
-#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
-#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST (0x1 << 24)
-#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW (0x2 << 24)
-#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW (0x4 << 24)
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP BIT(20)
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP BIT(19)
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP BIT(18)
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP BIT(17)
-#define AFIO_MAPR_TIM5CH4_IREMAP BIT(16)
-#define AFIO_MAPR_PD01_REMAP BIT(15)
-#define AFIO_MAPR_CAN_REMAP (0x3 << 13)
-#define AFIO_MAPR_CAN_REMAP_NONE (0x0 << 13)
-#define AFIO_MAPR_CAN_REMAP_PB8_PB9 (0x2 << 13)
-#define AFIO_MAPR_CAN_REMAP_PD0_PD1 (0x3 << 13)
-#define AFIO_MAPR_TIM4_REMAP BIT(12)
-#define AFIO_MAPR_TIM3_REMAP (0x3 << 10)
-#define AFIO_MAPR_TIM3_REMAP_NONE (0x0 << 10)
-#define AFIO_MAPR_TIM3_REMAP_PARTIAL (0x2 << 10)
-#define AFIO_MAPR_TIM3_REMAP_FULL (0x3 << 10)
-#define AFIO_MAPR_TIM2_REMAP (0x3 << 8)
-#define AFIO_MAPR_TIM2_REMAP_NONE (0x0 << 8)
-#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 (0x1 << 8)
-#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8)
-#define AFIO_MAPR_TIM2_REMAP_FULL (0x3 << 8)
-#define AFIO_MAPR_TIM1_REMAP (0x3 << 6)
-#define AFIO_MAPR_TIM1_REMAP_NONE (0x0 << 6)
-#define AFIO_MAPR_TIM1_REMAP_PARTIAL (0x1 << 6)
-#define AFIO_MAPR_TIM1_REMAP_FULL (0x3 << 6)
-#define AFIO_MAPR_USART3_REMAP (0x3 << 4)
-#define AFIO_MAPR_USART3_REMAP_NONE (0x0 << 4)
-#define AFIO_MAPR_USART3_REMAP_PARTIAL (0x1 << 4)
-#define AFIO_MAPR_USART3_REMAP_FULL (0x3 << 4)
-#define AFIO_MAPR_USART2_REMAP BIT(3)
-#define AFIO_MAPR_USART1_REMAP BIT(2)
-#define AFIO_MAPR_I2C1_REMAP BIT(1)
-#define AFIO_MAPR_SPI1_REMAP BIT(0)
-
-/* External interrupt configuration register 1 */
-
-#define AFIO_EXTICR1_EXTI3 (0xF << 12)
-#define AFIO_EXTICR1_EXTI3_PA (0x0 << 12)
-#define AFIO_EXTICR1_EXTI3_PB (0x1 << 12)
-#define AFIO_EXTICR1_EXTI3_PC (0x2 << 12)
-#define AFIO_EXTICR1_EXTI3_PD (0x3 << 12)
-#define AFIO_EXTICR1_EXTI3_PE (0x4 << 12)
-#define AFIO_EXTICR1_EXTI3_PF (0x5 << 12)
-#define AFIO_EXTICR1_EXTI3_PG (0x6 << 12)
-#define AFIO_EXTICR1_EXTI2 (0xF << 8)
-#define AFIO_EXTICR1_EXTI2_PA (0x0 << 8)
-#define AFIO_EXTICR1_EXTI2_PB (0x1 << 8)
-#define AFIO_EXTICR1_EXTI2_PC (0x2 << 8)
-#define AFIO_EXTICR1_EXTI2_PD (0x3 << 8)
-#define AFIO_EXTICR1_EXTI2_PE (0x4 << 8)
-#define AFIO_EXTICR1_EXTI2_PF (0x5 << 8)
-#define AFIO_EXTICR1_EXTI2_PG (0x6 << 8)
-#define AFIO_EXTICR1_EXTI1 (0xF << 4)
-#define AFIO_EXTICR1_EXTI1_PA (0x0 << 4)
-#define AFIO_EXTICR1_EXTI1_PB (0x1 << 4)
-#define AFIO_EXTICR1_EXTI1_PC (0x2 << 4)
-#define AFIO_EXTICR1_EXTI1_PD (0x3 << 4)
-#define AFIO_EXTICR1_EXTI1_PE (0x4 << 4)
-#define AFIO_EXTICR1_EXTI1_PF (0x5 << 4)
-#define AFIO_EXTICR1_EXTI1_PG (0x6 << 4)
-#define AFIO_EXTICR1_EXTI0 0xF
-#define AFIO_EXTICR1_EXTI0_PA 0x0
-#define AFIO_EXTICR1_EXTI0_PB 0x1
-#define AFIO_EXTICR1_EXTI0_PC 0x2
-#define AFIO_EXTICR1_EXTI0_PD 0x3
-#define AFIO_EXTICR1_EXTI0_PE 0x4
-#define AFIO_EXTICR1_EXTI0_PF 0x5
-#define AFIO_EXTICR1_EXTI0_PG 0x6
-
-/* External interrupt configuration register 2 */
-
-#define AFIO_EXTICR2_EXTI7 (0xF << 12)
-#define AFIO_EXTICR2_EXTI7_PA (0x0 << 12)
-#define AFIO_EXTICR2_EXTI7_PB (0x1 << 12)
-#define AFIO_EXTICR2_EXTI7_PC (0x2 << 12)
-#define AFIO_EXTICR2_EXTI7_PD (0x3 << 12)
-#define AFIO_EXTICR2_EXTI7_PE (0x4 << 12)
-#define AFIO_EXTICR2_EXTI7_PF (0x5 << 12)
-#define AFIO_EXTICR2_EXTI7_PG (0x6 << 12)
-#define AFIO_EXTICR2_EXTI6 (0xF << 8)
-#define AFIO_EXTICR2_EXTI6_PA (0x0 << 8)
-#define AFIO_EXTICR2_EXTI6_PB (0x1 << 8)
-#define AFIO_EXTICR2_EXTI6_PC (0x2 << 8)
-#define AFIO_EXTICR2_EXTI6_PD (0x3 << 8)
-#define AFIO_EXTICR2_EXTI6_PE (0x4 << 8)
-#define AFIO_EXTICR2_EXTI6_PF (0x5 << 8)
-#define AFIO_EXTICR2_EXTI6_PG (0x6 << 8)
-#define AFIO_EXTICR2_EXTI5 (0xF << 4)
-#define AFIO_EXTICR2_EXTI5_PA (0x0 << 4)
-#define AFIO_EXTICR2_EXTI5_PB (0x1 << 4)
-#define AFIO_EXTICR2_EXTI5_PC (0x2 << 4)
-#define AFIO_EXTICR2_EXTI5_PD (0x3 << 4)
-#define AFIO_EXTICR2_EXTI5_PE (0x4 << 4)
-#define AFIO_EXTICR2_EXTI5_PF (0x5 << 4)
-#define AFIO_EXTICR2_EXTI5_PG (0x6 << 4)
-#define AFIO_EXTICR2_EXTI4 0xF
-#define AFIO_EXTICR2_EXTI4_PA 0x0
-#define AFIO_EXTICR2_EXTI4_PB 0x1
-#define AFIO_EXTICR2_EXTI4_PC 0x2
-#define AFIO_EXTICR2_EXTI4_PD 0x3
-#define AFIO_EXTICR2_EXTI4_PE 0x4
-#define AFIO_EXTICR2_EXTI4_PF 0x5
-#define AFIO_EXTICR2_EXTI4_PG 0x6
-
-/* AF remap and debug I/O configuration register 2 */
-
-#define AFIO_MAPR2_FSMC_NADV BIT(10)
-#define AFIO_MAPR2_TIM14_REMAP BIT(9)
-#define AFIO_MAPR2_TIM13_REMAP BIT(8)
-#define AFIO_MAPR2_TIM11_REMAP BIT(7)
-#define AFIO_MAPR2_TIM10_REMAP BIT(6)
-#define AFIO_MAPR2_TIM9_REMAP BIT(5)
-
-/*
- * AFIO convenience routines
- */
-
-void afio_init(void);
-
-/**
- * External interrupt line numbers.
- */
-typedef enum afio_exti_num {
- AFIO_EXTI_0, /**< External interrupt line 0. */
- AFIO_EXTI_1, /**< External interrupt line 1. */
- AFIO_EXTI_2, /**< External interrupt line 2. */
- AFIO_EXTI_3, /**< External interrupt line 3. */
- AFIO_EXTI_4, /**< External interrupt line 4. */
- AFIO_EXTI_5, /**< External interrupt line 5. */
- AFIO_EXTI_6, /**< External interrupt line 6. */
- AFIO_EXTI_7, /**< External interrupt line 7. */
- AFIO_EXTI_8, /**< External interrupt line 8. */
- AFIO_EXTI_9, /**< External interrupt line 9. */
- AFIO_EXTI_10, /**< External interrupt line 10. */
- AFIO_EXTI_11, /**< External interrupt line 11. */
- AFIO_EXTI_12, /**< External interrupt line 12. */
- AFIO_EXTI_13, /**< External interrupt line 13. */
- AFIO_EXTI_14, /**< External interrupt line 14. */
- AFIO_EXTI_15, /**< External interrupt line 15. */
-} afio_exti_num;
-
-void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port);
-
-/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and
- * not used in either MAPR or MAPR2 */
-#define AFIO_REMAP_USE_MAPR2 (1 << 31)
/**
- * @brief Available peripheral remaps.
- * @see afio_remap()
+ * @brief GPIO alternate functions.
+ * Use these to select an alternate function for a pin.
+ * @see gpio_set_af()
*/
-typedef enum afio_remap_peripheral {
- AFIO_REMAP_ADC2_ETRGREG = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**<
- ADC 2 external trigger regular conversion remapping */
- AFIO_REMAP_ADC2_ETRGINJ = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**<
- ADC 2 external trigger injected conversion remapping */
- AFIO_REMAP_ADC1_ETRGREG = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**<
- ADC 1 external trigger regular conversion remapping */
- AFIO_REMAP_ADC1_ETRGINJ = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**<
- ADC 1 external trigger injected conversion remapping */
- AFIO_REMAP_TIM5CH4_I = AFIO_MAPR_TIM5CH4_IREMAP, /**<
- Timer 5 channel 4 internal remapping */
- AFIO_REMAP_PD01 = AFIO_MAPR_PD01_REMAP, /**<
- Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
- AFIO_REMAP_CAN_1 = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**<
- CAN alternate function remapping 1 (RX on PB8, TX on PB9) */
- AFIO_REMAP_CAN_2 = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**<
- CAN alternate function remapping 2 (RX on PD0, TX on PD1) */
- AFIO_REMAP_TIM4 = AFIO_MAPR_TIM4_REMAP, /**<
- Timer 4 remapping */
- AFIO_REMAP_TIM3_PARTIAL = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**<
- Timer 3 partial remapping */
- AFIO_REMAP_TIM3_FULL = AFIO_MAPR_TIM3_REMAP_FULL, /**<
- Timer 3 full remapping */
- AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**<
- Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3
- on PA2, CH4 on PA3) */
- AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**<
- Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3
- on PB10, CH4 on PB11) */
- AFIO_REMAP_TIM2_FULL = AFIO_MAPR_TIM2_REMAP_FULL, /**<
- Timer 2 full remapping */
- AFIO_REMAP_USART2 = AFIO_MAPR_USART2_REMAP, /**<
- USART 2 remapping */
- AFIO_REMAP_USART1 = AFIO_MAPR_USART1_REMAP, /**<
- USART 1 remapping */
- AFIO_REMAP_I2C1 = AFIO_MAPR_I2C1_REMAP, /**<
- I2C 1 remapping */
- AFIO_REMAP_SPI1 = AFIO_MAPR_SPI1_REMAP, /**<
- SPI 1 remapping */
- AFIO_REMAP_FSMC_NADV = (AFIO_MAPR2_FSMC_NADV |
- AFIO_REMAP_USE_MAPR2), /**<
- NADV signal not connected */
- AFIO_REMAP_TIM14 = (AFIO_MAPR2_TIM14_REMAP |
- AFIO_REMAP_USE_MAPR2), /**<
- Timer 14 remapping */
- AFIO_REMAP_TIM13 = (AFIO_MAPR2_TIM13_REMAP |
- AFIO_REMAP_USE_MAPR2), /**<
- Timer 13 remapping */
- AFIO_REMAP_TIM11 = (AFIO_MAPR2_TIM11_REMAP |
- AFIO_REMAP_USE_MAPR2), /**<
- Timer 11 remapping */
- AFIO_REMAP_TIM10 = (AFIO_MAPR2_TIM10_REMAP |
- AFIO_REMAP_USE_MAPR2), /**<
- Timer 10 remapping */
- AFIO_REMAP_TIM9 = (AFIO_MAPR2_TIM9_REMAP |
- AFIO_REMAP_USE_MAPR2) /**<
- Timer 9 */
-} afio_remap_peripheral;
+typedef enum gpio_af {
+ GPIO_AF_SYS = 0, /**< System. */
+ GPIO_AF_TIM_2 = 1, /**< Timer 2. */
+ GPIO_AF_TIM_3_4 = 2, /**< Timers 3 and 4. */
+ GPIO_AF_TIM_9_10_11 = 3, /**< Timers 9 through 11. */
+ GPIO_AF_I2C = 4, /**< I2C 1 and 2. */
+ GPIO_AF_SPI_1_2 = 5, /**< SPI1, SPI2. */
+ GPIO_AF_6 = 6, /**< Not used?. */
+ GPIO_AF_USART_1_2_3 = 7, /**< USART 1, 2, and 3. */
+ GPIO_AF_8 = 8, /**< Not used?. */
+ GPIO_AF_9 = 9, /**< Not used?. */
+ GPIO_AF_USB = 10, /**< USB. */
+ GPIO_AF_LCD = 11, /**< LCD. */
+ GPIO_AF_12 = 12, /**< Not used?. */
+ GPIO_AF_13 = 13, /**< Not used?. */
+ GPIO_AF_RI = 13, /**< RI. */
+ GPIO_AF_EVENTOUT = 15, /**< EVENTOUT. */
+} gpio_af;
-void afio_remap(afio_remap_peripheral p);
-
-/**
- * @brief Debug port configuration
- *
- * Used to configure the behavior of JTAG and Serial Wire (SW) debug
- * ports and their associated GPIO pins.
- *
- * @see afio_cfg_debug_ports()
- */
-typedef enum afio_debug_cfg {
- AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**<
- Full Serial Wire and JTAG debug */
- AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**<
- Full Serial Wire and JTAG, but no NJTRST. */
- AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**<
- Serial Wire debug only (JTAG-DP disabled,
- SW-DP enabled) */
- AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**<
- No debug; all JTAG and SW pins are free
- for use as GPIOs. */
-} afio_debug_cfg;
-
-/**
- * @brief Enable or disable the JTAG and SW debug ports.
- * @param config Desired debug port configuration
- * @see afio_debug_cfg
- */
-static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
- __io uint32 *mapr = &AFIO_BASE->MAPR;
- *mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
-}
#ifdef __cplusplus
}
View
65 libmaple/stm32l1/include/series/pwr.h
@@ -25,28 +25,65 @@
*****************************************************************************/
/**
- * @file stm32f1/pwr.h
- * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief STM32F1 Power control (PWR) support.
+ * @file stm32l1/pwr.h
+ * @brief STM32L1 Power control (PWR) support.
*/
-#ifndef _LIBMAPLE_STM32F1_PWR_H_
-#define _LIBMAPLE_STM32F1_PWR_H_
+#ifndef _LIBMAPLE_STM32L1_PWR_H_
+#define _LIBMAPLE_STM32L1_PWR_H_
+
+/** Power register map type */
+// typedef struct pwr_reg_map {
+// __io uint32 CR; /**< Control register */
+// __io uint32 CSR; /**< Control/status register */
+// } pwr_reg_map;
/*
* Register bit definitions
*/
-
/* Control register */
+#define PWR_CR_LPRUN_BIT 14
+#define PWR_CR_FWU_BIT 10
+#define PWR_CR_ULP_BIT 9
+#define PWR_CR_DBP_BIT 8
+#define PWR_CR_PVDE_BIT 4
+#define PWR_CR_CSBF_BIT 3
+#define PWR_CR_CWUF_BIT 2
+#define PWR_CR_PDDS_BIT 1
+#define PWR_CR_LPSDSR_BIT 0
+
+#define PWR_CR_VOS (0x3 << 12)
+#define PWR_CR_PLS (0x7 << 5)
+
+/* Voltage scaling range selection */
+#define PWR_CR_VOS_1_2V (0x3 << 12)
+#define PWR_CR_VOS_1_5V (0x2 << 12)
+#define PWR_CR_VOS_1_8V (0x1 << 12)
+
/* PVD level selection */
-#define PWR_CR_PLS_2_2V (0x0 << 5)
-#define PWR_CR_PLS_2_3V (0x1 << 5)
-#define PWR_CR_PLS_2_4V (0x2 << 5)
-#define PWR_CR_PLS_2_5V (0x3 << 5)
-#define PWR_CR_PLS_2_6V (0x4 << 5)
-#define PWR_CR_PLS_2_7V (0x5 << 5)
-#define PWR_CR_PLS_2_8V (0x6 << 5)
-#define PWR_CR_PLS_2_9V (0x7 << 5)
+#define PWR_CR_PLS_1_9V (0x0 << 5)
+#define PWR_CR_PLS_2_1V (0x1 << 5)
+#define PWR_CR_PLS_2_3V (0x2 << 5)
+#define PWR_CR_PLS_2_5V (0x3 << 5)
+#define PWR_CR_PLS_2_7V (0x4 << 5)
+#define PWR_CR_PLS_2_9V (0x5 << 5)
+#define PWR_CR_PLS_3_1V (0x6 << 5)
+#define PWR_CR_PLS_PVD_IN (0x7 << 5)
+
+/* Control/status register */
+
+#define PWR_CSR_EWUP3_BIT 26
+#define PWR_CSR_EWUP2_BIT 25
+#define PWR_CSR_EWUP1_BIT 24
+#define PWR_CSR_REGLPF_BIT 5
+#define PWR_CSR_VOSF_BIT 4
+#define PWR_CSR_VREFINTRDYF_BIT 3
+#define PWR_CSR_PVDO_BIT 2
+#define PWR_CSR_SBF_BIT 1
+#define PWR_CSR_WUF_BIT 0
+
+#define PWR_CSR_VOSF BIT(PWR_CSR_VOSF_BIT)
+
#endif
View
190 libmaple/stm32l1/include/series/rcc.h
@@ -89,21 +89,21 @@ typedef struct rcc_reg_map {
#define RCC_CR_HSEBYP BIT(RCC_CR_HSEBYP_BIT)
#define RCC_CR_HSERDY BIT(RCC_CR_HSERDY_BIT)
#define RCC_CR_HSEON BIT(RCC_CR_HSEON_BIT)
+#define RCC_CR_MSIRDY BIT(RCC_CR_MSIRDY_BIT)
+#define RCC_CR_MSION BIT(RCC_CR_MSION_BIT)
#define RCC_CR_HSIRDY BIT(RCC_CR_HSIRDY_BIT)
#define RCC_CR_HSION BIT(RCC_CR_HSION_BIT)
/* Internal clock sources calibration register */
-#define RCC_CR_HSICAL (0xFF)
-#define RCC_CR_HSITRIM (0x1F << 8)
-#define RCC_CR_MSIRANGE (0x7 << 13)
-#define RCC_CR_MSICAL (0xFF << 16)
-#define RCC_CR_MSITRIM (0xFF << 24)
+#define RCC_ICSCR_HSICAL (0xFF)
+#define RCC_ICSCR_HSITRIM (0x1F << 8)
+#define RCC_ICSCR_MSIRANGE (0x7 << 13)
+#define RCC_ICSCR_MSICAL (0xFF << 16)
+#define RCC_ICSCR_MSITRIM (0xFF << 24)
/* Clock configuration register */
-// #define RCC_CFGR_USBPRE_BIT 22
-// #define RCC_CFGR_PLLXTPRE_BIT 17
#define RCC_CFGR_PLLSRC_BIT 16
#define RCC_CFGR_MCOPRE (0x7 << 28)
@@ -117,6 +117,59 @@ typedef struct rcc_reg_map {
#define RCC_CFGR_SWS (0x3 << 2)
#define RCC_CFGR_SW 0x3
+#define RCC_CFGR_MCOPRE_DIV_1 (0x0 << 28)
+#define RCC_CFGR_MCOPRE_DIV_2 (0x1 << 28)
+#define RCC_CFGR_MCOPRE_DIV_4 (0x2 << 28)
+#define RCC_CFGR_MCOPRE_DIV_8 (0x3 << 28)
+#define RCC_CFGR_MCOPRE_DIV_16 (0x4 << 28)
+
+#define RCC_CFGR_MCOSEL_DISABLED (0x0 << 24)
+#define RCC_CFGR_MCOSEL_SYSCLK (0x1 << 24)
+#define RCC_CFGR_MCOSEL_HSI (0x2 << 24)
+#define RCC_CFGR_MCOSEL_MSI (0x3 << 24)
+#define RCC_CFGR_MCOSEL_HSE (0x4 << 24)
+#define RCC_CFGR_MCOSEL_PLL (0x5 << 24)
+#define RCC_CFGR_MCOSEL_LSI (0x6 << 24)
+#define RCC_CFGR_MCOSEL_LSE (0x7 << 24)
+
+#define RCC_CFGR_PLLDIV_DIV_2 (0x1 << 22)
+#define RCC_CFGR_PLLDIV_DIV_3 (0x2 << 22)
+#define RCC_CFGR_PLLDIV_DIV_4 (0x3 << 22)
+
+#define RCC_CFGR_PLLMUL_MUL_3 (0x0 << 18)
+#define RCC_CFGR_PLLMUL_MUL_4 (0x1 << 18)
+#define RCC_CFGR_PLLMUL_MUL_6 (0x2 << 18)
+#define RCC_CFGR_PLLMUL_MUL_8 (0x3 << 18)
+#define RCC_CFGR_PLLMUL_MUL_12 (0x4 << 18)
+#define RCC_CFGR_PLLMUL_MUL_16 (0x5 << 18)
+#define RCC_CFGR_PLLMUL_MUL_24 (0x6 << 18)
+#define RCC_CFGR_PLLMUL_MUL_32 (0x7 << 18)
+#define RCC_CFGR_PLLMUL_MUL_48 (0x8 << 18)
+
+#define RCC_CFGR_PLLSRC_HSI 0x0
+#define RCC_CFGR_PLLSRC_HSE RCC_CFGR_PLLSRC
+
+/* Skipped: all the 0b0xx values meaning "not divided" */
+#define RCC_CFGR_PPRE2_AHB_DIV_2 (0x4 << 13)
+#define RCC_CFGR_PPRE2_AHB_DIV_4 (0x5 << 13)
+#define RCC_CFGR_PPRE2_AHB_DIV_8 (0x6 << 13)
+#define RCC_CFGR_PPRE2_AHB_DIV_16 (0x7 << 13)
+
+/* Skipped: all the 0b0xx values meaning "not divided" */
+#define RCC_CFGR_PPRE1_AHB_DIV_2 (0x4 << 10)
+#define RCC_CFGR_PPRE1_AHB_DIV_4 (0x5 << 10)
+#define RCC_CFGR_PPRE1_AHB_DIV_8 (0x6 << 10)
+#define RCC_CFGR_PPRE1_AHB_DIV_16 (0x7 << 10)
+
+/* Skipped: all the 0b0xxx values meaning "not divided" */
+#define RCC_CFGR_HPRE_SYSCLK_DIV_2 (0x8 << 4)
+#define RCC_CFGR_HPRE_SYSCLK_DIV_4 (0x9 << 4)
+#define RCC_CFGR_HPRE_SYSCLK_DIV_8 (0xA << 4)
+#define RCC_CFGR_HPRE_SYSCLK_DIV_16 (0xB << 4)
+#define RCC_CFGR_HPRE_SYSCLK_DIV_64 (0xC << 4)
+#define RCC_CFGR_HPRE_SYSCLK_DIV_128 (0xD << 4)
+#define RCC_CFGR_HPRE_SYSCLK_DIV_256 (0xE << 4)
+#define RCC_CFGR_HPRE_SYSCLK_DIV_512 (0xF << 4)
#define RCC_CFGR_SWS_PLL (0x3 << 2)
#define RCC_CFGR_SWS_HSE (0x2 << 2)
@@ -131,7 +184,7 @@ typedef struct rcc_reg_map {
/* Clock interrupt register */
#define RCC_CIR_CSSC_BIT 23
-#define RCC_CIR_MSIRDYC_BIT 20
+#define RCC_CIR_MSIRDYC_BIT 21
#define RCC_CIR_PLLRDYC_BIT 20
#define RCC_CIR_HSERDYC_BIT 19
#define RCC_CIR_HSIRDYC_BIT 18
@@ -152,7 +205,7 @@ typedef struct rcc_reg_map {
#define RCC_CIR_LSIRDYF_BIT 0
#define RCC_CIR_CSSC BIT(RCC_CIR_CSSC_BIT)
-#define RCC_CIR_MSERDYC BIT(RCC_CIR_mSERDYC_BIT)
+#define RCC_CIR_MSERDYC BIT(RCC_CIR_MSERDYC_BIT)
#define RCC_CIR_PLLRDYC BIT(RCC_CIR_PLLRDYC_BIT)
#define RCC_CIR_HSERDYC BIT(RCC_CIR_HSERDYC_BIT)
#define RCC_CIR_HSIRDYC BIT(RCC_CIR_HSIRDYC_BIT)
@@ -214,7 +267,6 @@ typedef struct rcc_reg_map {
/* APB1 peripheral reset register */
-
#define RCC_APB1RSTR_COMPRST_BIT 31
#define RCC_APB1RSTR_DACRST_BIT 29
#define RCC_APB1RSTR_PWRRST_BIT 28
@@ -446,6 +498,18 @@ typedef struct rcc_reg_map {
*/
/**
+ * @brief SYSCLK sources
+ * @see rcc_switch_sysclk()
+ */
+typedef enum rcc_sysclk_src {
+ RCC_CLKSRC_MSI = RCC_CFGR_SW_MSI,
+ RCC_CLKSRC_HSI = RCC_CFGR_SW_HSI,
+ RCC_CLKSRC_HSE = RCC_CFGR_SW_HSE,
+ RCC_CLKSRC_PLL = RCC_CFGR_SW_PLL,
+} rcc_sysclk_src;
+
+
+/**
* @brief Identifies bus and clock line for a peripheral.
*
* Also generally useful as a unique identifier for that peripheral
@@ -501,30 +565,30 @@ typedef enum rcc_clk_id {
* @brief Deprecated PLL multipliers, for rcc_clk_init().
*/
typedef enum rcc_pll_multiplier {
- RCC_PLLMUL_2 = (0x0 << 18),
- RCC_PLLMUL_3 = (0x1 << 18),
- RCC_PLLMUL_4 = (0x2 << 18),
- RCC_PLLMUL_5 = (0x3 << 18),
- RCC_PLLMUL_6 = (0x4 << 18),
- RCC_PLLMUL_7 = (0x5 << 18),
- RCC_PLLMUL_8 = (0x6 << 18),
- RCC_PLLMUL_9 = (0x7 << 18),
- RCC_PLLMUL_10 = (0x8 << 18),
- RCC_PLLMUL_11 = (0x9 << 18),
- RCC_PLLMUL_12 = (0xA << 18),
- RCC_PLLMUL_13 = (0xB << 18),
- RCC_PLLMUL_14 = (0xC << 18),
- RCC_PLLMUL_15 = (0xD << 18),
- RCC_PLLMUL_16 = (0xE << 18),
+ RCC_PLLMUL_3 = RCC_CFGR_PLLMUL_MUL_3,
+ RCC_PLLMUL_4 = RCC_CFGR_PLLMUL_MUL_4,
+ RCC_PLLMUL_6 = RCC_CFGR_PLLMUL_MUL_6,
+ RCC_PLLMUL_8 = RCC_CFGR_PLLMUL_MUL_8,
+ RCC_PLLMUL_12 = RCC_CFGR_PLLMUL_MUL_12,
+ RCC_PLLMUL_16 = RCC_CFGR_PLLMUL_MUL_16,
+ RCC_PLLMUL_24 = RCC_CFGR_PLLMUL_MUL_24,
+ RCC_PLLMUL_32 = RCC_CFGR_PLLMUL_MUL_32,
+ RCC_PLLMUL_48 = RCC_CFGR_PLLMUL_MUL_48
} rcc_pll_multiplier;
+typedef enum rcc_pll_divider {
+ RCC_PLLDIV_2 = RCC_CFGR_PLLDIV_DIV_2,
+ RCC_PLLDIV_3 = RCC_CFGR_PLLDIV_DIV_3,
+ RCC_PLLDIV_4 = RCC_CFGR_PLLDIV_DIV_4
+} rcc_pll_divider;
+
/**
* @brief PLL clock sources.
* @see rcc_configure_pll()
*/
typedef enum rcc_pllsrc {
- RCC_PLLSRC_HSE = (0x1 << 16),
- RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16)
+ RCC_PLLSRC_HSE = RCC_CFGR_PLLSRC,
+ RCC_PLLSRC_HSI = (0x0 << RCC_CFGR_PLLSRC_BIT)
} rcc_pllsrc;
typedef enum rcc_clk_domain {
@@ -533,39 +597,24 @@ typedef enum rcc_clk_domain {
RCC_AHB
} rcc_clk_domain;
-/**
- * Prescaler identifiers
- * @see rcc_set_prescaler()
- */
typedef enum rcc_prescaler {
- RCC_PRESCALER_AHB,
- RCC_PRESCALER_APB1,
+ RCC_PRESCALER_MCO,
RCC_PRESCALER_APB2,
- RCC_PRESCALER_USB,
- RCC_PRESCALER_ADC
+ RCC_PRESCALER_APB1,
+ RCC_PRESCALER_AHB
} rcc_prescaler;
-/**
- * ADC prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_adc_divider {
- RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14,
- RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14,
- RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14,
- RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14,
-} rcc_adc_divider;
/**
* APB1 prescaler dividers
* @see rcc_set_prescaler()
*/
typedef enum rcc_apb1_divider {
- RCC_APB1_HCLK_DIV_1 = 0x0 << 8,
- RCC_APB1_HCLK_DIV_2 = 0x4 << 8,
- RCC_APB1_HCLK_DIV_4 = 0x5 << 8,
- RCC_APB1_HCLK_DIV_8 = 0x6 << 8,
- RCC_APB1_HCLK_DIV_16 = 0x7 << 8,
+ RCC_APB1_HCLK_DIV_1 = 0x0 << 10,
+ RCC_APB1_HCLK_DIV_2 = RCC_CFGR_PPRE1_AHB_DIV_2,
+ RCC_APB1_HCLK_DIV_4 = RCC_CFGR_PPRE1_AHB_DIV_4,
+ RCC_APB1_HCLK_DIV_8 = RCC_CFGR_PPRE1_AHB_DIV_8,
+ RCC_APB1_HCLK_DIV_16 = RCC_CFGR_PPRE1_AHB_DIV_16,
} rcc_apb1_divider;
/**
@@ -573,11 +622,11 @@ typedef enum rcc_apb1_divider {
* @see rcc_set_prescaler()
*/
typedef enum rcc_apb2_divider {
- RCC_APB2_HCLK_DIV_1 = 0x0 << 11,
- RCC_APB2_HCLK_DIV_2 = 0x4 << 11,
- RCC_APB2_HCLK_DIV_4 = 0x5 << 11,
- RCC_APB2_HCLK_DIV_8 = 0x6 << 11,
- RCC_APB2_HCLK_DIV_16 = 0x7 << 11,
+ RCC_APB2_HCLK_DIV_1 = 0x0 << 13,
+ RCC_APB2_HCLK_DIV_2 = RCC_CFGR_PPRE2_AHB_DIV_2,
+ RCC_APB2_HCLK_DIV_4 = RCC_CFGR_PPRE2_AHB_DIV_4,
+ RCC_APB2_HCLK_DIV_8 = RCC_CFGR_PPRE2_AHB_DIV_8,
+ RCC_APB2_HCLK_DIV_16 = RCC_CFGR_PPRE2_AHB_DIV_16,
} rcc_apb2_divider;
/**
@@ -586,17 +635,17 @@ typedef enum rcc_apb2_divider {
*/
typedef enum rcc_ahb_divider {
RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4,
- RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4,
- RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4,
- RCC_AHB_SYSCLK_DIV_8 = 0xA << 4,
- RCC_AHB_SYSCLK_DIV_16 = 0xB << 4,
- RCC_AHB_SYSCLK_DIV_32 = 0xC << 4,
- RCC_AHB_SYSCLK_DIV_64 = 0xD << 4,
- RCC_AHB_SYSCLK_DIV_128 = 0xD << 4,
- RCC_AHB_SYSCLK_DIV_256 = 0xE << 4,
- RCC_AHB_SYSCLK_DIV_512 = 0xF << 4,
+ RCC_AHB_SYSCLK_DIV_2 = RCC_CFGR_HPRE_SYSCLK_DIV_2,
+ RCC_AHB_SYSCLK_DIV_4 = RCC_CFGR_HPRE_SYSCLK_DIV_4,
+ RCC_AHB_SYSCLK_DIV_8 = RCC_CFGR_HPRE_SYSCLK_DIV_8,
+ RCC_AHB_SYSCLK_DIV_16 = RCC_CFGR_HPRE_SYSCLK_DIV_16,
+ RCC_AHB_SYSCLK_DIV_64 = RCC_CFGR_HPRE_SYSCLK_DIV_64,
+ RCC_AHB_SYSCLK_DIV_128 = RCC_CFGR_HPRE_SYSCLK_DIV_128,
+ RCC_AHB_SYSCLK_DIV_256 = RCC_CFGR_HPRE_SYSCLK_DIV_256,
+ RCC_AHB_SYSCLK_DIV_512 = RCC_CFGR_HPRE_SYSCLK_DIV_512,
} rcc_ahb_divider;
+
/**
* @brief Available clock sources.
*/
@@ -608,12 +657,8 @@ typedef enum rcc_clk {
RCC_CR_HSEON_BIT), /**< High speed external. */
RCC_CLK_HSI = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
RCC_CR_HSION_BIT), /**< High speed internal. */
- RCC_CLK_LSE = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) |
- RCC_CSR_LSEON_BIT), /**< Low-speed external
- * (32.768 KHz). */
- RCC_CLK_LSI = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) |
- RCC_CSR_LSION_BIT), /**< Low-speed internal
- * (approximately 32 KHz). */
+ RCC_CLK_MSI = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
+ RCC_CR_MSION_BIT), /**< Medium-speed internal */
} rcc_clk;
/*
@@ -632,9 +677,10 @@ void rcc_clk_init(rcc_sysclk_src sysclk_src,
*
* @see struct rcc_pll_cfg.
*/
-typedef struct stm32f1_rcc_pll_data {
+typedef struct stm32l1_rcc_pll_data {
rcc_pll_multiplier pll_mul; /**< PLL multiplication factor. */
-} stm32f1_rcc_pll_data;
+ rcc_pll_divider pll_div; /**< PLL divide factor. */
+} stm32l1_rcc_pll_data;
#ifdef __cplusplus
}
View
4 libmaple/stm32l1/include/series/stm32.h
@@ -49,9 +49,9 @@ extern "C" {
* STM32F103 microcontrollers set below won't take effect.
*/
-#if defined(MCU_STM32L152RB)
+#if defined(MCU_STM32L152RB) || defined(MCU_STM32L151CB)
# define STM32_NR_GPIO_PORTS 6
-# define STM32_DELAY_US_MULT 10 //???
+# define STM32_DELAY_US_MULT 8 //???
# define STM32_SRAM_END ((void*)0x20004000)
# define NR_GPIO_PORTS STM32_NR_GPIO_PORTS
# define DELAY_US_MULT STM32_DELAY_US_MULT
View
34 libmaple/stm32l1/include/series/timer.h
@@ -27,11 +27,11 @@
/**
* @file stm32f1/include/series/timer.h
* @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief STM32F1 timer sub-header.
+ * @brief STM32L1 timer sub-header.
*/
-#ifndef _LIBMAPLE_STM32F1_TIMER_H_
-#define _LIBMAPLE_STM32F1_TIMER_H_
+#ifndef _LIBMAPLE_STM32L1_TIMER_H_
+#define _LIBMAPLE_STM32L1_TIMER_H_
#include <libmaple/libmaple_types.h>
@@ -63,38 +63,27 @@ typedef struct timer_gen_reg_map {
__io uint32 DMAR; /**< DMA address for full transfer */
} timer_gen_reg_map;
-struct timer_adv_reg_map;
struct timer_gen_reg_map;
struct timer_bas_reg_map;
/** Timer 1 register map base pointer */
-#define TIMER1_BASE ((struct timer_adv_reg_map*)0x40012C00)
+#define TIMER1_BASE ((struct timer_gen_reg_map*)0x40012C00)
/** Timer 2 register map base pointer */
#define TIMER2_BASE ((struct timer_gen_reg_map*)0x40000000)
/** Timer 3 register map base pointer */
#define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400)
/** Timer 4 register map base pointer */
#define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800)
-/** Timer 5 register map base pointer */
-#define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00)
/** Timer 6 register map base pointer */
#define TIMER6_BASE ((struct timer_bas_reg_map*)0x40001000)
/** Timer 7 register map base pointer */
#define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400)
-/** Timer 8 register map base pointer */
-#define TIMER8_BASE ((struct timer_adv_reg_map*)0x40013400)
/** Timer 9 register map base pointer */
-#define TIMER9_BASE ((struct timer_gen_reg_map*)0x40014C00)
+#define TIMER9_BASE ((struct timer_gen_reg_map*)0x40010800)
/** Timer 10 register map base pointer */
-#define TIMER10_BASE ((struct timer_gen_reg_map*)0x40015000)
+#define TIMER10_BASE ((struct timer_gen_reg_map*)0x40010C00)
/** Timer 11 register map base pointer */
-#define TIMER11_BASE ((struct timer_gen_reg_map*)0x40015400)
-/** Timer 12 register map base pointer */
-#define TIMER12_BASE ((struct timer_gen_reg_map*)0x40001800)
-/** Timer 13 register map base pointer */
-#define TIMER13_BASE ((struct timer_gen_reg_map*)0x40001C00)
-/** Timer 14 register map base pointer */
-#define TIMER14_BASE ((struct timer_gen_reg_map*)0x40002000)
+#define TIMER11_BASE ((struct timer_gen_reg_map*)0x40011000)
/*
* Device pointers
@@ -111,19 +100,10 @@ extern struct timer_dev *TIMER1;
extern struct timer_dev *TIMER2;
extern struct timer_dev *TIMER3;
extern struct timer_dev *TIMER4;
-#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
-extern struct timer_dev *TIMER5;
extern struct timer_dev *TIMER6;
extern struct timer_dev *TIMER7;
-extern struct timer_dev *TIMER8;
-#endif
-#ifdef STM32_XL_DENSITY
extern struct timer_dev *TIMER9;
extern struct timer_dev *TIMER10;
extern struct timer_dev *TIMER11;
-extern struct timer_dev *TIMER12;
-extern struct timer_dev *TIMER13;
-extern struct timer_dev *TIMER14;
-#endif
#endif
View
95 libmaple/stm32l1/isrs_performance.S
@@ -134,33 +134,33 @@ __default_handler:
.weak __irq_adc
.globl __irq_adc
.set __irq_adc, __default_handler
- .weak __irq_usb_hp_can_tx
- .globl __irq_usb_hp_can_tx
- .set __irq_usb_hp_can_tx, __default_handler
- .weak __irq_usb_lp_can_rx0
- .globl __irq_usb_lp_can_rx0
- .set __irq_usb_lp_can_rx0, __default_handler
- .weak __irq_can_rx1
- .globl __irq_can_rx1
- .set __irq_can_rx1, __default_handler
- .weak __irq_can_sce
- .globl __irq_can_sce
- .set __irq_can_sce, __default_handler
+ .weak __irq_usb_hp
+ .globl __irq_usb_hp
+ .set __irq_usb_hp, __default_handler
+ .weak __irq_usb_lp
+ .globl __irq_usb_lp
+ .set __irq_usb_lp, __default_handler
+ .weak __irq_dac
+ .globl __irq_dac
+ .set __irq_dac, __default_handler
+ .weak __irq_comp
+ .globl __irq_comp
+ .set __irq_comp, __default_handler
.weak __irq_exti9_5
.globl __irq_exti9_5
.set __irq_exti9_5, __default_handler
- .weak __irq_tim1_brk
- .globl __irq_tim1_brk
- .set __irq_tim1_brk, __default_handler
- .weak __irq_tim1_up
- .globl __irq_tim1_up
- .set __irq_tim1_up, __default_handler
- .weak __irq_tim1_trg_com
- .globl __irq_tim1_trg_com
- .set __irq_tim1_trg_com, __default_handler
- .weak __irq_tim1_cc
- .globl __irq_tim1_cc
- .set __irq_tim1_cc, __default_handler
+ .weak __irq_lcd
+ .globl __irq_lcd
+ .set __irq_lcd, __default_handler
+ .weak __irq_tim9
+ .globl __irq_tim9
+ .set __irq_tim9, __default_handler
+ .weak __irq_tim10
+ .globl __irq_tim10
+ .set __irq_tim10, __default_handler
+ .weak __irq_tim11
+ .globl __irq_tim11
+ .set __irq_tim11, __default_handler
.weak __irq_tim2
.globl __irq_tim2
.set __irq_tim2, __default_handler
@@ -206,56 +206,9 @@ __default_handler:
.weak __irq_usbwakeup
.globl __irq_usbwakeup
.set __irq_usbwakeup, __default_handler
-#if defined (STM32_HIGH_DENSITY)
- .weak __irq_tim8_brk
- .globl __irq_tim8_brk
- .set __irq_tim8_brk, __default_handler
- .weak __irq_tim8_up
- .globl __irq_tim8_up
- .set __irq_tim8_up, __default_handler
- .weak __irq_tim8_trg_com
- .globl __irq_tim8_trg_com
- .set __irq_tim8_trg_com, __default_handler
- .weak __irq_tim8_cc
- .globl __irq_tim8_cc
- .set __irq_tim8_cc, __default_handler
- .weak __irq_adc3
- .globl __irq_adc3
- .set __irq_adc3, __default_handler
- .weak __irq_fsmc
- .globl __irq_fsmc
- .set __irq_fsmc, __default_handler
- .weak __irq_sdio
- .globl __irq_sdio
- .set __irq_sdio, __default_handler
- .weak __irq_tim5
- .globl __irq_tim5
- .set __irq_tim5, __default_handler
- .weak __irq_spi3
- .globl __irq_spi3
- .set __irq_spi3, __default_handler
- .weak __irq_uart4
- .globl __irq_uart4
- .set __irq_uart4, __default_handler
- .weak __irq_uart5
- .globl __irq_uart5
- .set __irq_uart5, __default_handler
.weak __irq_tim6
.globl __irq_tim6
.set __irq_tim6, __default_handler
.weak __irq_tim7
.globl __irq_tim7
.set __irq_tim7, __default_handler
- .weak __irq_dma2_channel1
- .globl __irq_dma2_channel1
- .set __irq_dma2_channel1, __default_handler
- .weak __irq_dma2_channel2
- .globl __irq_dma2_channel2
- .set __irq_dma2_channel2, __default_handler
- .weak __irq_dma2_channel3
- .globl __irq_dma2_channel3
- .set __irq_dma2_channel3, __default_handler
- .weak __irq_dma2_channel4_5
- .globl __irq_dma2_channel4_5
- .set __irq_dma2_channel4_5, __default_handler
-#endif /* STM32_HIGH_DENSITY */
View
7 libmaple/stm32l1/rcc.c
@@ -134,16 +134,17 @@ void rcc_clk_init(rcc_sysclk_src sysclk_src,
* to a valid struct stm32f1_rcc_pll_data.
*/
void rcc_configure_pll(rcc_pll_cfg *pll_cfg) {
- stm32f1_rcc_pll_data *data = pll_cfg->data;
+ stm32l1_rcc_pll_data *data = pll_cfg->data;
rcc_pll_multiplier pll_mul = data->pll_mul;
+ rcc_pll_divider pll_div = data->pll_div;
uint32 cfgr;
/* Check that the PLL is disabled. */
ASSERT_FAULT(!rcc_is_clk_on(RCC_CLK_PLL));
cfgr = RCC_BASE->CFGR;
- cfgr &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL);
- cfgr |= pll_cfg->pllsrc | pll_mul;
+ cfgr &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV);
+ cfgr |= pll_cfg->pllsrc | pll_mul | pll_div;
RCC_BASE->CFGR = cfgr;
}
View
114 libmaple/stm32l1/timer.c
@@ -25,24 +25,9 @@
*****************************************************************************/
/**
- * @file libmaple/stm32f1/timer.c
+ * @file libmaple/stm32l1/timer.c
* @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief STM32F1 timer support.
- */
-
-/* Notes:
- *
- * - We use STM32F1 density test macros throughout to avoid defining
- * symbols or linking in code that would use timers that are
- * unavailable in a given density. For example, TIM5 doesn't exist
- * on medium-density, and TIM9 doesn't exist on high-density, so we
- * don't define or use TIM5 when being compiled for medium-density,
- * and similarly for TIM9 and high-density.
- *
- * This makes a mess, but helps avoid bloat and ensures backwards
- * compatibility. Since the mess is manageable and there don't seem
- * to be any plans on ST's part to add new STM32F1 lines or
- * densities, we'll live with it.
+ * @brief STM32L1 timer support.
*/
#include <libmaple/timer.h>
@@ -54,12 +39,12 @@
* Defer to the timer_private API.
*/
-static DECLARE_ADVANCED_TIMER(timer1, 1);
+static DECLARE_GENERAL_TIMER(timer1, 1);
static DECLARE_GENERAL_TIMER(timer2, 2);
static DECLARE_GENERAL_TIMER(timer3, 3);
static DECLARE_GENERAL_TIMER(timer4, 4);
-/** Timer 1 device (advanced) */
+/** Timer 1 device (general-purpose) */
timer_dev *TIMER1 = &timer1;
/** Timer 2 device (general-purpose) */
timer_dev *TIMER2 = &timer2;
@@ -68,35 +53,19 @@ timer_dev *TIMER3 = &timer3;
/** Timer 4 device (general-purpose) */
timer_dev *TIMER4 = &timer4;
-#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
-static DECLARE_GENERAL_TIMER(timer5, 5);
static DECLARE_BASIC_TIMER(timer6, 6);
static DECLARE_BASIC_TIMER(timer7, 7);
-static DECLARE_ADVANCED_TIMER(timer8, 8);
-
-/** Timer 5 device (general-purpose) */
-timer_dev *TIMER5 = &timer5;
/** Timer 6 device (basic) */
timer_dev *TIMER6 = &timer6;
/** Timer 7 device (basic) */
timer_dev *TIMER7 = &timer7;
-/** Timer 8 device (advanced) */
-timer_dev *TIMER8 = &timer8;
-#endif /* defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) */
-#ifdef STM32_XL_DENSITY
/* TIM9 has UIE, CC1IE, CC2IE, TIE bits in DIER. */
static DECLARE_RESTRICTED_GENERAL_TIMER(timer9, 9, TIMER_DIER_TIE_BIT);
/* TIM10 has UIE, CC1IE. */
static DECLARE_RESTRICTED_GENERAL_TIMER(timer10, 10, TIMER_DIER_CC1IE_BIT);
/* TIM11 has UIE, CC1IE. */
static DECLARE_RESTRICTED_GENERAL_TIMER(timer11, 11, TIMER_DIER_CC1IE_BIT);
-/* TIM12 has UIE, CC1IE, CC2IE, TIE. */
-static DECLARE_RESTRICTED_GENERAL_TIMER(timer12, 12, TIMER_DIER_TIE_BIT);
-/* TIM13 has UIE, CC1IE. */
-static DECLARE_RESTRICTED_GENERAL_TIMER(timer13, 13, TIMER_DIER_CC1IE_BIT);
-/* TIM14 has UIE, CC1IE. */
-static DECLARE_RESTRICTED_GENERAL_TIMER(timer14, 14, TIMER_DIER_CC1IE_BIT);
/** Timer 9 device (general-purpose) */
timer_dev *TIMER9 = &timer9;
@@ -104,13 +73,6 @@ timer_dev *TIMER9 = &timer9;
timer_dev *TIMER10 = &timer10;
/** Timer 11 device (general-purpose) */
timer_dev *TIMER11 = &timer11;
-/** Timer 12 device (general-purpose) */
-timer_dev *TIMER12 = &timer12;
-/** Timer 13 device (general-purpose) */
-timer_dev *TIMER13 = &timer13;
-/** Timer 14 device (general-purpose) */
-timer_dev *TIMER14 = &timer14;
-#endif /* STM32_XL_DENSITY */
/*
* Routines
@@ -125,20 +87,11 @@ void timer_foreach(void (*fn)(timer_dev*)) {
fn(TIMER2);
fn(TIMER3);
fn(TIMER4);
-#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
- fn(TIMER5);
fn(TIMER6);
fn(TIMER7);
- fn(TIMER8);
-#endif
-#ifdef STM32_XL_DENSITY
fn(TIMER9);
fn(TIMER10);
fn(TIMER11);
- fn(TIMER12);
- fn(TIMER13);
- fn(TIMER14);
-#endif
}
/*
@@ -146,37 +99,8 @@ void timer_foreach(void (*fn)(timer_dev*)) {
*
* Defer to the timer_private dispatch API.
*
- * FIXME: The names of these handlers are inaccurate since XL-density
- * devices came out. Update these to match the STM32F2 names, maybe
- * using some weak symbol magic to preserve backwards compatibility if
- * possible.
*/
-void __irq_tim1_brk(void) {
- dispatch_adv_brk(TIMER1);
-#ifdef STM32_XL_DENSITY
- dispatch_tim_9_12(TIMER9);
-#endif
-}
-
-void __irq_tim1_up(void) {
- dispatch_adv_up(TIMER1);
-#ifdef STM32_XL_DENSITY
- dispatch_tim_10_11_13_14(TIMER10);
-#endif
-}
-
-void __irq_tim1_trg_com(void) {
- dispatch_adv_trg_com(TIMER1);
-#ifdef STM32_XL_DENSITY
- dispatch_tim_10_11_13_14(TIMER11);
-#endif
-}
-
-void __irq_tim1_cc(void) {
- dispatch_adv_cc(TIMER1);
-}
-
void __irq_tim2(void) {
dispatch_general(TIMER2);
}
@@ -189,11 +113,6 @@ void __irq_tim4(void) {
dispatch_general(TIMER4);
}
-#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
-void __irq_tim5(void) {
- dispatch_general(TIMER5);
-}
-
void __irq_tim6(void) {
dispatch_basic(TIMER6);
}
@@ -202,28 +121,15 @@ void __irq_tim7(void) {
dispatch_basic(TIMER7);
}
-void __irq_tim8_brk(void) {
- dispatch_adv_brk(TIMER8);
-#ifdef STM32_XL_DENSITY
- dispatch_tim_9_12(TIMER12);
-#endif
+void __irq_tim9(void) {
+ dispatch_general(TIMER9);
}
-void __irq_tim8_up(void) {
- dispatch_adv_up(TIMER8);
-#ifdef STM32_XL_DENSITY
- dispatch_tim_10_11_13_14(TIMER13);
-#endif
+void __irq_tim10(void) {
+ dispatch_general(TIMER10);
}
-void __irq_tim8_trg_com(void) {
- dispatch_adv_trg_com(TIMER8);
-#ifdef STM32_XL_DENSITY
- dispatch_tim_10_11_13_14(TIMER14);
-#endif
+void __irq_tim11(void) {
+ dispatch_general(TIMER11);
}
-void __irq_tim8_cc(void) {
- dispatch_adv_cc(TIMER8);
-}
-#endif /* defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) */
View
35 libmaple/stm32l1/vector_table_performance.S
@@ -24,7 +24,7 @@
* SOFTWARE.
*****************************************************************************/
-/* STM32F1 vector table */
+/* STM32L1 vector table */
.section ".stm32.interrupt_vector"
@@ -69,15 +69,15 @@ __stm32_vector_table:
.long __irq_dma1_channel6
.long __irq_dma1_channel7
.long __irq_adc
- .long __irq_usb_hp_can_tx
- .long __irq_usb_lp_can_rx0
- .long __irq_can_rx1
- .long __irq_can_sce
+ .long __irq_usb_hp
+ .long __irq_usb_lp
+ .long __irq_dac
+ .long __irq_comp
.long __irq_exti9_5
- .long __irq_tim1_brk
- .long __irq_tim1_up
- .long __irq_tim1_trg_com
- .long __irq_tim1_cc
+ .long __irq_lcd
+ .long __irq_tim9
+ .long __irq_tim10
+ .long __irq_tim11
.long __irq_tim2
.long __irq_tim3
.long __irq_tim4
@@ -93,24 +93,7 @@ __stm32_vector_table:
.long __irq_exti15_10
.long __irq_rtcalarm
.long __irq_usbwakeup
-#if defined (STM32_HIGH_DENSITY)
- .long __irq_tim8_brk
- .long __irq_tim8_up
- .long __irq_tim8_trg_com
- .long __irq_tim8_cc
- .long __irq_adc3
- .long __irq_fsmc
- .long __irq_sdio
- .long __irq_tim5
- .long __irq_spi3
- .long __irq_uart4
- .long __irq_uart5
.long __irq_tim6
.long __irq_tim7
- .long __irq_dma2_channel1
- .long __irq_dma2_channel2
- .long __irq_dma2_channel3
- .long __irq_dma2_channel4_5
-#endif /* STM32_HIGH_DENSITY */
.size __stm32_vector_table, . - __stm32_vector_table
View
24 support/ld/mchck/flash.ld
@@ -0,0 +1,24 @@
+/*
+ * mc hck (STM32L151CBT6, medium density) linker script for Flash builds.
+ */
+
+/*
+ * Define memory spaces.
+ */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
+ rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+}
+
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+/*
+ * Define the rest of the sections
+ */
+_FLASH_BUILD = 1;
+
+INCLUDE common.inc
View
24 support/ld/mchck/jtag.ld
@@ -0,0 +1,24 @@
+/*
+ * mc hck (STM32L151CBT6, medium density) linker script for JTAG (bare
+ * metal, no bootloader) builds.
+ */
+
+/*
+ * Define memory spaces.
+ */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
+ rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+}
+
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+/*
+ * Define the rest of the sections
+ */
+_FLASH_BUILD = 1;
+INCLUDE common.inc
View
22 support/ld/mchck/ram.ld
@@ -0,0 +1,22 @@
+/*
+ * mc hck (STM32L151CBT6, medium density) linker script for RAM builds.
+ */
+
+/*
+ * Define memory spaces.
+ */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
+ rom (rx) : ORIGIN = 0x08000000, LENGTH = 0K
+}
+
+REGION_ALIAS("REGION_TEXT", ram);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", ram);
+
+/*
+ * Define the rest of the sections
+ */
+INCLUDE common.inc
View
5 support/make/board-includes/mchck.mk
@@ -0,0 +1,5 @@
+MCU := STM32L151CB
+PRODUCT_ID := 0003
+ERROR_LED_PORT := GPIOC
+ERROR_LED_PIN := 13
+MCU_SERIES := stm32l1
View
2  wirish/boards.cpp
@@ -62,7 +62,7 @@ static void setup_adcs(void);
void init(void) {
// setup_flash();
-// setup_clocks();
+ wirish::priv::board_setup_clocks();
// setup_nvic();
// systick_init(SYSTICK_RELOAD_VAL);
wirish::priv::board_setup_gpio();
View
90 wirish/boards/mchck/board.cpp
@@ -0,0 +1,90 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file wirish/boards/mchck/board.cpp
+ * @author Anton Eltchaninov <anton.eltchaninov@gmail.com>
+ * @brief mc hck board file.
+ */
+
+#include <board/board.h>
+
+#include <libmaple/gpio.h>
+#include <libmaple/timer.h>
+#include <wirish/wirish_types.h>
+
+void boardInit(void) {
+// afio_cfg_debug_ports(AFIO_DEBUG_SW_ONLY);
+}
+
+extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
+
+ {GPIOA, TIMER9, ADC1, 3, 2, 3}, /* D0/PA3 */
+ {GPIOA, TIMER9, ADC1, 2, 1, 2}, /* D1/PA2 */
+ {GPIOA, NULL, ADC1, 0, 0, 0}, /* D2/PA0 */
+ {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D3/PA1 */
+ {GPIOB, TIMER3, NULL, 5, 2, ADCx}, /* D4/PB5 */
+ {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D5/PB6 */
+ {GPIOA, NULL, NULL, 8, 0, ADCx}, /* D6/PA8 */
+ {GPIOA, NULL, NULL, 9, 0, ADCx}, /* D7/PA9 */
+ {GPIOA, NULL, NULL, 10, 0, ADCx}, /* D8/PA10 */
+ {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D9/PB7 */
+ {GPIOA, NULL, ADC1, 4, 0, 4}, /* D10/PA4 */
+ {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D11/PA7 */
+ {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D12/PA6 */
+ {GPIOA, NULL, ADC1, 5, 0, 5}, /* D13/PA5 */
+ {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D14/PB8 */
+ {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D15/PC13 (LED) */
+ {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D16/PC14 */
+ {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D17/PC15 */
+ {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D18/PB9 */
+ {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D19/PB0 */
+ {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D20/PB1 */
+ {GPIOB, TIMER2, NULL, 10, 3, ADCx}, /* D21/PB10 */
+ {GPIOB, TIMER2, NULL, 11, 4, ADCx}, /* D22/PB11 */
+ {GPIOB,TIMER10, ADC1, 12, 1, 18}, /* D23/PB12 */
+ {GPIOB, TIMER9, ADC1, 13, 1, 19}, /* D24/PB13 */
+ {GPIOB, NULL, ADC1, 14, 0, 20}, /* D25/PB14 */
+ {GPIOB,TIMER11, ADC1, 15, 1, 21}, /* D26/PB15 */
+ {GPIOA, NULL, NULL, 11, 0, ADCx}, /* D27/PA11 */
+ {GPIOA, NULL, NULL, 12, 0, ADCx}, /* D28/PA12 */
+ {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D29/PA15 */
+ {GPIOB, NULL, NULL, 2, 0, ADCx}, /* D30/PB2 */
+ {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D31/PB3 */
+ {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D32/PB4 */
+};
+
+extern const uint8 boardPWMPins[] __FLASH__ = {
+ 0, 1, 3, 4, 5, 9, 11, 12, 14, 18, 19, 20, 21, 22, 23, 24, 26
+};
+
+extern const uint8 boardADCPins[] __FLASH__ = {
+ 0, 1, 2, 3, 10, 11, 12, 13, 19, 20, 23, 24, 25, 26
+};
+
+extern const uint8 boardUsedPins[] __FLASH__ = {
+ BOARD_LED_PIN
+};
View
87 wirish/boards/mchck/include/board/board.h
@@ -0,0 +1,87 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file wirish/boards/mchck/include/board/board.h
+ * @author Anton Eltchaninov <anton.eltchaninov@gmail.com>
+ * @brief mc hck board header.
+ */
+
+#ifndef _BOARD_MCHCK_H_
+#define _BOARD_MCHCK_H_
+
+#define BOARD_RCC_PLLMUL RCC_PLLMUL_4
+
+#define CYCLES_PER_MICROSECOND 32
+#define SYSTICK_RELOAD_VAL 31999 /* takes a cycle to reload */
+
+#define BOARD_LED_PIN 15 /* led on PC13 */
+#define BOARD_BUTTON_PIN 30 /* dummy, PB2(BOOT1) */
+
+
+/* Number of USARTs/UARTs whose pins are broken out to headers */
+#define BOARD_NR_USARTS 3
+
+/* Default USART pin numbers (not considering AFIO remap) */
+#define BOARD_USART1_TX_PIN 7
+#define BOARD_USART1_RX_PIN 8
+#define BOARD_USART2_TX_PIN 1
+#define BOARD_USART2_RX_PIN 0
+#define BOARD_USART3_TX_PIN 29
+#define BOARD_USART3_RX_PIN 30
+
+/* Number of SPI ports */
+#define BOARD_NR_SPI 2
+
+/* Default SPI pin numbers (not considering AFIO remap) */
+#define BOARD_SPI1_NSS_PIN 10
+#define BOARD_SPI1_MOSI_PIN 11
+#define BOARD_SPI1_MISO_PIN 12
+#define BOARD_SPI1_SCK_PIN 13
+#define BOARD_SPI2_NSS_PIN 31
+#define BOARD_SPI2_MOSI_PIN 34
+#define BOARD_SPI2_MISO_PIN 33
+#define BOARD_SPI2_SCK_PIN 32
+
+/* Total number of GPIO pins that are broken out to headers and
+ * intended for general use. */
+#define BOARD_NR_GPIO_PINS 33
+
+/* Number of pins capable of PWM output */
+#define BOARD_NR_PWM_PINS 15
+
+/* Number of pins capable of ADC conversion */
+#define BOARD_NR_ADC_PINS 15
+
+/* Number of pins already connected to external hardware. */
+#define BOARD_NR_USED_PINS 2
+
+/* USB configuration. BOARD_USB_DISC_DEV is the GPIO port containing
+ * the USB_DISC pin, and BOARD_USB_DISC_BIT is that pin's bit. */
+#define BOARD_USB_DISC_DEV GPIOC
+#define BOARD_USB_DISC_BIT 12
+
+#endif
View
3  wirish/boards_private.h
@@ -39,6 +39,8 @@
#include <libmaple/rcc.h>
#include <libmaple/adc.h>
+#include <libmaple/pwr.h>
+#include <libmaple/flash.h>
namespace wirish {
namespace priv {
@@ -60,6 +62,7 @@ namespace wirish {
void board_setup_gpio(void);
void board_setup_timers(void);
void board_setup_usb(void);
+ void board_setup_clocks(void);
}
}
View
4 wirish/include/wirish/wirish_debug.h
@@ -43,7 +43,7 @@
* @see enableDebugPorts()
*/
static inline void disableDebugPorts(void) {
- afio_cfg_debug_ports(AFIO_DEBUG_NONE);
+//??? afio_cfg_debug_ports(AFIO_DEBUG_NONE);
}
/**
@@ -55,7 +55,7 @@ static inline void disableDebugPorts(void) {
* @see disableDebugPorts()
*/
static inline void enableDebugPorts(void) {
- afio_cfg_debug_ports(AFIO_DEBUG_FULL_SWJ);
+//??? afio_cfg_debug_ports(AFIO_DEBUG_FULL_SWJ);
}
#endif
View
2  wirish/rules.mk
@@ -29,11 +29,11 @@ cppSRCS_$(d) += wirish_math.cpp \
wirish_analog.cpp \
wirish_time.cpp \
pwm.cpp \
- ext_interrupts.cpp \
wirish_digital.cpp \
HardwareSerial.cpp \
HardwareSPI.cpp \
HardwareTimer.cpp
+# ext_interrupts.cpp \
ifneq ($(BOARD), VLDiscovery)
# cppSRCS_$(d) += usb_serial.cpp
View
67 wirish/stm32l1/boards_setup.cpp
@@ -25,11 +25,11 @@
*****************************************************************************/
/**
- * @file wirish/stm32f1/boards_setup.cpp
+ * @file wirish/stm32l1/boards_setup.cpp
* @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief STM32F1 chip setup.
+ * @brief STM32L1 chip setup.
*
- * This file controls how init() behaves on the STM32F1. Be very
+ * This file controls how init() behaves on the STM32L1. Be very
* careful when changing anything here. Many of these values depend
* upon each other.
*/
@@ -51,21 +51,72 @@
#define BOARD_RCC_PLLMUL RCC_PLLMUL_4
#endif
+#ifndef BOARD_RCC_PLLDIV
+#define BOARD_RCC_PLLDIV RCC_PLLDIV_2
+#endif
+
/* FIXME: Reintroduce all "#if 0"'ed blocks once libmaple provides
* these definitions again. */
namespace wirish {
namespace priv {
- static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
- rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
- adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
+ static stm32l1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL, BOARD_RCC_PLLDIV};
+ rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI, &pll_data};
+ adc_prescaler w_adc_pre = ADC_PRE_DIV_1;
adc_smp_rate w_adc_smp = ADC_SMPR_55_5;
static void config_timer(timer_dev*);
+ void board_setup_clocks(void) {
+ // Turn off and reset the clock subsystems we'll be using.
+
+ rcc_turn_on_clk(RCC_CLK_MSI);
+ RCC_BASE->CFGR &= ~(RCC_CFGR_SW | RCC_CFGR_PPRE2 | RCC_CFGR_PPRE1 | RCC_CFGR_HPRE | RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE);
+ rcc_turn_off_clk(RCC_CLK_HSI);
+ rcc_turn_off_clk(RCC_CLK_HSE);
+ rcc_turn_off_clk(RCC_CLK_PLL);
+ rcc_disable_css();
+ RCC_BASE->CR &= ~(RCC_CR_HSEBYP);
+ wirish::priv::board_reset_pll();
+
+ // Clear clock readiness interrupt flags and turn off clock
+ // readiness interrupts.
+ RCC_BASE->CIR = 0x00000000;
+
+ rcc_turn_on_clk(RCC_CLK_HSI);
+ while (!rcc_is_clk_ready(RCC_CLK_HSI))
+ ;
+
+ FLASH_BASE->ACR |= FLASH_ACR_ACC64;
+ FLASH_BASE->ACR |= FLASH_ACR_PRFTEN;
+ FLASH_BASE->ACR |= FLASH_ACR_LATENCY;
+
+ // Enable power control
+ RCC_BASE->APB1ENR |= RCC_APB1ENR_PWREN;
+
+ // Set 1.8 V
+ PWR_BASE->CR &= ~PWR_CR_VOS;
+ PWR_BASE->CR |= PWR_CR_VOS_1_8V;
+ while((PWR_BASE->CSR & PWR_CSR_VOSF))
+ ;
+
+ // Configure AHBx, APBx, etc. prescalers and the main PLL.
+ wirish::priv::board_setup_clock_prescalers();
+ rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
+
+ // Enable the PLL, and wait until it's ready.
+ rcc_turn_on_clk(RCC_CLK_PLL);
+ while (!rcc_is_clk_ready(RCC_CLK_PLL))
+ ;
+
+
+ // Finally, switch to the now-ready PLL as the main clock source.
+ rcc_switch_sysclk(RCC_CLKSRC_PLL);
+ }
+
void board_reset_pll(void) {
- // TODO
+ RCC_BASE->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV);
}
void board_setup_clock_prescalers(void) {
@@ -78,7 +129,7 @@ namespace wirish {
gpio_init_all();
// Initialize AFIO here, too, so peripheral remaps and external
// interrupts work out of the box.
- afio_init();
+//??? afio_init();
}
void board_setup_timers(void) {
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