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  4. Blink an LED on an FPGA in VHDL using ghdl, yosys and nextpnr

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361 contributions in the last year

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Contribution activity

March 2021

Created 1 repository

Created a pull request in The-OpenROAD-Project/OpenROAD that received 2 comments

Remove cts_max_slew/cts_max_cap

+0 −15 2 comments
Opened 1 other pull request in 1 repository
The-OpenROAD-Project/OpenROAD-flow-scripts
1 open

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